JPS5528107A - Trnsmission and reception method of signal - Google Patents

Trnsmission and reception method of signal

Info

Publication number
JPS5528107A
JPS5528107A JP9894278A JP9894278A JPS5528107A JP S5528107 A JPS5528107 A JP S5528107A JP 9894278 A JP9894278 A JP 9894278A JP 9894278 A JP9894278 A JP 9894278A JP S5528107 A JPS5528107 A JP S5528107A
Authority
JP
Japan
Prior art keywords
signal
control
operation mode
microprocessor
logic level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9894278A
Other languages
Japanese (ja)
Inventor
Shinji Tachika
Haruo Wakabayashi
Takashi Tojiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP9894278A priority Critical patent/JPS5528107A/en
Publication of JPS5528107A publication Critical patent/JPS5528107A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To transmit and receive the signal in suitable logic level depending on the status of the controlled units, by designating the signal operation mode inputted to the control unit with microprogram, when the signal of logic level is transferred to the controlled unit from the control unit.
CONSTITUTION: The data channel unit 1 transfers the control word to the register 4a in the microprocessor 4 with the gate signal 9 and the operation mode control signal 14, when the one control word is read in the data buffer register 3 with the gate signal. The microprocessor 4 has the register 4b storing the control words for polarity inversion and executes logical operation with the operation circuit 4c for the control words of the registers 4a and 4b with the operation mode control signal 14. For example, when conversion is made from the information 30 to the information 31, several times of logic operations are made in the microprocessor with the operation mode control signal 14. Thus, the signal can be transmitted and received in a given logic level.
COPYRIGHT: (C)1980,JPO&Japio
JP9894278A 1978-08-14 1978-08-14 Trnsmission and reception method of signal Pending JPS5528107A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9894278A JPS5528107A (en) 1978-08-14 1978-08-14 Trnsmission and reception method of signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9894278A JPS5528107A (en) 1978-08-14 1978-08-14 Trnsmission and reception method of signal

Publications (1)

Publication Number Publication Date
JPS5528107A true JPS5528107A (en) 1980-02-28

Family

ID=14233156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9894278A Pending JPS5528107A (en) 1978-08-14 1978-08-14 Trnsmission and reception method of signal

Country Status (1)

Country Link
JP (1) JPS5528107A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208559A (en) * 1985-03-13 1986-09-16 Kawaguchiko Seimitsu Kk Input and output interface circuit for printer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61208559A (en) * 1985-03-13 1986-09-16 Kawaguchiko Seimitsu Kk Input and output interface circuit for printer

Similar Documents

Publication Publication Date Title
JPS54100634A (en) Computer
JPS5570783A (en) Sound information clock
JPS5528107A (en) Trnsmission and reception method of signal
JPS57130150A (en) Register control system
JPS573126A (en) Input and output controlling system
JPS55136753A (en) Compressed data recovery system
JPS5247329A (en) Data processing unit
JPS5478635A (en) Data transfer control circuit
JPS5759261A (en) Information processor
JPS5214323A (en) Shift register data transfer control system
JPS5665250A (en) Information processing
JPS5721146A (en) Data transmission system
JPS57147749A (en) Picture data transfer device
JPS56114055A (en) Bulk transfer speed converter
JPS56114026A (en) Data processor
JPS5445545A (en) Control system for input and output interface
JPS5488749A (en) Information processor
JPS57100536A (en) Data buffer device
JPS57209569A (en) Memory access device in vector processor system
JPS5652429A (en) Interface circuit of input/output device
JPS5755447A (en) Data converting circuit
JPS53113438A (en) Data transfer unit
JPS55108038A (en) Information renewal system for input monitor memory
JPS5498133A (en) Input/output control system
JPS5541560A (en) Data transfer system of variable burst mode