JPS5445545A - Control system for input and output interface - Google Patents

Control system for input and output interface

Info

Publication number
JPS5445545A
JPS5445545A JP11237577A JP11237577A JPS5445545A JP S5445545 A JPS5445545 A JP S5445545A JP 11237577 A JP11237577 A JP 11237577A JP 11237577 A JP11237577 A JP 11237577A JP S5445545 A JPS5445545 A JP S5445545A
Authority
JP
Japan
Prior art keywords
field
circuit
input
stored
content
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11237577A
Other languages
Japanese (ja)
Other versions
JPS5746573B2 (en
Inventor
Katsuaki Matsumoto
Tadashi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP11237577A priority Critical patent/JPS5445545A/en
Publication of JPS5445545A publication Critical patent/JPS5445545A/en
Publication of JPS5746573B2 publication Critical patent/JPS5746573B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To speed up the input and output interface operation, by taking the specific field of the instruction word read out from the memory address as the transmission signal pattern and by controlling the input and output interface operation.
CONSTITUTION: The instruction read out from the memory 5 is stored in the instruction register 3, the instruction format field 3-1 is interpreted in the decode circuit 6, and the content of the reception signal latch circuit 1 is set to the memory address register 4. That is, the memory address accessed next is determined with the reception signal pattern of the circuit 1, the content of the memory 5 corresponding to the memory address is read out newly and is stored in the register 3. At this time, the transmission signal pattern corresponding to the reception signal pattern is stored to the input tag field 3-5 of the register 3, the field 3-1 is interpreted in the circuit 6, and the content of the field 3-5 is transferred to the circuit 2 by instructing the content of the field 3 to the transmission latch circuit 2 to be stored, and it is delivered to the opposing unit
COPYRIGHT: (C)1979,JPO&Japio
JP11237577A 1977-09-19 1977-09-19 Control system for input and output interface Granted JPS5445545A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11237577A JPS5445545A (en) 1977-09-19 1977-09-19 Control system for input and output interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11237577A JPS5445545A (en) 1977-09-19 1977-09-19 Control system for input and output interface

Publications (2)

Publication Number Publication Date
JPS5445545A true JPS5445545A (en) 1979-04-10
JPS5746573B2 JPS5746573B2 (en) 1982-10-04

Family

ID=14585099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11237577A Granted JPS5445545A (en) 1977-09-19 1977-09-19 Control system for input and output interface

Country Status (1)

Country Link
JP (1) JPS5445545A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56162149A (en) * 1980-05-16 1981-12-12 Nippon Telegr & Teleph Corp <Ntt> Data transfer device
JPS59208647A (en) * 1983-05-13 1984-11-27 Nec Corp Microprocessor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5175348A (en) * 1974-12-26 1976-06-29 Fujitsu Ltd
JPS51137340A (en) * 1975-05-23 1976-11-27 Yokogawa Hokushin Electric Corp Data processing unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5175348A (en) * 1974-12-26 1976-06-29 Fujitsu Ltd
JPS51137340A (en) * 1975-05-23 1976-11-27 Yokogawa Hokushin Electric Corp Data processing unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56162149A (en) * 1980-05-16 1981-12-12 Nippon Telegr & Teleph Corp <Ntt> Data transfer device
JPS59208647A (en) * 1983-05-13 1984-11-27 Nec Corp Microprocessor
JPH0218731B2 (en) * 1983-05-13 1990-04-26 Nippon Electric Co

Also Published As

Publication number Publication date
JPS5746573B2 (en) 1982-10-04

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