JPS5553743A - Address control system - Google Patents

Address control system

Info

Publication number
JPS5553743A
JPS5553743A JP12575778A JP12575778A JPS5553743A JP S5553743 A JPS5553743 A JP S5553743A JP 12575778 A JP12575778 A JP 12575778A JP 12575778 A JP12575778 A JP 12575778A JP S5553743 A JPS5553743 A JP S5553743A
Authority
JP
Japan
Prior art keywords
microorder
address
output
memory unit
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12575778A
Other languages
Japanese (ja)
Other versions
JPS6148735B2 (en
Inventor
Makoto Tazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12575778A priority Critical patent/JPS5553743A/en
Publication of JPS5553743A publication Critical patent/JPS5553743A/en
Publication of JPS6148735B2 publication Critical patent/JPS6148735B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To obtain an economical device which can easily cope with the alteration of the head address of the microorder by using the address tabel of the memory unit which can perform the writing via the microorder.
CONSTITUTION: The order read out from reading exclusive control memory unit CM2 which memorizes the microorder is stored into microorder register CMIR8, and part of this order is written into microorder register IR4 which stores the order read from main memory unit MM3. Then part of the output of CMIR8 is written into rewritable address table 1' for the next writing in synchronization with the writting signal sent from control part 6 and in the form of the writing data. Part of the output of table 1' and part of the output of IR4 are supplied to arithmetic circuit AC5 to deliver the logic product, and then the output of the logic product is supplied to CM2 along with part of the output of table 1' via address selector CMAS7 to be used as the address of CM2. Table 1' is rewritable and thus can cope easily with the alteration of the head address of the microorder.
COPYRIGHT: (C)1980,JPO&Japio
JP12575778A 1978-10-13 1978-10-13 Address control system Granted JPS5553743A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12575778A JPS5553743A (en) 1978-10-13 1978-10-13 Address control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12575778A JPS5553743A (en) 1978-10-13 1978-10-13 Address control system

Publications (2)

Publication Number Publication Date
JPS5553743A true JPS5553743A (en) 1980-04-19
JPS6148735B2 JPS6148735B2 (en) 1986-10-25

Family

ID=14918053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12575778A Granted JPS5553743A (en) 1978-10-13 1978-10-13 Address control system

Country Status (1)

Country Link
JP (1) JPS5553743A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60128531A (en) * 1983-12-15 1985-07-09 Nec Corp Data processing unit
JPH0813752A (en) * 1994-10-20 1996-01-16 Taisei Denki Kogyo:Kk Dry movable floor construction method and unit support leg used for this method
JPH081017U (en) * 1995-08-18 1996-06-21 有限会社泰成電機工業 Dry floor structure

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0511863Y2 (en) * 1990-07-24 1993-03-25

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5397349A (en) * 1977-02-05 1978-08-25 Fujitsu Ltd Order decording system
JPS553046A (en) * 1978-06-21 1980-01-10 Toshiba Corp Microprogram control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5397349A (en) * 1977-02-05 1978-08-25 Fujitsu Ltd Order decording system
JPS553046A (en) * 1978-06-21 1980-01-10 Toshiba Corp Microprogram control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60128531A (en) * 1983-12-15 1985-07-09 Nec Corp Data processing unit
JPH0813752A (en) * 1994-10-20 1996-01-16 Taisei Denki Kogyo:Kk Dry movable floor construction method and unit support leg used for this method
JPH081017U (en) * 1995-08-18 1996-06-21 有限会社泰成電機工業 Dry floor structure

Also Published As

Publication number Publication date
JPS6148735B2 (en) 1986-10-25

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