JPS5694425A - Receiving data transfer control system - Google Patents

Receiving data transfer control system

Info

Publication number
JPS5694425A
JPS5694425A JP17367779A JP17367779A JPS5694425A JP S5694425 A JPS5694425 A JP S5694425A JP 17367779 A JP17367779 A JP 17367779A JP 17367779 A JP17367779 A JP 17367779A JP S5694425 A JPS5694425 A JP S5694425A
Authority
JP
Japan
Prior art keywords
data
processing unit
buffer
address information
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17367779A
Other languages
Japanese (ja)
Inventor
Noboru Yamamoto
Kenichi Okada
Shinji Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17367779A priority Critical patent/JPS5694425A/en
Publication of JPS5694425A publication Critical patent/JPS5694425A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Computer And Data Communications (AREA)

Abstract

PURPOSE: To improve the processing efficiency to cause the channel device to write receiving data during the reading of the central processing unit for contents of the data buffer, by causing the central processing unit to transfer receiving data onto the main memory efficiently when the traffic quantity is increased specially.
CONSTITUTION: Central processing unit 1 reserves plural data buffer areas 10 on main memory 2 and transfers address information of these buffer areas 10 to data buffer address holding part 8 of channel device 3 and transfers received data to receiving buffers 7-0W7-N. When data is transferred by the control of direct memory access DMA control part 6, one address information of buffer area 10 which is idle is extracted, and received data is written in memory 2 by DMA control while processing unit 1 reads data in buffer area 10 according to this address information, thus improving the processing efficiency.
COPYRIGHT: (C)1981,JPO&Japio
JP17367779A 1979-12-27 1979-12-27 Receiving data transfer control system Pending JPS5694425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17367779A JPS5694425A (en) 1979-12-27 1979-12-27 Receiving data transfer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17367779A JPS5694425A (en) 1979-12-27 1979-12-27 Receiving data transfer control system

Publications (1)

Publication Number Publication Date
JPS5694425A true JPS5694425A (en) 1981-07-30

Family

ID=15965045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17367779A Pending JPS5694425A (en) 1979-12-27 1979-12-27 Receiving data transfer control system

Country Status (1)

Country Link
JP (1) JPS5694425A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58129628A (en) * 1982-01-29 1983-08-02 Nec Corp Data channel device
JPS60251452A (en) * 1984-05-28 1985-12-12 Kokusai Electric Co Ltd Continuous i/o transfer method of high speed circuit data

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58129628A (en) * 1982-01-29 1983-08-02 Nec Corp Data channel device
JPS60251452A (en) * 1984-05-28 1985-12-12 Kokusai Electric Co Ltd Continuous i/o transfer method of high speed circuit data

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