JPS60251452A - Continuous i/o transfer method of high speed circuit data - Google Patents

Abstract

PURPOSE:To reduce the load of a master CPU and to improve processing functions by adding an one-chip microprocessor as a slave CPU and directly controlling data transfer between a master memory and a serial data communication control LSI. CONSTITUTION:Buffer areas 21, 22 are formed in the master memory 2 and switching circuits SW1, SW2 are controlled by programs from the master CPU1 and the slave CPU9 to switch the areas 21, 22 in the memory 2 alternately and access them. When a large quantity of data are to be sent from a disk 14-1, the circuit SW1 is turned to the area 21 side, data transfer from the disk 14-1 to the area 21 is started, and at the end of data transfer, the circuit SW2 is turned to the area side 21 to transfer data from the area 21 to a communication control LSI6. At the end of the data transfer, the slave CPU9 turns the circuit SW2 to the area 22 side and the data of the transferred area 22 are transferred to the LSI6. Thus, the data can be transferred at a high speed without interruption by switching the circuits 21, 22 alternately.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention provides a data transmission terminal device using a microprocessor (hereinafter referred to as CPU), which transmits high-speed line data in one piece.
The present invention relates to a method for performing continuous direct input/output transfers to and from main memory by additionally using a slave microprocessor on a chip.

(Prior Art) Figure 1 is a side view of a conventional high-speed line data continuous input/output transfer control circuit. In the figure, 1 is the CPU, 2 is the main memory, 4
is DM A O (Direct Memory Acc
ess C! controller), 6 is M P-S
O (Multi-Protocal Elerial
Controller'r, communication control IC)'.

7 is D'C! E (Data C! omnica
tion equipment.

(line terminating equipment such as a modem), which will be explained in more detail in Figure 2, the main part of the present invention. Further, 8 is a transmission line, 10 is a control circuit, and 11 is a bus (bus) for data, addresses, and control signals.

As shown in this figure, the conventional method for continuous high-speed line data input/output transfer is to use multiple buffer memories (same for shift registers and FO memories) between the main memory 2 and the MPSO (communication control LSI) 60. 101 and 102'J, and these buffer memories were switched and controlled by hardware. Therefore, as is clear from the figure, there are two buffer memories 101 and 102, a buffer memory control circuit 106, and two bidirectional data switching circuits (j3KL1, 2) 104, 105 each having a width of 8 bits.

is necessary. In particular, the buffer memory control circuit 105 has
Each buffer memory includes a transfer number counter, a control circuit for the memory itself, an interface circuit with the microprocessor (CPU) 1, a control circuit for EiEL1, 5EL2, and a control interface circuit with MPSo6. Therefore, the disadvantage is that the hardware is complicated and expensive. Furthermore, since memory control requires the intervention of a microprocessor, and part of line control is performed by the CPU, the processing load on the CPH is large and the processing capacity is reduced. Furthermore, when data is received and processed and then stored in a large-capacity file or the like, this delay may become a problem because the data is taken into the main memory via the buffer memory. Further, since the capacity of the backup memory is fixed by hardware, there is a degree of freedom in terms of transfer speed and processing speed.

Next, the operation of the circuit shown in Figure 1 will be explained to supplement the above. In Figure 1, buffer memories 101 and 102 temporarily store transfers between the main memory 2 and the communication control ICMPSo 6. Reference numeral 106 denotes a buffer memory control and bidirectional data bus switching circuit (SEL) 104 .

This is a buffer memory control circuit that controls 105, and includes two address counters and two counters for the number of bytes of transfer data used when transferring data between 101, 102, and 6.

104 (SELl) is an 8-bit width bidirectional data bus switching circuit for selecting either buffer memory 101 or 102, and 1o5 (SEL) is an 8-bit width bidirectional data bus switching circuit for selecting either 104 or BUSll. 0ONT10 is a circuit controlled from C, PU1 via BUSII, 14-1 is an input/output device including a large capacity file such as a magnetic disk device (DIS, K), 13 -1 is its controller.

Here, the operation of the circuit will be explained for an example when data in 14-IDISK is sent. buffer memory 101,
A buffer area corresponding to 102 is provided in the main memory 2, and data is read from 14-IDISK into the two buffer areas of the main memory by DMA (direct memory access) using DMAO4. Next, the read data in the buffer area corresponding to 101 of main memory 2 is transferred to buffer memory 101 by DMA. During this transfer, the address counters for backup memories 101 and 102 in the buffer memory control circuit 105 are set to zero (0) by a program from the CPU 1, and the transfer data (
Set the byte λ number counter to the specified data number. In addition, 704SBL1 is connected to 105S from backup memory 101.
BL2 is configured to select data from 104 SEL1. And from main memory 2 to buffer memory 10
After the data transfer to buffer memory 10 is completed, the buffer memory 10
1 or t) Start data transfer to MPSo6. During this data transfer, data in the buffer area corresponding to 102 in main memory 2 is transferred to buffer memory 102 by DMA, and data in the buffer area corresponding to 101 in main memory 2 is also transferred from 14-IDISK to buffer area 101 in main memory 2 by DMA. Transfer the data to be sent to.

The data transfer time from main memory 2 to buffer memory 101 or 102 and the data transfer time from 14-IDISK to main memory 2 are as follows:
It is designed to be sufficiently fast compared to the transfer time from MPS (! 6).
When the data transfer between 06 and 06 is completed, that is, when the transfer data (byte) number counter corresponding to 101 in the buffer memory control circuit 1o5 becomes zero, the control circuit 105
switches 104EIEL1 to the buffer memory 102 side and starts data transfer between 102 and MPSO6. During this transfer, the data in the buffer area corresponding to 101 in the main memory 2 is transferred to the buffer memory 101, and the data is transferred from the 14-1 DISK to the buffer area corresponding to 102 in the main memory 2 by DMA. At the same time, the address counter corresponding to the memory 101 of the buffer memory control circuit 106 and the transfer data (byte) number counter are set to C! Set by the program of PU1. Data is input and output continuously by repeating the above operation, but the reason why multiple buffer memories are switched and controlled by hardware is that when it comes to high-speed transfer, CPU 1 This is because the switching processing by the program cannot be done in time, that is, the switching cannot be performed within time t2 shown in Figure 6, which will be described later.

As is clear from Figure 1-1, all of 101 to 105 are made up of individual parts, so compared to the case where they are made up of one chip of CPU, the number of parts is about 40 times greater, and the area occupied is about 15 times more. The drawback is that the circuit is complex and expensive.

Furthermore, since the buffer memory control circuit 103 does not have intelligence, the OONT10 is connected to the BUSll, and part of the line control is performed by the program of the CPU1. Moreover, the program processing for this 0ONTiO requires constant monitoring of the status.
The processing load on the CPU 1 is heavy. Furthermore, the intervention of the CPU1 program related to DMA transfer is also
Transfer between main memory 2 and main memory 101 or 102
Transfer between buffer memories 101, 102 and MPSO 6
This is necessary for the transfer between the two chips, and the number of transfers is one more time than when a single-chip CPU is used, reducing the overall processing capacity. Since data is taken into the main memory 2 via the buffer memories 101 and 102, for example, when the received data is processed and then stored in the D-engine 5K14-1, the processing is performed in the main memory.

If an abnormality is discovered in the data content at this stage and retransmission is requested, the data in the buffer memory 101 or 102 will be discarded, resulting in a decrease in transmission efficiency. Further, as described above, since the memory capacity of the buffer memories 101 and 102 is fixed in terms of hardware, it is not possible to respond flexibly to transfer speeds and processing speeds.

(Objective of the present invention) It is to eliminate the drawbacks of the conventional continuous input/output transfer control method for high-speed line data. Specifically, an inexpensive 1-chip microprocessor is added as a slave CPU, and the main memory and Direct data transfer control is performed between MPSOs (serial data communication control ICs that meet various communication protocols) without placing a buffer memory in between. Furthermore, slave CPU
Since it is equipped with intelligence, it is possible to share part of the line control and other controls, and the main CP
The purpose is to reduce the processing load on U and improve its processing capabilities. Note that since a buffer area is provided on the main memory instead of the buffer memory, it can be used freely within the capacity of the main memory. Another purpose is to make effective use of the main memory by opening it up to other programs when it is not used for data transfer.

(Structure and operation of the present invention) Figure 2 shows an example of the configuration of a microcomputer system embodying the present invention, and those with the same symbols as those in Figure 1 have the same names. In Figure 2, Ml is the master microflow 0 setter (abbreviated as master CPU), and 5 is L for interrupt control.
SI, PIO' (programmable interactive controller), 5 is switching control game) S E L (+9e
9 is a one-chip slave microprocessor (abbreviated as slave CPU), which is the core of the present invention.

10 is a control circuit 00NT (Controller
) controls some of the MPSO6 and DOK7. 1
1 is a bus for data, addresses, control signals, etc., 12 is a timer LEII (programmable interactive timer), 16-1 to 13-n are controllers for each input/output device, and 14-1 to 14-n are Magnetic disk device DI
Input/output equipment such as SK, FD is floppy disk drive, OR, TKB is CRT keyboard, PRT
is a printer.

Figure 5 is an explanatory diagram (B) showing the operational concept of the present invention (Shu and switching timing chart). Areas 21 and 22 in the main memory 2 are areas for temporary storage of transferred data, and are called buffer areas. 23 is a data bus between buffer area 21 or 22 and MPSC6, SW, 1 and S
W2 is a switching circuit used to select which buffer area in the main memory is to be used for data transfer between the DISK and the main memory or between the main memory and the MPSO.

As mentioned above, there are two buffer areas in main memory.

A 21 and 22 are provided, and swi is executed by the master CPU 1 and slave PU 9 programs.

SW2 is controlled to alternately switch and access the two buffer areas in the main memory 2. As an example, DISK14
- When sending a large amount of data from 1, switch swi to the buffer area 21 side, start data transfer from DISK to 21, and when the transfer to 21 is finished, switch swi to buffer area 21.
2 to the buffer area 21 side and MPSO from 21
Start data transfer to 6. During this transfer from 21 to 6, the next data is transferred from DISK 14-1 to buffer area 22. The slave CPU 9 monitors the transfer from 21 to the MPSO 6, and when the transfer is completed, the slave 0PU 9 transfers the EIW 2 from the buffer area 21 to the buffer area 22.
The next data is transferred from 22 to MPSC 6. By alternately switching and using 21 and 22 in this way, data can be transferred at high speed without interruption.

The data transfer speed between DISK or FD and main memory is normally between main memory 2 and MPEIC! The data transfer rate is several tens to several times faster than the data transfer rate between 6 and 6.

For this purpose, SW1 uses one channel of MAC4 and is executed by the program of master OPUM1. SW2
In order to perform seamless transfer, it is necessary to switch within the time t2 illustrated in Figure 3 (B), as explained below. For this reason, SW2 uses two channels of DMAO4, and is executed by the program of slave CPU 9 according to the data specified by the mask OP and U programs.

Next, Figure 6 CB) will be explained. 23' indicates the data transfer status between the main memory 2 and MPS06, of which 2
4 indicates the final transfer data between the buffer area 21 and MPS 06, and 25 indicates the first transfer data between the buffer area 22 and MPS 06. Further, t is the transfer period (reciprocal of the data transfer rate) of one data (byte), and for example, if the data transfer rate of the line is 8 KB/S, t=125 μB. t3 is main memory 2 and M
The time required to transfer 1 data (byte) between PS06 is usually 1 to 2 μS.

t2 is equal to (1, -13), within which time SW2 needs to complete the switching from buffer area 21 to 22 or from 22 to 21. The fact that the transition between 24 and 25 is performed seamlessly means that t can remain unchanged even if switching is performed.

While the master OPUM1 program was trying to perform switching within time t2, the master OPUM1 was executing multiple services and other processing programs for the input/output devices 14-1 to 14-n, so the switching request was not received. Even if there is, the t2 time may be significantly exceeded depending on waiting time, program running time, etc. In order to solve this problem, the present invention uses a slave O'P U 9 having intelligence to perform flexible switching control.

Next, we will explain the operation of the present circuit. Figure 4 is a side view of the detailed configuration of the portion of Figure 2 that performs high-speed data transfer. P engineering C (Progr'amable engineering interruptCo)
controller) 5 accepts an interrupt request signal 15 from the slave 1 chip CPU 9 and transmits it to the mask CPU 1 via the bus 11. DMAO4 uses two channels CHO and CHI to transfer data between buffer area 21.22 in main memory 2 and MPSO6, and at the same time uses one of the remaining channels to perform DIEIK.
Large capacity files such as 14-1 and buffer area 21.
Data input/output is performed between 22 and 22. 5A and 5B are switching gates (SEL), and 5A distributes the transfer request signal 65 from MPSC6 as 16.17 to channels CHO and OH1 of DMAO4, and this OHO, 1m! The transfer permission signals 18 and 19 from H1 are collectively numbered 66. 5B is a combination of different transfer request signals 61, 62 such as transmission or reception from MPSO 6 as 65, transfer permission signal 66 from DMAC 4 as 66.64, and T of M23C6.
Distribute to XA and RXB. This MPS O6 converts serial data into parallel data or parallel data into serial data, and has various protocol control functions. Furthermore, M
TXA of PSO6 is a transmitter, RXA is a receiver, and DRQ
, represents a DMA transfer request signal, DAK represents a transfer permission signal, and T represents a terminal. 9 is a 1-chip slave CPU, which has a hardware counter function. T in 9
I (29) is the count signal input terminal of the doware counter, baud) 1 (20) is the control circuit C0NTI
O control signal 300Å output terminal, baud! -2 (26),
% is provided with output terminals for the selection control signals 27.28 to the interrupt request signals 15.5A and 5B to the PIO3, respectively. Further, DBB31 is a data bus buffer, and exchanges data with mask OP U'M1.

If you want to send the data in DISK14-1 with this \ For the example of ゛,! This will be explained using Figure 8. The 8th figure is Master O.
It is a flow chart showing mutual processing between PUMI, slave O, and PU 9. In Figure 8, 801 and D-work 61 are 14
-1 to the buffer area 21 of the main memory 2 by DMA. When the data transfer to the buffer area 21 is completed, MPSC! Various parameters of MPSO 6 are set, and the operation mode and protocol (communication rules) of MPSO 6 are determined thereby. 805 is DMAC
! In setting the parameters of the channel to be used from now on in step 4, the start address of the buffer area 21, the number of transfer data (bytes), and the transfer mode are set in CHO.

804 is C! Control data to 0NTIO to slave C!
Set to DBB31 of PU9, slave CPU9 side takes in this data at 822, and MPSC! Controls such as switching the transmission lock speed of 6 are controlled by C! This is done through 0NTiO. In addition, master OPUMI and slave 0PU9
I will explain later how to transfer data.

805 is the first DMAC to use! Specify the cHO of 4, and 826 receives this and moves sBB, 1 (5A) to the 16.18 side, and 5EL2 (5B) by 27 and 28 in Figure 4.
) to the 61.63 side.

806 is the first DMAC to use! Specify the number of transfer data (bytes) of CHD 4, and 824 transfers this to slave 0.
Set in the hard counter and soft counter of PU9. 807 and 808 are DMACs to be used next! 4 O
Specify the number of transfer data (bytes) for H1, 825, 82
6 stores each data in the data memory of the slave 0PU9. In the explanation so far, for the sake of clarity, steps 802 to 808 are executed after data is read at 801, but in reality, if the transfer is started at 801, D
Since MAO4 executes the transfer independently of the program and can return to the program via an interrupt when the transfer is complete, it executes steps 802 to 808 during this transfer and waits for the transfer to complete while executing other processes. Is possible. When a transfer end interrupt occurs, the process is interrupted and step 809 is executed.

Here, the method of receiving and passing data between master OPUM1 and slave 0PU9 will be explained.

Figure 5 (Shu is an example of the flowchart of the main program of slave 0PU9. After setting the initial state at 501 in the figure, it is checked at 502 whether there is a channel switching request for DMAO4, and if there is no request, the flowchart at 506 is executed. 0ONT1
Processing such as monitoring the line status is performed at step 0, and the operation of returning to step 502 is repeated.

When data is set from the mask CPU to DBB31 of the slave CPU, the slave CPU generates an interrupt.
The interrupt processing program from the mask CPU is activated and receives data.

Figure 7 shows an example of a processing flowchart for an interrupt from the master (:!PUM1) of slave 0PU9.

There are two types of data passed from the mask CPU: one that specifies processing as a command, and one that specifies processing. In this figure, first, at 701, the mask CPU transfers the data to the slave C.
Command set in DBB31 of PU9 (Master C
The command from the PU) is read, the command is analyzed in step 702, and the corresponding processing in steps 706 to 706 is performed based on the result. For example, 805 in Fang 8 is DMA0H.
If O is specified, in 825 the command from mask OP'U is determined to be DMACH specification in 702.

At 703, 5EL1 and 5EL2 (5A, 5B) are switched to the 16.18 side and the 61.63 side, respectively.

Also, when DMA OH1 is specified by 807, 703 determines that it is the next DMA channel to be used and sends it to slave 0.
Store it in the data memory of PU9.

Here, we return to the explanation of Fig. 8. 809 specifies the start of data transfer between the buffer area 21 and MPS (T6) by DMA, and 827 causes the slave CPU 9 to start transfer control. 810 specifies the data transfer from DISK 14-1 to the buffer area 22 by DMA. Activate it. When the transfer start is specified, the MPSO 6 outputs a transfer request signal of 61, and this signal is set as 16 to the DMAO 4 by BEL'5 and requests the OHO to transfer data. DMA
When O4 becomes ready for transfer, it outputs a transfer permission signal of 18, and this signal is sent to MPSC as 65 by 5EL5.
6, where one data (byte) is transferred. Data is transferred from the backup memory 21 via the bus 11 to the MPSC! Sent to 6. When the transfer of one arter (byte) is completed, MPSO6 abruptly shuts off 61), and DM
AO4 drops 18, advances the address of the buffer area 21 by one, and subtracts one from the number of transfer data (bytes).

Also, 61 is input to T129 of slave CP'U9,
A hard counter is incremented at the trailing edge of this signal. MPSC! 6 converts the received data into serial data, sends it to DOFli 7, outputs the next transfer request signal 61 again, and repeats the above operation. A timing chart of this relationship is shown in Figure 9.

In Figure 9 (A), 65 and 66 are the same as those shown in Figure 4, 65 is the transfer request signal REQ output from MPSO/1, and 66 is the transfer permission signal AOK output from DMAO4. Further, 64 indicates the count state of the hardware counter of the slave CPU 9, and 65 indicates the count state of the software counter of the slave 0PU9.
34 increments the count by 65 in Figure 74, and 35 counts down when the counter 64 overflows. Here nrXn8 is the master CPU
One D passed to the slave CPU by the program
Represents the number of data transferred to the MA channel.

Figure 9 (B) shows the switching state of the DMA0HO channel based on the software counter 65 at 36, the interrupt request signal R to the master CPU at 15, and the state D 5K1.
The data transfer between 4-1 and main memory 2 is indicated by 57, respectively. Now, the hard counter of slave 0PU9 is incremented one after another, and when it reaches the specified count, it overflows and the allocation to TI (Figure 4) 19 is performed. This interrupt causes the T1 interrupt processing program to be activated.

Figure 6 is an example of a T1 interrupt processing flowchart of the slave 0PU9. In this figure, at 601, the transfer number counter held by the software is decremented by one, and at 602, it is determined whether or not the count has increased, and if the count has not increased, the process returns to the main program. The count up is 603 and 825 (Figure 8) is the slave CP.
The next DMA channel designation data (C!H1 in this case) stored in the data memory of U9 is output to 27 (Figure 4), and S]1CL5A transfers the transfer request and permission signal lines from 16 to 17. Switch from 18 to 19. 6
04 sets the factors when issuing the interrupt request 15 to the master OPUM1 via PT03, and in this example, a switching request flag and a flag indicating that CHO has been completed are set.

Figure 5 (B) is a diagram showing an example of bit allocation for this factor. This figure is slave C! Master CPU from PU9
This is an interrupt factor bit assignment to notify the cause of an interrupt. In the figure bO
The switching request flag indicates that the transfer of either 0I (0 or OH1) of DMAO4 has been completed, and b4 and b5 are D
A termination flag indicating which channel of MAO has terminated, and is used in combination with bO. Mask OP'
If this bO is set when there is an interrupt from the slave CPU, the U program checks b4 and b5 to determine which channel has completed the transfer, and if that channel is to be used for the next transfer, DMAO4 and slave C!
Set the necessary parameters for PU9. bl,
b2, b3, b6, and bl are used for line monitoring status and other interrupt factors.

Now, 605 in figure 6 is 826 in figure 8, and slave 0
After setting the number of transfer data (bytes) of the next DMA channel stored in the data memory of PU 9 in the hardware counter and software counter, the program returns to the main program.

In the main program shown in Figure 5 (A), 502
So DMAC! If there is a channel switching request flag, 5
At step 05, the factor data set by the T1 interrupt processing program is output to the DBB 51 of the slave CPU 9, and an interrupt request 15 is issued.

Step 504 waits for the master OPUMI to receive the factor data, and upon receipt, resets the switching request flag and end flag in step 505.

The processing from the time when the CPU 9 of the slave CPU 9 counts up to when the switching request interrupt is issued corresponds to the steps 828 to 860 in Figure 8. and master C
The PU program reads and analyzes the interrupt factor data from the slave CPU in 811, and when it is found that the CHO transfer is completed, sets the OHO parameters of DMAO4 in 812, and sets the DMAO4 CHO parameters in 813.814.
and the number of OHO transfer data (bytes). 8
At 51 and 862, each is stored in the data memory of the slave CPU 9. From 815 to 8 on the mask CPU side below
20, the processing is repeated from 835 to 857 on the slave CPU side until the required number of data (bytes) is reached, and when the required number is reached, the transfer is stopped at 821 and 838.

The above description has focused on data transfer, but from the perspective of mask CCPU program processing, as mentioned above, in 801, data reading from DISK 4-1 to main memory 2 is
By starting the DMA and then executing steps 802 to 808, it is possible to perform other program processing until the reading is completed. When reading is completed, main memory 2 and M are stored in 809.
Once the transfer between PsO6 has started, the DISK
It only performs processing for starting and terminating data reading DMA0 between l4-1 and main memory 2, and processing for switching request interrupt 15 from slave 0PU9 related to data transfer between main memory 2 and MPS06. Since it is small, most of the time can be devoted to other program processing.

Also, Figure 8 shows an example of a general usage method, but under certain conditions, the processing of master apUllQ can be simplified as follows.For example, DMAI:!
DMAO4 assumes that there is no retransmission processing, etc., and always uses OHO and CHl alternately, and assumes that the number of transferred data (bytes) for OHO and CHI is constant. DMAO4 is set to auto as the operation mode when setting parameters in 806. If initialization (automatic initial setting) is specified, the parameters can be automatically reset at the end of the transfer, so steps 812 and 817 can be omitted. 8 more
Processing of 16.814.818.819 is also 805 to 80
Slave 0PU9 to use the one specified in 8.
It can be omitted if it is programmed on the side.

The above explanation was for the case of sending data in DISKl4-1, but the case of receiving data is also the same as that of 801.
, 810 are gone, and 815 is the first main memory 2 to D
Data is read into ISK14-1. Further, after the transfer between the MPsO 6 and the main memory 2 is stopped at step 821, the transfer from the main memory 2 to the DISK 1 4-1 becomes necessary. Naturally, the designation in Figure 28 is to set 5B to the 62.64 side, and slave 0PU
The transfer process on the 9 side is from the MPsO 6 to the main memory 2.

(Effects of the Invention) (1) Comparing Figure 1 showing the configuration of a conventional high-speed data input/output transfer control circuit with Figure 2 showing the configuration of a high-speed data input/output transfer control circuit according to the present invention. As can be seen, the circuit of the present invention eliminates the need for a buffer memory and its control circuit, making the hardware simple, compact, inexpensive, and flexible.

(2) Since the processing load is shared by the slave CPU, the data processing function of the entire system can be improved.

(3) The buffer area on the main memory can be used freely and can be used for other programs when it is not used for data transfer.

[Brief explanation of drawings]

Figure 1 shows an example of the configuration of a conventional high-speed data input/output transfer control circuit, Figure 2 shows an example of the configuration of a high-speed data input/output transfer control circuit according to the present invention, and Figure 3 shows the operational concept of the present invention. Explanatory diagram and switching timing chart in the diagram, spear 4 figure is spear 2
A detailed configuration example of the part that performs high-speed data transfer in the figure. Figure 5 is a flowchart of the main program of the slave CPH in Figure 4. (B) is an example of the interrupt factor bit assignment of the slave O'P U. Figure 6 is a flowchart of the slave CPU's T1 interrupt processing, and Figure 7 is the master CPU of the slave CPU.
FIG. 8 is a flowchart of processing between the master CPU and slave CPU, and FIG. 9 is a timing chart of data switching operation. 1... Microprocessor (C!'PU), Ml.
...Master OP'U, 2...Main memory, 6...P
ICt (programmable interrupt controller, LSI for interrupt control), 4...DMA0 (direct memory access controller), 5...5EL (data bus switching circuit), 6...MPSO (multiprotocol serial controller, for communication control) LSI), 7...
DOE (data communication equipment modem), 8...transmission line,
9...Slave C! PU, 10...0ONT (control circuit), 11...BU, E+ (bus), 12...
...P engineering T (programmable interwoven timer),
15... Input/output controller, 14... Input/output device, 101, 102... Buffer memory, 103...
Buffer memory control circuit, io4, 1os...5EL
(data switching circuit), 15... interrupt request signal, 20.
...Port (300Å output terminal), 21.22...Buffer area, 23...Data bus, 27.28...
・Selection control signal, 26... port (15, 27,, 2
8 data output terminal), 29 (TI)...Count signal input terminal, 50...0Control signal to ONT 10, 31 (DBB)...Data bus buffer, 52.
55... Control signal, 16.17, 61. ．． 62.65
... Transfer request signal, 18.19, 63, 64.66.
...Transfer permission signal, CHO, CHI...Channel number. 'Patent applicant: Kokusai Denki Co., Ltd. agent Daibu, 1 outsider Figure 5 (A) Figure 6 Ryo 7 Figure 8 (1)

Claims (1)

[Claims] When using a data processing system using a microprocessor and controlling high-speed data input/output transfer by simultaneously operating a data transmission line and a large-capacity file such as a magnetic disk device, it is necessary to use a mask microprocessor to send or receive takes. Main memory and MPS are controlled using a control circuit consisting of a single-chip slave microprocessor and a DMA (direct memory access) controller.
Transferring high-speed lines directly between main memory and MPS 0 without placing a buffer memory between O (multi-protocol serial controller LSI for communication control), switching between multiple buffer areas in main memory. In addition, a part of the line control is processed by the slave microprocessor 90, thereby reducing the processing load related to data transfer on the master microprocessor and improving the processing function. Continuous input/output transfer method for high-speed line data.