JP2581001B2 - Information management apparatus and information management method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information management apparatus and an information management method for loading a program from a main control unit to a plurality of sub-control units.

[0002]

2. Description of the Related Art When a main control unit and a sub control unit are provided, the operation of the sub control unit is controlled by loading a program of the main control unit into the sub control unit. FIG. 3 is a configuration diagram showing the configuration of the information management apparatus having the upper panel serving as the main control unit and the lower panel serving as the sub control unit.
In the figure, 10 is an upper panel, 10a is a memory storing a program to be loaded, 20
a _1, 20a ₂ ~20a _n is lower panel, 30 is an address bus, 31 denotes a data bus, 35 an interrupt line.

[0003] FIG. 4 is a diagrammatic view showing the structure of the sub-control section 20 _1, 21 panel identification address setting switch different value for each of the lower panel is set, 22 is panel identification address setting The address value set by the switch 21 and the address bus 3 from the upper panel 10
A comparison block for comparing with a value above 0; 23, a program loading address setting switch in which the same value is set in a plurality of lower panels; 24, a value and an address set in the program loading address setting switch 23 This is a comparison block for comparing the value with the value on the bus 30.

A gate circuit 25 calculates the logical sum of the outputs of the comparison blocks 22 and 24.
5, a buffer memory whose writing is controlled by the logical sum signal output from the CPU 5, a CPU 27 connected to the upper panel 10 via the buffer memory 26a via the address bus 30 and the data bus 31 for communication, and 28 a CPU 27 A memory in which the program is stored, and 32a is a register indicating a program loading request on the upper panel 10.

When starting up the system, the lower panel 20
a ₁ denotes a program loading request to register 32a. Top panel 10 monitors the register 32a always receives the first time a program loading request from the lower panel 20a ₁ to operate the timer.
At this time, the upper panel 10 is connected to the other lower panels 20a ₂ to 20a ₂ .
Continue scanning the 20a _n, and checks whether within a predetermined time the timer is running from other lower panel 20a ₂ through 20a _n have programs loading requirements.

After a predetermined time, the upper panel 10 sets the value set in the program loading address setting switch 23 on the address bus 30. Next, a program to be loaded onto the data bus 31 is output. In comparison block 24 of the lower panel 20a _1, program loading address setting switch 2
3 is compared with the value of the address bus 30, and the gate circuit 2
5 to control writing to the buffer memory 26a.

When the value of the program loading address setting switch 23 matches the value of the address bus 30, the output of the comparison block 24 becomes "0", "0" is output from the gate circuit 25, and the buffer memory 26a
Writing to is allowed. That is, the upper panel 10
Waits for a certain period of time after receiving a program loading request from the lower panel 20a, and then sets the value of the program loading address setting switch 23 on the address bus 30 so that a plurality of lower-level devices operating with the same program are operated. the panel 20a ₁ through 20a _n, can be loaded a program at a time.

[0008]

Conventionally, as described above, when a plurality of programs are loaded into a plurality of sub-control units (lower panels), there are the following problems. First, since a plurality of programs are loaded one after another, this loading time is required for the number of programs. Also, when there are a plurality of programs and these individual programs are to be loaded into a plurality of sub-control units, addresses for distinguishing them by the number of programs, that is, the above-described program loading address setting switches 23 are provided.
Must be prepared for the number of programs.

Therefore, in the sub-control unit, a plurality of addresses must be prepared for storing different programs in the buffer memory 26, that is, the memory capacity must be increased. was there. And while such a large memory must be prepared, the sub control unit loads one program. That is, not all of them are used, and therefore, there is a problem that a portion that is not normally used is formed in the memory, and there is much waste.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to make it possible to more quickly load a plurality of different programs.

[0011]

An information management apparatus according to the present invention uses only write control by first and second identification means based on the coincidence / mismatch between first and second identifiers transmitted on an address bus. In addition, the sub-control unit includes a buffer memory in which write control by the main control unit is also performed by the write control unit in which the write control is stored. When loading the requested instruction program, the sub-control unit includes The main control unit includes a main CPU for writing the write control.

Further, according to the information management method of the present invention, when the main control unit finishes sending the first instruction program to the first sub-control unit, the writing of the first sub-control unit to the buffer memory is prohibited. Thus, the writing to the buffer memory of the second sub-control unit, which has been prohibited from writing, is permitted. While the CPU of the first sub-control unit is transferring the first instruction program written in its own buffer memory to the memory of the first sub-control unit, the main control unit transmits the second instruction program to the address bus. And sending the second instruction program to the data bus.

[0013]

While the first sub-controller is transferring the first instruction program received in the buffer memory to the memory, the second sub-controller receives the second instruction program in its own buffer memory.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing a configuration of an information management device according to an embodiment of the present invention. In the figure, the memory table 11 is primarily CPU, 12 in the upper panel 10 program memory for storing a loading program in the upper panel, the 13 stores a type of program request from the lower panel 20 ₁ to 20 _n , 14
Is a timer.

Also, 25a and 25b are gate circuits, 26
Is a buffer memory whose writing is controlled by the output of the gate circuit 25b, and 32 is a signal that the upper panel 10 has recognized the program loading request to the lower panel 20 that has requested it, and a program is stored in the buffer memory 26 of the lower panel 20. A read register 33 for controlling whether or not writing is permitted is a write register 33 for issuing a program loading request to the upper panel 10.

The gate circuit 25a calculates the logical sum of the output of the comparison block 24 and the read register 32, and the gate circuit 25b calculates the logical sum of the output of the comparison circuit 22 and the gate circuit 25a. The other symbols are the same as in FIGS. Hereinafter, a method of loading a plurality of programs in the above configuration will be described with reference to the flowchart of FIG. Here, upper panel 10 has lower panel 20
_{1 to} 20 ₄ are connected, and the lower panels 20 ₁ and 20 ₄ are connected.
₂ requires the A program, and the lower panels 20 ₃ , 20
_{The case where 4} requires the B program will be described.

When the apparatus is started up, the lower panels 20 ₁ to 20 ₁
20 ₄ writes the program loading request to its write register 33 (step S21). Top panel 10 monitors the respective lower panel 20 ₁ to 20 ₄ of the write register 33 always (step S
1) When the program loading request is written into the write register 33, the upper panel 10 recognizes this, and thus receives the program loading request (step S2). Thus, when the upper panel 10 accepts first the program loading request from the lower panel 20 _1, to operate the timer 14.

The upper panel 10 is continued, it continues to monitor the other lower panel 20 ₂ to 20 ₄ write register 33, within a predetermined time, i.e., other lower panel 20 ₂ 20 ₄ while the timer 14 is operating It checks whether there is a program loading request from. As described above, the upper panel 10 becomes the lower panel 10 ₁ , 1
0 ₂ requests the A program, and the lower panel 20
_3, recognizes that requesting 20 _4, B program.

[0019] Then, while the timer 14 is operating, to the lower panel 20 ₁ to 20 ₄ Top panel 10 there is a program loading request, that resets the program loading request, recognizes the request transmitting to the lower panel 20 ₁ to 20 ₄ (step S
3). The reset of the request is performed by erasing the contents of the write register 33. At the same time, the upper panel 10, and the number of the lower panel 20 ₁ to 20 _4, requesting a memory for respective program table 13
(Step S3).

During a certain time period during which the timer 14 is operating, even if there is a lower panel that is started up late, the program loading request can be received. After a lapse of a certain period of time when the operation of the timer 14 ends, the upper panel 10 first starts the transfer of the A program. At this time, the upper panel 10 performs write inhibition instruction to the lower panel 20 _3, 20 ₄ of the read register 32 requesting the B program (step S4). Thus, the program is not written in the buffer memory 26 of the lower panel 20 _3, 20 _4.

The upper panel 10 sets the value set by the program loading address setting switch 23 on the address bus 30 by referring to the table memory 13. Subsequently, the A program stored in the program memory 12 is output to the data bus 31 (step S5). Each lower panel 20 ₁ to 2
0 to ₄ program loading address setting switch 23, a common value is set, the upper panel 10
Thus, by setting this value on the address bus 30, the same program can be loaded to a plurality of lower panels at one time.

[0022] In the lower panel 20 ₁ to 20 _4, since the value set to the value and the program loading address setting switch 23 on the address bus 30 are equal, the write enable signal for the buffer memory 26 from the comparison block 24 Is output. And here, since this lower panel 20 _1, 20 ₂ in the read register 32 write inhibition instruction is not written, the data bus 3
The A program output to 1 is the lower panel 20 ₁ , 20
₂ is written to the buffer memory 26. On the other hand, in the lower panels 20 ₃ and 20 ₄ , the A program on the data bus 31 is not written since the writing into the buffer memory 26 is not possible as described above.

Here, since the buffer memory 26 usually does not have a very large capacity, the upper panel 10 loads the program in a plurality of times when loading the program. Thus, the loading of a lump with a loaded A program from the host panel 10 is completed, the high-order panel 10 broadcast distribution request to the lower panel 20 _1, 20 ₂ of the read register 32 requesting A program Is set (step S6), and at the same time, a write inhibit instruction is issued (step S6).
7).

[0024] broadcasting request is set in the read register 32, the lower panel 20 _1, 20 _2, CPU
27 transfers the contents of the buffer memory 26 to the memory 28 (step S6). When the transfer is completed, the reset state of the broadcast distribution request is indicated to the write register 33 (step S11). Here, the lower panels 20 ₁ and 2
In 0 _2, while the CPU27 is transferring the contents of the buffer memory 26 in the memory 28 can not send a mass of the next A program for the upper panel 10 the lower panel 20 _1, 20 _2. The upper panel 10 uses this time to load the B program to the lower panels 20 ₃ and 20 ₄ .

The upper panel 10, lower panel 20 ₁ requesting A program, 20 _second read register 3
Set the multicasting request to 2 and when performing a write inhibition instruction (step S7), and performs the write permission instruction to the read register 32 of the lower panel 20 ₃ to 20 ₄ which requested the B program (step S8). Thus, the output signal of the write enable to the buffer memory 26 through the gate circuit 25a and the gate circuit 25b of the lower panel 20 ₃ to 20 _4, the device can be programmed into the buffer memory 26 (step S8).

In the upper panel 10, the value set in the program loading address setting switch 23 is set in the address bus 30, and the B program stored in the program memory 12 is output on the data bus 31 (step). S9). Backward panel 20 ₃ 20 ₄ requesting the B program, the value and the address bus 30 of the program loading address setting switch 23
Since the value is equal to the above value, a write enable signal is output from the comparison block 24. Then, since the write permission instruction is also issued to the read register 32, a certain block of the B program on the data bus 31 is written (loaded) into the buffer memory 26.

[0027] bloc loading with B program from the upper panel 10 is completed, in the same manner as described above, the upper panel 10 sets the broadcast distribution request to read register 32 in the lower panel 20 ₃ 20 ₄ At the same time (step S10), a write prohibition instruction is issued (step S11). Backward panel 20 ₃ to 20 ₄ which are set broadcast distribution request to the read register 32, CPU 2
7 transfers a block of the B program on the buffer memory 26 to the memory 28 (step S10).

In the upper panel 10, this time, A
The next one mass of the program in the lower panel 20 ₁ to 20 _2,
Loading as described above (step S1
2, S13), when the lump loading is completed,
Above and sets the broadcast distribution request to the lower panel 20 ₁ to 20 ₂ read register 32 in the same manner and performing a write inhibition instruction (step S14, S15). And on the other hand,
Backward panel 20 ₃ to 20 ₄ which has finished transferring the bloc with B program in the memory 28, indicating the broadcasting request reset the CPU27 is the write register 33 (step S15).

As described above, while one block of the loaded program is being transferred from the buffer memory 26 to the memory 28 of the lower panel 20 of the loading destination, one block of a different program is loaded. The A program and the B program are alternately loaded, and all the programs are loaded. As a result, after all the A programs have been loaded, the loading of the program is completed in a shorter time than in the method of loading the B program.

[0030]

As described above, according to the present invention, a write control instruction from the main control unit to the buffer memory is stored, and write control means for controlling write enable / inhibit of the buffer memory is provided. The main control unit can control writing to the buffer memory via the writing control means. When the first instruction program is being loaded into the first sub-control unit, writing to the buffer memory by the second sub-control unit is prohibited, and
When the sub-control unit transfers the loaded first instruction program to its own memory, the writing of the buffer memory of the first sub-control unit is prohibited and the writing of the buffer memory of the second sub-control unit is prohibited. Allowed to load the second instruction program.

For this reason, when loading a plurality of instruction programs, another instruction program can be loaded without waiting for the loading of one instruction program to be completed. There is an effect that loading can be performed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration of an information management device according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an information management method according to an embodiment of the present invention.

FIG. 3 is a configuration diagram showing a configuration of a conventional information management device having an upper panel as a main control unit and a lower panel as a sub control unit.

4 is a block diagram showing a sub controller 20 ₁ of the configuration in FIG.

[Explanation of symbols]

10: Upper panel, 11: Main CPU, 12: Program memory, 13: Table memory, 14: Timer, 2
0 _{1 to} 20 ₄ : lower panel, 21: panel identification address setting switch, 22, 24: comparison block, 23 ... program loading address setting switch, 25a, 2
5b: gate circuit, 26: buffer memory, 27: CP
U, 28: memory, 30: address bus, 31: data bus, 32: read register, 33: write register.

Claims (4)

(57) [Claims] 1. An information processing apparatus in which a plurality of sub-control units are controlled by a main control unit connected by an address bus and a data bus, wherein the sub-control unit includes: a memory in which programs and data are stored; A buffer memory for temporarily storing an instruction program loaded from the main control unit via the data bus; and a buffer memory that operates with the program stored in the memory and transfers the instruction program loaded in the buffer memory to the memory. Identifies a match / mismatch between a CPU and a signal on the connected address bus and a preset first identifier address for distinguishing the signal from the others, and when they match, enables writing to the buffer memory. First identifying means, and the main control unit loads the instruction program to a plurality of sub-control units simultaneously. Second identification means for identifying a match / mismatch between a second identifier address used for the address and a signal on the address bus, and when matched, enabling writing to the buffer memory; A write control instruction to the buffer memory is stored, and write control means for controlling write enable / inhibit of the buffer memory; and a program loading request for requesting an instruction program to the main control unit under the control of the CPU is transmitted. The main control unit, when reading the program loading request, also reads and stores the program loading requests from other sub-control units, and sends the program loading request to the sub-control unit. Informs that it has been read, and instructs at the time of the program loading request A main CPU that transmits the second identifier address onto the address bus when loading a program, and further controls whether or not writing to the buffer memory can be performed on a sub-control unit that has requested the program loading; An information management device, comprising: a main CPU; and a main memory in which a program for operating the CPU, an instruction program, data, and the like are stored. 2. The information management device according to claim 1, wherein the main control unit includes a timer that operates for a predetermined time, and the main CPU receives a timer from the sub control unit while the timer operates. An information management device characterized by continuously monitoring a program loading request. 3. A memory storing a program or data, a CPU operated by the program stored in the memory, a signal of a connected address bus and a predetermined first identifier address. First identification means for identifying a match / mismatch; second identification for identifying a match / mismatch between a second identifier address used for simultaneously loading an instruction program to a plurality of sub-control units and a signal on the address bus; Communication means for communicating with the CPU; a sub-controller having a buffer memory for temporarily storing a loaded instruction program when the first identification means or the second identification means identifies a match; A main CPU, a main memory storing programs and data for operating the main CPU; An information management device comprising: a main control unit connected to the sub-control unit via the address bus and the data bus, and loading an instruction program into the sub-control unit; a first sub-control unit and a second sub-control unit Requests the main control unit to load a first instruction program and a second instruction program, respectively. When the main control unit receives a loading request from the first sub-control unit, the second sub-control unit Also, when these loading requests are recognized, the fact that the loading request has been recognized is notified to the first and second sub-control units, and the request is stored at the same time. The second sub-control unit prohibits writing to the buffer memory by transmitting a write prohibition instruction to a read register included in the unit. And sends the first instruction program to the data bus. When the main control unit finishes transmitting the first instruction program, the main control unit sends the first instruction program to the buffer memory of the first sub-control unit. Is prohibited, writing to the buffer memory of the second sub-control unit is permitted, and the CPU of the first sub-control unit executes the first instruction program written in its own buffer memory by the first sub-control unit. Wherein the main control unit sets the second identifier address on the address bus and transmits the second instruction program to the data bus while transferring the data to the memory of the sub control unit. Information management method. 4. The information management method according to claim 3, wherein when the main control unit receives a loading request from the first sub control unit, the main control unit monitors a loading request from another sub control unit for a predetermined time. An information management method characterized by continuing.