JP2580962B2 - Collective panel device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a collective panel apparatus for loading a program from a memory storing a program to a plurality of lower child panels from an upper parent panel.

[0002]

2. Description of the Related Art Each device to be controlled is arranged in a device,
There is an aggregate panel device including a child panel that actually controls the device and a parent panel that controls the status of the child panel and grasps the status of all of a plurality of devices to be controlled. FIG. 2 is a configuration diagram showing the configuration of this collective panel device. In the figure, 10 is a parent panel, 11 is a memory (main memory) storing programs to be executed, and the like.
Reference numeral 12 denotes a CPU (main CPU) of the parent panel 10, 201 to 2
09 is a child panel, 21 is a panel recognition address setting switch on which an identification number for identifying the panel is set,
Reference numeral 22 denotes a comparison block for comparing the transmitted address with the panel identifier set in the panel recognition address setting switch 21. Reference numeral 26 denotes a memory buffer which is controlled by a signal from the comparison block 22 and temporarily stores transmitted data. , 27 are CPUs, and 28 is a memory in which programs executed by the CPU 27 are stored.

[0003] Reference numeral 30 denotes a parent panel 10 and a child panel 20.
1 to 209, an address bus for transferring an identifier for designating a location for storing a program, 31 a data bus for transferring the program itself, data, and the like;
32 is a control bus to which control signals are transferred.
In this collective panel device, an instruction program for operating the child panel at startup is loaded from the parent panel. The instruction program loaded from the parent panel 10 is
The destination address is sent via the address bus 20, and the instruction program itself is sent via the data bus 31. The child panels 202 to 209 have the same configuration as the child panel 201, and are omitted from FIG.

[0004] The operation of the collective panel device at the time of startup will be described below. At the time of starting the collective panel device, a necessary instruction program is loaded from the parent panel 10 to the child panels 201 to 209. Here, it is assumed that the child panels 201 to 207 require the instruction program A, and the child panels 208 and 209 require the instruction program B. Here, parent panel 1
0 distinguishes the child panels 201 to 209 for communication with the child panels 201 to 209 using the panel identifiers set in the respective panel recognition address setting switches 21.

[0005] First, in the parent panel 10, the CPU 12 transmits the panel identifier set in the panel recognition address setting switch 21 of the child panel 201 and the instruction program A stored in the memory 11 to the address bus 30 and the data bus 31, respectively. To load. The child panel 201 compares the panel identifier sent via the address bus 30 with the value set in its own panel recognition address setting switch 21 in the comparison block 22. Here, since the transmitted panel identifier matches the value set in its own panel recognition address setting switch 21, the output of the comparison block 22 to the memory buffer 26 becomes "0", Writing is allowed. Therefore, the instruction program A sent via the data bus 31 is written into the memory buffer 26.

On the other hand, in the other child panels, the data bus 30
Is different from the panel identifier set in its own panel recognition address setting switch 21, the output of the comparison block 22 to the memory buffer 26 is "1",
Is not allowed. That is, when the parent panel 10 loads the instruction program, the panel identifier is also transmitted at the same time, so that only the child panel that matches the panel identifier can receive the loaded data. It becomes possible.

In the child panel 201, the instruction program written in the memory buffer 26 is transmitted to the CPU 27.
Is transferred to the memory 28 to make this instruction program operable, and the CPU 27 transmits to the CPU 12 of the parent panel 10 via the control bus 32 that the instruction program has been normally loaded. The CPU 12
Thus, it is determined that the loading of the instruction program A to the child panel 201 has been completed. Then, the instruction program A is loaded to the child panels 202 to 207 in the same manner, and the instruction program B is loaded to the child panels 208 and 209.

[0008]

Conventionally, the above-mentioned structure is employed, so that there is a problem that the more child panels for loading the instruction program, the longer the time required for program loading. If the programs to be loaded are not all the same, the parent panel needs to identify the child panel to be loaded surely so as not to load the wrong program. Therefore, conventionally, even when the same program is loaded to a plurality of child panels, it is necessary to perform one program loading for one child panel using an identifier corresponding to each child panel. was there. In addition, there is a problem that the load on the parent panel is large because the time required for program loading is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to reduce the time required for program loading in a collective panel device.

[0010]

According to the collective panel device of the present invention , the child panels are set in a program identifier setting section in which a program identifier for identifying an instruction program to be loaded is set, and in the program identifier setting section. A second comparing means for outputting a second signal enabling writing to the memory buffer when receiving the same program identifier as the program identifier, and at least one of the first signal and the second signal Write control means for enabling the memory buffer to be written upon receipt of the command, loading request means for transmitting a program loading request for requesting loading of the instruction program to the parent panel via the control bus under the control of the CPU,
The PU has a register for registering requests and replies to the parent panel. On the other hand, when the parent panel receives a program loading request, the parent panel controls a signal from the control bus so as not to accept another program loading request. Means for transmitting a program identifier for identifying the instruction program when loading the instruction program.

[0011]

When a program is loaded, the child panel determines whether to receive the loaded program by using an identifier for identifying the program sent at the same time as this program.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a collective panel device according to one embodiment of the present invention. In the figure, reference numeral 13 denotes an interrupt gate (request control means) for controlling the input of a control signal sent via the control bus 32 to the CPU 10, and 23 denotes a program load for setting the same value on a panel operated by the same program. Address setting switch (program identifier setting unit), 24
Is a comparison block for comparing the value with the value on the address bus 30; 25 is a gate circuit (write control means) for taking the logical sum of the outputs of the comparison block 22 and the comparison block 24;
26 is a memory buffer that is write-controlled by the logical sum signal, 33 is a register in which program loading requests and the like are written, and these are shown in the upper panel. 34 is a request transmission unit that outputs a program loading request to the control bus 32. Others are the same as FIG.

The operation of program loading in the collective panel device will be described below. here,
It is assumed that the child panels 201 to 207 require the instruction program A, and the child panels 208 and 209 require the instruction program B. First, at the time of starting the collective panel device, each of the child panels 201 to 209 writes a program loading request to the register 33, and transmits this program loading request to the parent panel 10 from the request transmitting unit 34 via the control bus 32. .

When the CPU 12 of the parent panel 10 receives any one of the program loading requests, it immediately closes the interrupt gate 13 so as not to accept another program loading request. At the same time, the contents of the register 33 of the child panels 201 to 209 are searched for a predetermined time. By this search, CPU
Numeral 12 recognizes the program requested by the child panel.
For example, in this case, in the child panels 201 to 207, the loading request of the instruction program A is written in its own register, and in the child panels 208 and 209, the loading request of the instruction program B is written in its own register. The CPU 12 recognizes these.

Based on this recognition, the CPU 12 first takes out the instruction program A from the memory 11 and outputs it to the data bus 31. At the same time, it outputs the program identifier “A” as the instruction program A to the address bus 30. As described above, the program identifier "A" is loaded on the address bus 30, and the instruction program A is loaded on the data bus.

At this time, in the child panels 201 to 207, since the program identifier "A" is set in the program load address setting switch 23, it matches the program identifier "A" loaded on the address bus 30,
Therefore, the output of the comparison block 24 becomes “0”, and writing to the memory buffer 26 is permitted. Child panel 2
In 01 to 207, writing to the memory buffer 26 is permitted, so that the instruction program A loaded on the data bus 31 is written to each memory buffer 26.

On the other hand, in the child panels 208 and 209 in which the program identifier "B" is set in the program load address setting switch 23, this differs from the program identifier "A" on the address bus 30. Therefore, the output of the comparison block is "1", writing to the memory buffer 26 is not permitted, and the instruction program A on the data bus 31 is not written to the memory buffer 26. By the above, the memory buffer 2 of the child panels 201 to 207
6, the instruction program A is written in the panel 27. The CPU 27 of these panels takes out the instruction program A stored in the memory buffer 26, stores it in the memory 28, and makes the instruction program operable. Is written in the register 33 to indicate that the instruction program has been loaded.

As described above, the CPU of the parent panel 10
12 searches the register 33, so that the child panel 2
It is confirmed that the program loading to 01 to 207 has been completed normally. Next, the CPU 12 loads the instruction program B to the child panels 208 and 209 in the same manner. At this time, it is the same as described above, and the instruction program B is
Will not be loaded.

In the above embodiment, the instruction program A
Are loaded before the instruction program B, but the present invention is not limited to this. The instruction program B may be loaded earlier. The number of child panels is not limited to nine, but may be one hundred. The number of instruction programs to be loaded is not limited to two, but may be three or more. It goes without saying that it may be present.

[0020]

As described above, according to the present invention, the program loading is completed by a single loading operation for the child panels using the same instruction program, so that the program loading time can be shortened. effective. Then, there is an effect that the burden on the parent panel can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a collective panel device according to one embodiment of the present invention.

FIG. 2 is a configuration diagram showing a configuration of a conventional collective panel device.

[Explanation of symbols]

 Reference Signs List 10 parent panel 11 memory 12 CPU 13 interrupt gate 201 to 209 child panel 21 panel identification address setting switch 22, 24 comparison block 23 program load address setting switch 25 gate circuit 26 memory buffer 27 CPU 28 memory 30 address bus 31 data bus 32 control Bus 33 register 34 request transmission unit

Claims (1)

(57) [Claims] 1. A CPU and a CPU for operating the CPU.
The memory where programs and data are stored
The received program is temporarily stored under the control of the CPU.
The memory buffer and an identifier to identify it from others are set.
An identifier setting unit, and the identifier setting unit
When receiving the same identifier as the
Outputs a first signal that enables writing to a buffer
A sub-panel having first comparing means, a main CPU, and a main CPU and the CPU to operate.
Main memory that stores programs and data
A data bus for transferring a program,
Address to specify the destination of the
Control bus for transferring control signals
Connected to the child panel by using
Load the instruction program stored in the main memory
Panel device composed of a parent panel
, The child panel is a program for identifying an instruction program to be loaded.
A program identifier setting unit in which a program identifier is set , and a program identifier set in the program identifier setting unit.
When receiving the same program identifier as the program identifier,
Second signal enabling writing to the memory buffer
And at least one of the first signal and the second signal is received.
When writing, the memory buffer is made writable.
Control means, and the parent panel under the control of the CPU.
Loading of instruction program via trawling bus
Rode to send requested program loading request
Requesting means, and the CPU registers a request or reply to the parent panel.
And a that register, said parent panel receives the program loading request, other pro
So that it does not accept the gram loading request, the call
Request control means for controlling signals from the control bus
And, when the parent panel for loading instruction program
Is a program identifier for identifying this instruction program.
A collective panel device for simultaneously transmitting different children .