JPS6239792B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program debugging device for a multiprocessor system, particularly a multimicroprocessor system.

Conventionally, debugging devices for microprocessor systems have been limited to debugging and controlling single processor systems. FIG. 1 shows an example of a connection diagram of such a conventional debugging device with a single processor system. In the figure, 1 is a processor, 2 is a local memory, and 3 is a debug device. A processor system is composed of a processor 1 and a local memory 2. 1st
The debugging device 3 in the figure receives the address signal, data signal, and control signal of a single processor system, checks the address signal, checks the memory data signal, and generates a control signal according to the check results. Configured to generate interrupts to a single processor system.

By the way, when debugging a multiprocessor system based on such a configuration in which n processors each independently own local memory and execute programs independently, the debugging device n units are required for each processor system, making the configuration and handling complicated. The present invention aims to eliminate these drawbacks of conventional debugging devices and to provide a debugging device that can control a plurality of processors simultaneously. An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a diagram showing the connection between a multiprocessor system and a debugging device in an embodiment of the present invention. In the figure, a debugging device 30 is connected to address signals, data signals, and control signals of n processors 10, 11, . . . 1n.
20, 21, . . . 2n are local memories, respectively.

FIG. 3 shows a block diagram showing the detailed structure of an embodiment of the present invention. In the figure, 10, 11,
. . 1n is a processor of the multiprocessor system, 20, 21, . . . 2n is a local memory of the multiprocessor system, and 30 is a debugging device. 31 is a selection control circuit, 34 is a key input device, 35 is a display device, 36 is a comparison control circuit, 40, 41, . . . 4n is a data buffer,
50, 51, . . . 5n indicate comparison circuits.

Next, the operation of the embodiment shown in FIG. 3 will be explained. In FIG. 3, processor CP ₀ 10,
For example, when CP ₁ 11, ...CP _o 1n are executing programs stored in their respective independent internal memories, for example, if the execution of the program of processor CP ₀ 10 reaches the memory address a _0, If you want to stop the processor CP ₁
Suppose that we want to stop the execution of the program No. ₁₁ at the memory address a1, and in the same way, we want to stop the execution of the program No. 11 of the processor CP _o 1n at the address a _o . For example, if the program of processor CP _i 1i reaches memory address a _i first among the processors CP ₀ 10, CP ₁ 11, ... CP _o 1m, all processors are stopped at that point. Consider the case where you want to check the state of the remaining processors at that time. At this time, the key input device 34 is used to input the data buffers BUF ₀ 40, . . . BUF _o 4n to the a ₀ , . . . a
Store _o 's address information. When a command to execute a program of the multiprocessor system is input through the key input device 3, the system control circuit 33 outputs a common control output signal 3.
7 is generated and n processors 10, 11,
. . 1n is generated, and the programs of each of these n processors 10, 11, . . . 1n are executed. When each program is executed, the selection control circuit 31 selects the data signals of the n processors 10, 11, . . . 1n, and stores them in the storage device 32.
n address signals of the processors 10, 11, . . . 1n, and the n data buffers 40, 4.
The contents of 1,...4n are the n comparison circuits 5.
0, 51, . . . 5n, and when they match, n control signals indicating a matching state are sent to the comparison control circuit 36. The comparison control circuit 36 receives the n signals indicating the matching state, and when there is one or more signals indicating the matching state, generates a common control output signal 38 and outputs the common control output signal 38 to the n processors 10, 11. ,...1n to send control signals to n processors 10, 11,...1
Generates an interrupt to n processors 1
The execution of programs 0, 11, . . . 1n is stopped. On the other hand, if there is no signal indicating a matching state, the comparison control circuit 36 does not generate the common control output signal 38, and the n processors 10, 11, . . .
1n continues processing.

When a command to stop the execution of a program in the multiprocessor system is input through the key input device 34, the system control circuit 33 generates a common control signal 37, and
0, 11, . . . 1n control signals are generated, the execution of the programs of each of the n processors 10, 11, . is output to.

As explained above, the present invention sends a common control signal to a plurality of processors to simultaneously execute and stop the programs of the plurality of processors, and receives data from an arbitrary processor using a selection control circuit. By storing the information in a storage device and displaying it on a display device, it is possible to debug a multiprocessor system consisting of a plurality of processors, and the configuration and handling are significantly simplified.

[Brief explanation of the drawing]

FIG. 1 is a wiring diagram showing the connection between a conventional debugging device and a single processor system, and FIGS. FIG. 10,11,...1n...Processor, 2
0,21,...2n...Local memory, 30
... Debugging device, 31 ... Selection control circuit, 32
... Storage device, 33 ... System control circuit, 34
...Key input device, 35...Display device, 36...
Comparison control circuit, 40, 41,...4n...data buffer, 50,51,...5n...comparison circuit.

Claims (1)

[Claims] 1. In a multiprocessor system in which n (n≧2) processors each independently own a local memory and execute programs independently, n data buffers specify address signals of n processors; n comparison circuits that compare the address signal and the contents of the data buffer and generate a control signal indicating a matching state; and a common control output signal that receives the n control signals and outputs a common control output signal to the n processors. a comparison control circuit for generating data; a selection control circuit for selectively receiving data signals from the n processors; a storage device for storing data received by the selection control circuit; a key input device; a display device; a system control circuit that generates a control signal according to the contents of data inputted by an input device, receives the address signals of the n processors, compares them with the contents of the n data buffers, and determines whether they match. If there is one or more of them, the comparison control circuit generates the common control output signal and generates an interrupt to the n processors to stop the execution of the programs of the n processors. 2. A debugging device for a multiprocessor system, wherein if there is no matching data signal, the selection control circuit selectively receives data signals from n processors and stores them in the storage device.