JPS5849903B2 - Computer parallel connection system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a computer parallel connection system, and particularly to a computer parallel connection system in which a single or plural input/output devices are controlled by a plurality of computers.

Conventionally, there has been a computer system of this type as shown in FIG.

In FIG. 1, IA and IB are computers (hereinafter abbreviated as CPU) that perform arithmetic control, and 2 is a computer that controls CPUIA or CPU in response to the operation of CPUIA or CPUI B.
This is a computer parallel connection device (hereinafter simply referred to as CPC) that automatically switches the bus (hereinafter referred to as ``BUSj'') from PUIB.

Registers 2A and 2B accessed by CPUIA and CPUIB are provided in CPCZ.

31 to 3n are input/output devices (hereinafter abbreviated as I/O) controlled by CPUIA or CPUIB,
These ■/031 to 3n are all CPUIA or C
It has an interrupt request function for PU1B.

4A and 4B are BUs from CPUIA and CPUI B, respectively.
S, and 5 is a common BUS shared by I/031 to 3n.

This common BUS5 changes to BUS4A according to the switching of CPC2.
, BUS4B.

Reference numeral 6 denotes an I/O specification BUS for specifying I/031 to I/03n, and the contents of either register 2A or 2B are output according to switching of CPC2.

The operation will be explained.

For example, consider a case where the CPUIA attempts to control the I/032.

In this case, the CPUIA first records address information specifying the I/032 in two registers in the CPC2.

Next, the CPU 1A reads the contents of the register 2B and compares the contents with the contents just stored in the register 2A.

If they match, CPUI B has I/032
The CPUIA determines that the CPU is operating register 2.
Clear the person's information and give up control of ■/032.

If they do not match, it is determined that the /032 is inactive, and the CPUIA sends activation start information to the I/032 via BUS5.

Subsequently, the CPU 1A sends information regarding operation designation and control to the I/032 on the BUS 5, and causes the I/032 to perform the desired operation.

At this time, the register 2A in the cPU2 contains the CPU
Normally, the address information of ■/032 on which A performed the operation is held.

On the other hand, CPUIA sends boot start information to I/032,
Information regarding operation designation and control is sent to BUS4A. Common B
After being sent via US5, it is completely released from the control of I/032 and other information processing etc. are performed.

This is done in this manner in order to make effective use of the CPU, since the operation of the input/output device is normally slower than the operation of the CPU.

Now, ■ If /o32 completes the operation specified by CPUIA, if (7) L/ register 2 in CPC2
If address information corresponding to A2/032 is not set, an interrupt request signal cannot be sent from ■/032 to CPUIA via common BUS 5.

However, when the I/032 completes its operation and the register 2A has address information corresponding to the I/032, that is, when the cPc2 switches to the CPUIA side, an interrupt request signal indicating the completion of the operation is sent. CPUI
Send to A.

By the way, since the conventional computer parallel connection system was configured and operated as described above, it had the following drawbacks and inconveniences.

That is, first, the number of people connected to the common BUS 5 (
As the number of I/Os increases, the number of signals on the I/O designation BUS 5 that designates and sends the address information increases.

This requires a considerable amount of additional work, for example, when the I/O is located at a considerable distance from the CPU.

Second, once the CPU 1A or CPUIB starts a certain input/output device (I/O), it cannot start another I/O until the operation of that I/O is finished. It is.

Third, if register 2 or 2B in the parallel connection device (CPC) 2 is not set for a specific input/output device (I/O), the I/O will not be able to handle the CPU. An interrupt request cannot be made.

That is, it is not possible to issue a request from the I/O to the CPU, for example, an interrupt such as a service request from the I/O side.

Therefore, the main object of the present invention is to provide a computer parallel connection system that can eliminate the above-mentioned drawbacks.

To summarize this invention, multiple I/Os within the cPc
Instead of a register that holds address information specifying the address information, a register is provided that stores which one of multiple cPUs connected in parallel is using the common BUS, and the output of this register is used as a CPU selection signal for I/0. The C as a line
A PU selection signal line is commonly connected to each I/O, and each I/O
/O is provided with a resistor that stores whether there has been an access from one of the plurality of CPUs in response to the input from the CPU selection signal line.
Computer parallelism allows for a large degree of freedom in requesting multiple CPUs from multiple I/O sides in terms of the manner in which I/O operations are performed only after receiving an I/O specification from It is a connected system.

The above objects and features of the present invention will become more apparent from the following detailed description with reference to the drawings.

FIG. 2 shows a computer parallel connection system showing one embodiment of the present invention.

FIG. 2 differs from FIG. 1 in the following points.

That is, instead of the registers 2A and 2B for holding address information for I/O designation in the CPC2 shown in FIG. 1, in FIG.
Which BUS of each BUS4A or 4B of UIB
A register 2R is provided to indicate whether or not the terminal is connected to the common BUS5.

In addition, the output signal line 7 of the register 2R (in the embodiment shown in FIG. 2, there are two CPUs, so the status display is 1)
Bits are fine.

For this reason, only one output signal line 7 is shown in FIG.

) It becomes a CPU selection signal and each individual I/O 31 to 3n
It is included in.

Registers 31R to 3nR that receive the CPU selection signal and match detection circuits 31C to 3nC that compare the contents of the registers 2R and 31R to 3nR are provided for /031 to 3n, respectively.

Furthermore, the address information for specifying ■/o is the common BUS.
5.

For example, the operation is such that cPU1A communicates with the I/O32
Assume that a certain operation specified by the PUIA is to be performed.

In this case, the cPU 1A carries address information specifying the I/032 and control information specifying the operation and sends it to the BUS 4A.

At this time, Regisk 2R in CPC2 is automatically in state A to indicate that the access is from CPUIA (this is
For example, this signal corresponds to a high (H) voltage level signal), and this state A signal is output to the CPU selection signal line 7.

By the way, if the register 32R of I/032 is in state B (
This corresponds to, for example, a low (L) signal at a voltage level corresponding to the state A) and I
If /032 is in operation, this I/032 is CP
Assuming that the operation specified by UIB has not been completed, CPUI A→BUS4A-+CPC2-) Common B
US5-) While ignoring the information that came along I/032,
cPU1A suspends control of ■/032.

On the contrary, the contents of register 2R in CPC2 indicating that CPUIA is accessing the I/O side (
When state A) is taken as the contents of the register 32R in the I/032, the I/032 takes in the information sent through the route.

At this time, in order to ensure the link (coupling) between the cPU1A and the I/032, it is better to send a coupling confirmation signal from the I/032 to the CPUIA.

Next, CPUIA starts I/032 and then I/0
32 operation designation information, etc. are sent, and the desired operation is performed.

The contents of the registers 2R and 32R are compared by a match detection circuit 32C.

Now, after the CPUIA sends the operation designation information to the I/032, the CPUIA is released from control regarding the I/032.

In other words, cPU1A may access other I/Os, may receive interrupt requests from other I/Os, or may perform information processing independent of I/O control. .

Regarding CPUI B, the CPUIA mentioned above is I/03.
Of course, it operates in the same manner as when controlling CPUIA 2, and when it is released from I/O control, it operates in the same manner as when the above-mentioned CPUIA is released from I/O control.

That is, CPU I A, CPU I B (7
) The operation mode is exactly the same.

If the operating modes are similar, for example, the CPUIA performs the main control, and the CPUIB may be considered to be used as a backup when the functions of the CPUIA are reduced or when the load on the CPUIA increases.

Now, when the I/032 completes the operation specified by the CPUIA, the I/032 attempts to issue an interrupt request to the CPUIA.

At this time, the contents of register 2R in CPC2 are in state A, that is, the CPU currently using common BUS5.
is a signal indicating that it is CPUIA and before ■/0
I indicates that the CPU specified for operation in 32 is CPUIA.
When the contents of register 32R in /032 match,
I/032 immediately sends the I/03 to CPU1A.
The interrupt request signal including address information No. 2 is sent out.

When the CPUIA side receives this interrupt request signal, it determines which I/O the interrupt request is from and sends the interrupt request to the corresponding I/0.
Perform processing related to the action specified in 32, and finally
/032 ends control.

The final processing for this I/0332 requires the I/032
This also includes resetting the register 32R within.

CPUiA or CPUIB is each individual ■/o31-3
The mode of controlling n is accomplished by repeating the above-described procedure.

The CPC2 applied to the above embodiment is mainly suitable for sequence control for plants, etc., but it can also be effectively used for other purposes.

Further, although the number of CPUs connected to this CPC is two in the above embodiment, it goes without saying that the number of CPUs connected to the CPC may generally be two or more.

As described above, according to the present invention, the conventional I/O specification B
Since we adopted the CPU selection signal line instead of US, ■/
Even if the number of o's increases, there is no need to add address information lines corresponding to the increase.

If the number of CPUs is to be increased, simply one or two CPU selection signal lines are sufficient.

In addition, since the I/O address is not held in the register in the CPC, after a specific CPU gives operation specification information to a specific I/O and starts it, that CPU Freed from O's control.

Therefore, the CPU can control and operate the I/O at the same time.
In principle, the number of 0's can be seen as n (the number of all I/Os).

Furthermore, conventionally, if I/O address information from the CPU is not stored in a register within the CPC, the I/O
Although it was not possible to access (interrupt request) from the O side to the CPU side, it is possible to simply provide a register in the CPc to display the status of which one of the multiple CPUs is using the common BUS. Therefore, the degree of freedom in making interrupt requests to the CPU from the I/O side has increased.

For example, if you want to make a service request from a certain I/O to a specific CPU, you can simply set the contents of the register that receives the CPU selection signal in the I/O to a state in which the specific CPU operates. It also has the advantage that it can be done at any time.

The system configuration of the present invention also has the advantage that there is no need to make any changes to the conventional system configuration.

In other words, the register for the /o specified BUS can be used as a register for the CPU selection line by simply changing the connection method, and when adding registers on the I/O side, it is usually necessary to add registers for the I/O. Since it is equipped with many registers, it is sufficient to use one or several of them.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a conventional computer parallel connection system. FIG. 2 is an explanatory diagram of a computer system in which the present invention is implemented. In the figures, the same reference numerals indicate the same or equivalent parts, IA and IB are computers (CPU), 2 is a computer parallel connection device (CPC), and 31, 32, . . . 3n are input/output devices (I/O). , 4A, 4B are CPU (7) BUS, 5 is common BUS. 6 is I/O specification BUS, 7 is CPU selection signal line, 2A, 2B, 2R, 31 R, 32R, ... 3n
R represents a register, and 31C, 31C, . . . 3nC represent a coincidence detection circuit.

Claims (1)

[Claims] 1. A plurality of computers, an input/output device that can be controlled by each of the computers, and a parallel connection device that selectively controls one of the computers to be connected to the input/output device via a common bus. A computer parallel connection system further comprising: a first selection storage register provided in the parallel connection device and storing which of the computers is selected; and a first selection storage register provided in the input/output device. a second selection storage register that holds the contents of the register; and a coincidence detection circuit that compares the contents of the first and second selection storage registers; 1. A computer parallel connection system, characterized in that when a computer is output, an interrupt request can be issued to the selected computer via the common bus.