JPH0683640A - Interruption response processing system - Google Patents

Abstract

PURPOSE:To process an interruption response at a high speed by giving a system setting command in the one-word area of the head address of an interruption handler that is read out by an interruption request for execution of the interruption processing. CONSTITUTION:The information on a program counter (PC) 7a, a processor status word PSW 8a, a user stack printer USP, a previous bank pointer (PBP) 10, and general-purpose register are saved into a bank (RAM). An interruption controller (IRC) transfers the vector value assigned to an interruption permitting factor to a CPU 1 and calculates the head address of an interruption handler. The CPU 1 includes (16 bits X 3) pieces of core internal buses 12, and the vector value so far read by the CPU 1 as the 8-bit data is latched by a data register and latched with a 5-bit left shift. Thus the vector value is multiplied by 32 so that an area is secured for the interruption handler.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt response processing system capable of performing high-speed response processing until the start of interrupt processing, which is particularly effective in a single chip microcomputer.

[0002]

2. Description of the Related Art When a specific request due to an exceptional event occurs in a process of a single-chip microcomputer or the like, the process currently being executed is interrupted and another process is started. The sequence until the start of another process according to the related art will be described below.

In the prior art, when an interrupt request due to an exception event is accepted, the processing of the routine currently being processed is interrupted and the requested interrupt processing routine is entered, but when the interrupt processing is completed. , It is necessary to return to the interrupted processing routine and continue the processing. Therefore, when an interrupt request is accepted, the status register (SR) and program counter (PC) immediately before the interrupt occurred.
Will be automatically saved. After that, the exception vector table is referred to, the address value is branched to the address value described in the exception vector table, and interrupt processing is sequentially started.

In the interrupt processing, first, a vector value corresponding to an interrupt factor is generated. A vector table address is calculated using the generated vector value. The exception vector table is referred to by the address generated by the address calculation, and the address value that is described in the exception vector table and indicates the start address of the interrupt processing routine is read.

For setting various modes used in the interrupt processing routine, various modes are set by a program at the beginning of the interrupt processing routine. For example, switching banks or switching systems. Substantially, the start of the interrupt process comes after completing the various mode settings. For example, the MC68000 will be described as an example. It will be described with reference to FIG. 5 on the assumption that an interrupt of an exceptional event has occurred.

Each interrupt factor has an interrupt priority,
There are 7 levels. Central processing unit (CPU)
The interrupt request is given by encoding each priority of the interrupt factor.

FIG. 5A shows the bit allocation of the status register (SR). There is an interrupt mask (3 bits) in the status register (SR), which indicates the priority order at that time. If the priority level of the interrupt factor is higher than the priority level of the interrupt mask (3 bits), the interrupt exception processing sequence is started. It is assumed that the interrupt factor is accepted and the interrupt exception processing sequence is started.

First, the lower word of the program counter (PC) is saved in the stack (SSP), and the contents of the status register (SR) are temporarily stored.
Then, the S bit of the status register (SR) is set, and the privileged state is set to the supervisor state. At the same time, the T bit is reset so that the execution of the exception handling routine is not disturbed by the trace operation. After setting the status register (SR) for exception processing, the central processing unit (CPU) reads the vector number shown in FIG. 9B assigned to each interrupt factor.

Using this vector number, the address of the exception vector table (2 words) storing the exception vector is generated as shown in FIG. An exception vector is a memory location of a routine that handles exceptions stored in the exception vector table (2 words).

The higher-order status register (SR) and program counter (PC) temporarily stored are saved in the stack (SSP). Then, the exception vector is referenced using the address of the generated exception vector table (2 words). New program counter (PC)
The value is read from the exception vector as shown in (d) of the figure, and the exception processing for the actual interrupt factor is started.

As described above, the central processing unit (CPU) reads the vector value corresponding to each interrupt factor, and uses the vector value to calculate the address of the exception vector table. Then, by referring to the exception vector in the exception vector table, the value indicated by the exception vector becomes the start address for starting the actual interrupt processing. In this case, by referring to the exception vector once, the response time from the acceptance of the interrupt to the start of the actual interrupt processing will be delayed. As another example, the occurrence of an TLCS-900 interrupt will be described.

Similar to the previous example, the priority is assigned to each interrupt factor, and the interrupt factor is accepted according to the priority. Figure 5 (e) shows the bit allocation of the status register (SR).

By comparing the priority of the generated interrupt with the interrupt mask of the status register (SR), when the priority of the generated interrupt is higher, it means that the interrupt is permitted and accepted. . When the interrupt is accepted, the central processing unit (CPU) reads the interrupt vector from the interrupt controller.

The central processing unit (CPU) saves the program counter (PC) and status register (SR) in the stack on the system side. Status register (S
In the R) interrupt mask (IFF2 to 0), the priority of the accepted interrupt is incremented by "+1" and set to a value. The system mode (SYSM) of the status register (SR) is set to shift to the system mode. Then, the central processing unit (CPU) calculates the start address of the interrupt processing routine using the read interrupt vector value. After the start address is generated, the execution of the interrupt processing routine is started.

As described above, the interrupt is permitted, the central processing unit (CPU) reads the interrupt vector from the interrupt controller, and saves the program counter (PC) and the status register (SR) in the stack on the system side. Then, the interrupt vector is used to calculate the start address of the interrupt processing routine and branch to the interrupt processing routine.

With this configuration, the processing from the acceptance of the interrupt to the start of the interrupt processing routine is fast,
To set the various modes and execute the interrupt processing for the interrupt factor, after the interrupt processing routine is started, the bank will be switched and the various modes will be set by the program. Therefore, the response time until the actual interrupt processing is started becomes slow.

[0017]

DISCLOSURE OF THE INVENTION As in the example described above,
A system used by the interrupt process by referring to the vector table with the generated vector value, reading the address value described in the vector table to the start address of the interrupt process routine, and starting the interrupt process. Processing such as switching the mode of the memory, switching the current bank, etc., the program counter (PC), the status register (S
R) needs to be saved.

In the prior art, after performing these processes and saving, the start address of the interrupt process routine is calculated using the vector value, which is a sequential flow. Therefore, there is a problem that the response time from the occurrence of an interrupt due to an exception event to the execution of the actual interrupt processing routine is slow, and a high-speed interrupt response cannot be performed.

The present invention has been made in order to solve such a problem, and is capable of high-speed response processing after acceptance of an interrupt request and having a high degree of freedom in setting various interrupt modes and the like. The purpose is to provide a processing method.

[0020]

According to the interrupt response processing method of the present invention, a system setting command for interrupt processing is provided in at least one word area of the head address of an interrupt handler read when an interrupt request occurs. It is characterized by that.

[0021]

[Function] By configuring in this way, PC, PSW
Since the address of the interrupt destination is calculated and the interrupt process is started while saving the status information such as "etc.", high-speed interrupt response process becomes possible.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block configuration diagram showing a system configuration of an embodiment of the present invention, and FIG. 2 is a block configuration diagram showing an internal configuration of a central processing unit (CPU).

In FIG. 1, reference numeral 1 is a central processing unit (CP).
U), 2 is a bank (RAM), 3 is an interrupt controller (IRC), 4 is a peripheral device (I / O), and 5 is a main system bus (MBUS) connecting them. The central processing unit (CPU) 1 and the bank (RAM) 2 are connected by a dedicated bus 6.

The interrupt controller (IRC) 3 receives an interrupt request signal from the peripheral device 4 as shown in FIG.
An interrupt generation signal is sent to the central processing unit (CPU) 1 and an interrupt acceptance signal is received if interrupt processing is possible.

As shown in FIG. 2, the inside of the central processing unit (CPU) 1 is a bus interface unit 7, an arithmetic logic unit (ALU) 8, and a register file 9 whose detailed structure is shown in FIG. 4A. , A previous bank pointer (PBP) 10 indicating the number of the register bank used immediately before and a current bank pointer (CBP) 11 indicating the current register bank number are provided, and the core internal bus (IBUS) 12 is provided. Are connected to each other by.

Further, the bus interface unit 7 has a program counter (PC) 7a and an arithmetic logic unit (AL).
U) 8 is provided with a processor status word (PSW) 8a. The register file 9 is connected to the bank (RAM) 2 by a dedicated bus 6. Figure 3
(a) ~ (h) is an explanatory diagram of a command configuration for explaining the operation of this embodiment.

Further, FIGS. 4A and 4B show the register file 9
FIG. 3 is an explanatory diagram illustrating an example of a case where the information being processed for the interrupt processing for the detailed event and the exception event is saved in the bank (RAM) 2.

In FIG. 1A, the register file 9 is composed of registers, 9a is a user stack pointer (USP), 9b is an interrupt stack pointer (ISP), and 9c is an emulator stack pointer (E).
SP) and R0 to R15 are general-purpose registers. In the system having such a configuration, an interrupt response processing method for an exceptional event of this embodiment will be described with reference to FIGS. 1, 2, 3 and 4.

An exceptional event is a normal operation flow of a single-chip microcomputer in response to the occurrence.
This is a well-known method of changing. Exceptional events include those generated by internal factors and those generated by external factors.

For example, for those generated by internal factors,
When an instruction with a bit pattern different from the correct bit pattern is fetched during program execution, an undefined instruction violation occurs, and various instructions are privileged for the purpose of protecting the system. There is a privileged instruction violation that causes an interrupt when used in mode.

Resets, interrupts from peripheral devices, etc. are generated by external factors. When a plurality of exception events occur at the same time, they are determined and caused by the priority relationship assigned to each factor.

An example of the exception event to be described below is an interrupt from a peripheral device which is generated by an external factor. When a plurality of exception events occur simultaneously, the interrupt having the highest priority among them is the interrupt. It is assumed that the factors have been accepted. The technical terms that will appear in the explanation below will be defined in advance.

The interrupt generation signal (INT) means that the interrupt request from the peripheral device has a priority order assigned to each, and the interrupt controller (IRC) 3 recognizes the priority order and performs a central operation. This is a signal that notifies the processing device (CPU) 1 that an interrupt has occurred.

The interrupt acceptance signal (INTACK) means that the central processing unit (CPU) 1 decides to accept the interrupt depending on the priority of the interrupt factor and the state of the discrimination element for permitting the interrupt, and the interruption is accepted. This is a signal notifying that the interrupt has been accepted by the interrupt controller (IRC).

The interrupt processing response time is the EIT after the interrupt request is accepted (after the central processing unit (CPU) 1 outputs an interrupt acceptance signal (INTACK) to the interrupt controller (IRC) 3). This is the time from when the mode is executed until the processing for the actual interrupt factor is started.

The interrupt response bus cycle (IABC) is
The central processing unit (CPU) 1 receives an interrupt acceptance signal (INT
It is a cycle from the output of (ACK) to the interrupt controller (IRC) 3 until the central processing unit (CPU) 1 reads the vector value from the interrupt controller (IRC) 3. The interrupt handler is a routine that interprets the EIT mode, executes processing for an interrupt factor, and completes the processing. The interrupt handler routine is E
This is a process for an actual interrupt factor after the IT mode is executed and the mode is set. The dedicated bus 6 is a 64-bit wide bus that interfaces the register file 9 and the bank (RAM) 2 at the time of saving / restoring information by an interrupt.

The EIT mode is a command for setting various modes (bank switching, number of registers used, etc.) in which an area for at least one word is provided at the head address of the interrupt handler. In response to an interrupt request from the peripheral device 4, the interrupt process according to a predetermined sequence is started. The sequence from this to the start of the interrupt process will be described.

When the peripheral device 4 generates an interrupt request signal (INTREQ) due to a certain factor, a predetermined sequence is started, and the peripheral device 4 interrupts the interrupt controller (IRC) 3 that controls interrupts. A request signal (INTREQ) is transmitted. As described above, the priority is assigned to each factor in the exceptional event. The interrupt controller (IRC) 3 recognizes the priority of the interrupt factor by the interrupt request signal (INTREQ) from the peripheral device. After recognizing the priority, the interrupt controller (IRC) 3 sends an interrupt generation signal (INT) indicating that an interrupt has occurred to the central processing unit (CP).
U) Output to 1.

In response to the interrupt generation signal (INT) from the interrupt controller (IRC) 3, the central processing unit (C
The PU) 1 determines whether to accept the interrupt based on the priority of the interrupt factor and the state of the determination element that permits the interrupt. As a discrimination element, as shown in FIG. 3A, the interrupt enable flag (E) of the processor status word (PSW) 8a is used.
I) and interrupt mask (IM).

In the figure, C, V, N and Z are condition codes, TM is a task mode for designating a task, BS is a bank size, DI is a delay interrupt designation, and RG is a privilege mode designation. SS is the designation of single step operation.

The maskable interrupt is permitted by the EI flag if the maskable interrupt is enabled. As described above, priority is assigned to each factor for the exceptional event. The interrupt can be accepted when the priority of the generated interrupt factor is higher than that of the state of the IM flag.

As an example of the priority order, the IM flag is set to PS.
It is assumed that 3 bits are provided in W and 7 steps (7 levels) are provided as the number of priorities. When the IM flag is set to 2, it indicates a priority level of 2. The larger the value indicated by the priority, the higher the priority. The interrupt factor that occurred is priority 5
At this time, when the IM flag is set to 2, the interrupt factor that has occurred has a higher priority, so the interrupt can be accepted. Then, the IM flag is set to a value obtained by raising the priority of the accepted interrupt by one level. Here, the IM flag is set to 6.

When the number of interrupt factors increases so that the interrupt priorities cannot be individually assigned, the IM flag of the PSW is expanded from 3 bits to 4 or 5 bits, or the priority is further increased in the same priority. By assigning, it is possible to deal with the increase in the number of interrupt factors.

In the interrupt enabled state, the priority of the interrupt factor is
When the interrupt is accepted because the priority is higher than that indicated by the IM flag, the central processing unit (CPU) 1 informs the interrupt controller (IRC) 3 that the interrupt is generated and accepted (INTACK). Is output, and the interrupt response bus cycle is started by the interrupt acceptance signal (INTACK).

At the same time, the program counter (P
C) 7a, processor status word (PSW) 8a,
User stack pointer (USP) 9a, pre-deposit bank pointer (PBP) 10 and general-purpose registers R0-
Information in R15 is transferred to main system bus (MBUS) 5
The operation of saving the data in the bank (RAM) 2 via the dedicated bus 6 is performed without passing through. This will be described later.

When the interrupt controller (IRC) 3 receives the interrupt acceptance signal (INTACK), it outputs the vector value assigned to the interrupt-enabled factor to the main system bus (MBUS) 5 and outputs the vector value to the center. Transfer to the processing device (CPU) 1. Figure 3 (b) shows the format of vector values.

However, in this embodiment, it is assumed that the vector values assigned to each factor of interrupts are such that consecutive numerical values are assigned to each interrupt factor. Other cases will be described later.

The vector value transferred to the central processing unit (CPU) 1 is used to calculate the address of the head address where the interrupt handler is located. As an actual address calculation procedure, the bus interface (BI) of the central processing unit (CPU) 1 is used.
U) Calculate using 7.

Of a single-chip microcomputer,
The vector value transferred via the internal main system bus (MBUS) 5 is latched in the data register in the bus interface unit (BIU) 7.

Inside the central processing unit (CPU) 1, 1
There is a core internal bus (IBUS) 12 of 6 bits × 3 lines. Central processing unit (CP
U) The vector value read into 1 is latched in the data register. The vector value is then transferred to the core internal bus (I
Bus interface unit (BI)
U) Latched in the address register in 7.

When it is latched in the address register, it is left shifted by 5 bits and latched. By shifting to the left by 5 bits, the read vector value is multiplied by 32. By multiplying by 32, the area of the interrupt handler is secured, and one interrupt handler corresponds to 16 words.

When 16 words are not required, it is possible to reduce the area by 8 or 4 words by shifting 4 or 3 bits without shifting 5 bits. It becomes possible to deal with the interrupt factor of. For ease of understanding, the method of calculating the start address of the interrupt handler will be represented by a mathematical expression. It is as follows. INTha = Vec × 32 + VecBase INTha ... Interrupt handler start address Vec ... Vector value VecBase ... ROM start address The start address of the interrupt handler is added by adding the start address (VecBase) of the ROM to the value latched in the address register.

For example, the start address of the ROM (VecBas
Assuming that e) is assigned to 8000H, as shown in Fig. 3 (c), 1 is set in the 15th bit, 0 is set in the 14th and 13th bits, and the remaining 12 to 0 bits are vector values to the left. The value is bit-shifted. With the above, the start address (INTha) of the interrupt handler is generated.

As described above, when an interrupt is generated, the address of the start address (INTha) of the interrupt handler is calculated, while the program counter (PC) 7a, the processor status word (PSW) 8a, the user stack pointer (USP) 9a, Pleasure Bank Pointer (PBP)
10 and information of general-purpose registers (R0 to R15) without passing through the main system bus (MBUS) 5;
The evacuation is done via. The saving of information due to the occurrence of this interrupt will be described.

The central processing unit (CPU) 1 sends an interrupt acceptance signal (INTACK) to the interrupt controller (IRC) 3
Then, the vector value is read from the interrupt controller (IRC) 3, and the address saving operation is performed while executing the address calculation of the interrupt handler.

The procedure of saving will be described. As the information to be saved, a program counter (PC) 7a, a processor status word (PSW) 8a, shown in FIG.
User stack pointer (USP) 9a, pre-deposit bank pointer (PBP) 10 and general-purpose registers R0-
The five items of information in R15 are saved using the dedicated bus 6. The dedicated bus has a 64-bit width and is logically 1
Information of 6 bits × 4 registers can be transferred.

The structure of each register is as follows.
Each register of R15 is 16 bits, the program counter (PC) 7a is 24 bits, the processor status word (PSW) 8a is 16 bits, the user stack pointer (USP) 9a is 16 bits, and the previa bank pointer (PBP) 10 is It is 8 bits, and as a combination of transfer, a program counter (PC) 7a, a processor status word (PSW) 8a, a user stack pointer (USP) 9a, and a pre-bank bank pointer (PB).
P) 10 is set as one set, and general-purpose registers R0 to R15 are set as 4 sets of 4 sets, and a total of 5 sets are used to save information.

The information of the five sets of combinations is saved in the bank number of the value indicated by the current bank pointer (CBP) 11, and the saving operation is started at the same time when the interrupt is accepted. The information saved in the general-purpose registers R0 to R15 is saved first.

The registers in the register file 9 are
General-purpose registers R0 to R15, user stack pointer (USP) 9a, interrupt stack pointer (IS
P) 9b, emulator stack pointer (ESP) 9
c, which is the remaining information that needs to be saved, that is, the program counter (PC) 7a, the processor status word (PSW) 8a, and the previous bank pointer (PB).
The information of P) 10 needs to be transferred to the register file 9 using the core internal bus (IBUS) 6 in order to save it.

While the program counter (PC) 7a, the processor status word (PSW) 8a, and the pre-presence bank pointer (PBP) 10 are transferred, the information in the general-purpose registers R0 to R15 is saved in the bank (RAM) 2. Let The transferred program counter (P
C) 7a, processor status word (PSW) 8a,
The information of the Pre-Bank bank pointer (PBP) 10 is temporarily stored in the already saved register group of the general-purpose registers R0 to R15 for the time being.

As an example, it is assumed that the general register is saved from the larger register number. The registers saved first are R15 to R12, and the transferred program counter (PC) 7a, processor status word (PSW) 8a, and pre-via bank pointer (PB).
The information of P) 10 is saved in the register groups R15 to R12.

The lower 16 bits of the program counter (PC) 7a are transferred to the general-purpose register R12, and the preceding bank pointer (PBP) 1 is transferred to the upper 8 bits of R13.
The upper 8 bits of the program counter (PC) 7a are transferred to 0 and the lower 8 bits. The user stack pointer (USP) 9a is transferred to R14, and the processor status word (PSW) 8a is transferred to R15.

The size of one bank corresponds to four words. The bank number of the value indicated by the current bank pointer (CBP) 11 is a bank for saving the program counter (PC) 7a, processor status word (PSW) 8a, user stack pointer (USP) 9a, and pre-via bank pointer (PBP) 10. The general purpose registers R0 to R15 are used as the current pointer (CBP) 11
Of the bank number (R to +1 to +4 added to the value
AM) 2) to the bank.

As an example, the current bank pointer (C
When the value of the BP) 11 is 15, the bank to which the information to be saved is saved in the bank (RAM) 2
It is shown in Fig. 4 (b).

Program counter (PC) 7a, processor status word (PSW) 8a, user stack pointer (USP) are stored in bank 15 of bank (RAM) 2.
9a and the Previa Bank Pointer (PBP) 10 are saved, the general-purpose registers R0 to R3 are stored in the bank 16, the general-purpose registers R4 to R7 are stored in the bank 17, and the general-purpose register R is stored.
8 to R11 are bank 18 and general-purpose registers R12 to R1
5 are saved in the bank 19, and 5 banks are used to save the information in total. As described above in this example, the order of evacuation is evacuation from the bank 19 to the smaller bank number in the order of 1 to 5 as illustrated.

When the saving of information in the bank (RAM) 2 is completed and the start address of the interrupt handler is generated, the process branches to the start address of the interrupt handon. At the start address of the interrupt handler,
A mode setting command called EIT mode is provided for one word. The EIT mode will be described below. By setting each mode of the EIT mode provided at the first address of the interrupt handler, the mode used in the interrupt handler routine can be set.

In the EIT mode, bits are assigned so that banks can be switched (bank switching mode). If there are a total of 256 banks,
As shown in (d), it can be expressed by using the lower 8 bits of the EIT mode. If the bank number is set to a value other than 0, it means that the bank is switched.

The operation of storing the return information is started based on this bank number. First, the value indicated by the current bank pointer (CBP) 11 is transferred to the previous bank pointer (PBP) 10. Now you can remember the bank number you were using before. The bank number used in the interrupt is transferred to the current bank pointer (CBP) 11.
Information of the general-purpose registers R0 to R15 is transferred to the register file 9 from the designated bank.

If the bank number is set to a value of 0, it means that the bank is not switched.
The operation without switching the bank is performed by the program counter (PC) 7a, the processor status word (PSW) 8a, and the user stack pointer (USP) 9 saved in the bank.
a, the Previous Bank Pointer (PBP) 10 becomes invalid and will be newly saved to another location. It is saved in the area of the value indicated by the stack pointer.

Since the banks are not switched, 0 is set in the pre-bank bank pointer (PBP) 10 and the current bank pointer (CBP) does not need to be changed. Further, since the banks are not switched, the general purpose registers R0 to R15 existing in the register file 9 are used.

However, the program counter (PC) 7
a, the processor status word (PSW) 8a, the user stack pointer (USP) 9a, and the pre-previous bank pointer (PBP) 10, the general-purpose registers R12 to R15 were previously used as temporary storage registers. It is necessary to write back the general purpose registers R12 to R15 of the register file 9 from the RAM2. When the general-purpose registers R12 to R15 need to be saved, they are saved in a stack or the like by a program or banks are switched by a program.

As shown in FIG. 3 (e), it is possible to allocate bits capable of setting the number of registers used in the interrupt handler routine in the EIT mode (used register number mode).

The dedicated bus 6 is used to transfer the information saved in the bank (RAM) 2 to the register file 9, and the contents of four registers are transferred at a time. Therefore, there are four cases of 4, 8, 12, and 16, which can be represented by 2 bits.

When the number of registers used in the interrupt handler routine is not so large, if the number of used registers is set to 4 or 8 registers, unnecessary register transfer time can be omitted and the interrupt handler routine can be executed quickly. Can start execution.

It is assumed that another interrupt having a higher priority than that of the currently executing interrupt is generated and accepted during execution of the interrupt handler routine. Also in this case, the evacuation operation described above is started. The first interrupt is interrupt 1, and the subsequent interrupt is interrupt 2. In the case of interrupt 2 also, the program counter (PC) 7a and processor status word (PSW) 8
a, user stack pointer (USP) 9a, previous bank pointer (PBP) 10, general-purpose register R0
The information in R15 is saved.

Here, the number-of-used-registers mode of the EIT mode becomes effective. If, for example, the number of used registers is 4 in interrupt 1, the number of times of transfer to the bank (RAM) 2 is as follows: the program counter (PC) 7a, the processor status word (PSW) 8a, the user stack pointer (USP) 9a, and the previous bank pointer. (PB
P) 10 sets and general-purpose registers R0 to R3 are transferred twice.

That is, it is not necessary to transfer all of the general purpose registers R0 to R15, which leads to an improvement in processing speed. The same applies to the return, and when the interrupt 2 exits the interrupt handler after the interrupt processing is completed, the general register R
If it is necessary to save 0 to R3, only the used registers need to be saved.

In addition, as shown in FIG. 3 (f), if the stack designation mode is assigned, the stack used in the interrupt handler routine can be designated. (Stack specification mode)

Further, the above-mentioned three modes can be assigned to one word. As an example, as shown in FIG. 3 (g), the lower 8 bits in the bank number designation mode, the upper 8 bits in the stack designation mode, the user stack pointer (USP) 9a and the interrupt stack pointer (ISP) 9a in 2 bits. The emulator stack pointer (ESP) 9c may be assigned another 2 bits of the upper 8 bits to the used register number mode, and the remaining 4 bits may be undefined. In addition, as shown in FIG. 3 (h), if the interrupt priority designation mode is assigned, the interrupt level used in the interrupt handler routine can be designated.

By assigning this interrupt level designation mode, a user-defined interrupt level can be designated. For example, it is assumed that this interrupt priority order designation mode does not exist in the EIT mode. When the IM flag is set to 2, it represents an interrupt priority of 2. The larger the value indicated by the priority, the higher the priority. When the IM flag is set to 2 when the priority level of the generated interrupt factor is 5, the interrupt factor generated has a higher priority level, and therefore the interrupt is accepted. And
The IM flag is set to a value obtained by raising the accepted interrupt priority by one level, and in this example, the IM flag is set to 6.

The problem here is that the IM flag indicates 6 when an interrupt of priority 5 is accepted. This means that there is an interrupt of priority 7 which has a higher priority than the accepted interrupt factor.

In other words, there is a possibility that a double interrupt will occur during execution of an interrupt process of priority 5. At this time, there is a demand from the user that he / she does not want to accept any interrupt factor other than the non-maskable interrupt currently being processed. Therefore, if there is a request for such an example due to the existence of this interrupt priority order specifying mode, the normal 6
If the IM flag set in step 2 is set to the highest priority level 7 in the interrupt precedence designation mode, only non-maskable interrupts will be accepted. However, if you want the priority 6 according to the IM flag without changing the interrupt priority, set 0 in the interrupt priority designation mode so that the interrupt priority is not changed. To do.

In the above, the operation was required because the vector values were assigned with consecutive values. Do not make the vector values continuous in advance,
Allocation is made according to each interrupt factor with a certain interval and without being allocated at equal intervals.

For example, when a large area for the interrupt handler is required, the interval between the next vector value is large, or when 2 words are sufficient for the area for the interrupt handler, the vector value interval is set to 4. It should be set.

With this vector value allocation method, the hardware configuration is such that the vector value is not shifted but the address is latched. It is possible to increase the number of interrupt factors by allocating vector values by combining the former and the latter.

Although the EIT mode described above is provided for about one word in the interrupt handler, it is necessary to set other modes such as bank switching, stack designation, and registers used. If so, see Figure 3.
As in the extended mode shown in (h), by expanding one word in the EIT mode to a few words, many modes can be set by the mode setting command (EIT mode). The present invention is not limited to the above embodiment,
Modifications can be made without changing the gist.

In the above embodiments, the single chip microcomputer having the register bank structure has been described. However, the method of interpreting the EIT mode by the microprogram and completing various mode settings before the start of the interrupt handler routine, which is the gist of the present invention, is sufficiently effective even in a single-chip microcomputer without a register bank configuration. Needless to say.

[0088]

According to the conventional technique, it is necessary to switch the interrupt processing routine such as bank switching and system mode switching after the execution of the interrupt processing routine is started, and the interrupt processing routine is executed before the actual interrupt processing routine is executed. Since the acceptance of the request, the interrupt response processing time has been remarkably required.

According to the present invention, the response time before setting the mode under the same condition and starting the actual interrupt processing routine is the existence of the EIT mode, and the EIT mode can be microprogram controlled, so that the conventional interrupt response is possible. The processing time can be shortened significantly.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a system configuration for explaining the present invention.

FIG. 2 is a block configuration diagram showing an internal configuration of a CPU of the system.

FIG. 3 is an explanatory diagram of a configuration of an EIT mode and another information array for explaining the configuration and operation of one embodiment of the present invention.

FIG. 4 is a block configuration diagram centering on a register file of the CPU for explaining the saving operation of the embodiment.

FIG. 5 is an explanatory diagram of conventional interrupt response processing.

[Explanation of symbols]

1 ... Central processing unit (CPU), 2 ... Bank (RAM),
3 ... Interrupt controller (IRC), 4 ... Peripheral device, 5 ... Main system bus (MBUS), 6 ... Dedicated bus, 7 ... Bus interface unit (BIU), 7a ... Program counter (PC) 8 ... Arithmetic logic operation unit ( ALU), 8a ... Processor status word (PSW) 9 ... Register file, 9a ... User stack pointer (USP), 9b ... Interrupt stack pointer (I
SP), 9c ... Emulator stack pointer (ES
P), 10 ... Previous Bank Pointer (PBP), 1
1 ... Current bank pointer (CBP), 12 ... Core internal bus (IBUS).

Claims (2)

[Claims] 1. An interrupt response processing system characterized in that a system setting command for interrupt processing is provided in at least one word area of a leading address of an interrupt handler read upon generation of an interrupt request. 2. The system setting command includes respective commands of bank switching for specifying a bank for saving information, number of registers used for specifying the number of registers used in interrupt processing, and stack specification for specifying a stack to be used. The interrupt response processing method according to claim 1.