JP2876629B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention includes a plurality of general-purpose register sets (hereinafter referred to as register banks) used for data processing, and registers used for interrupt processing requests from peripheral devices. The present invention relates to a data processing device that selects and switches a set and executes an interrupt processing program.

[Conventional technology]

Generally, in a microcomputer system,
When a peripheral device generates an interrupt processing request, the central processing unit (hereinafter referred to as a CPU) includes an interrupt control unit for interrupting the execution of the program and executing the processing program in response to the interrupt request from the peripheral device. I have. Also,
If the number of peripheral devices is large, a plurality of interrupt processing requests may be generated at the same time, or an interrupt processing request of another peripheral device may be generated while a program for an interrupt processing request of a certain peripheral device is being executed. In order to deal with such a conflict between a plurality of interrupt processing requests, a priority control function is provided for setting a priority order for each interrupt processing request and giving priority to execution of a processing program for an interrupt processing request having a high priority. ing.

As an interrupt processing method in a general microcomputer system, a program status word (hereinafter, referred to as PSW) that stores the contents of a program counter (hereinafter, referred to as PC) for specifying an address of a program being executed and a state during execution of the program. And the contents of general-purpose registers are saved on a stack, a start address of a processing program corresponding to a preset interrupt request is set in a program counter, and a vector interrupt processing method for executing interrupt processing is available.

According to this method, a lot of time is required for overhead processing such as saving or restoring the contents of the PC, PSW, and general-purpose registers to the stack or restoring. Is coming. The interrupt acceptance control by the register bank switching method will be described with reference to FIG.

FIG. 4 is a block diagram showing a conventional data processing device. When at least one of the interrupt request signals 140-1, 140-2, 140-3,... Is generated, the interrupt control unit 110 selects the interrupt request signal having the highest processing priority by priority control and determines that the interrupt request signal can be accepted. For CPU120,
An interrupt acceptance signal 141 is transmitted. The register bank selection control circuit 112 generates a register bank designation code for selecting a register bank to be used in interrupt processing,
It is stored in a register bank designation register (hereinafter referred to as RB) 123. Upon receiving the interrupt acceptance signal 141, the CPU 120 suspends the execution of the program and executes the interrupt processing program. That is, the CPU transmits the read signal 143 to the interrupt processing control unit 110, reads the register bank designation code, and switches to the register bank in the data memory 124.

As shown in FIG. 5, each register bank includes general-purpose registers, a PC save area, a PSW save area, and a start address of an interrupt processing program (hereinafter, referred to as PCI). The CPU 120 saves the contents of the PC 121 and the PSW 122 in a save area in the register bank of the switching destination, loads the PCI stored in the register bank of the switching destination into the PC 121, and starts and executes the interrupt processing program.

Recently, the number of peripheral devices has increased with the advancement of the functions of microcomputer systems, and the number of interrupt requests generated from the peripheral devices has also tended to increase. If all of such a large number of interrupt requests are to be handled by the register bank switching method as described above, register banks must be individually provided for each interrupt request and assigned. Have difficulty. Therefore, a plurality of interrupt requests must be processed using a common register bank. However, since the interrupt processing start address stored in the switching destination register bank cannot be set arbitrarily, individual processing corresponding to each interrupt request cannot be started.

[Problems to be solved by the invention]

As described above, in the conventional data processing device, when performing the interrupt processing by the register bank switching method, the start address of the interrupt processing program cannot be set arbitrarily for each interrupt request. And cannot perform individual processing corresponding to each interrupt request. Therefore, as a result, the number of interrupt requests that can be processed by the register bank switching interrupt is limited to the number of register banks.
The remaining interrupts have the disadvantage that they must be serviced by vector interrupts that have lower processing efficiency than register bank switching interrupts.

An object of the present invention is to provide a data processing device that can share a register bank for a plurality of interrupt requests and start an interrupt processing program corresponding to each interrupt in order to efficiently perform interrupt processing. is there.

[Means for solving the problem]

The configuration of the present invention includes a plurality of general-purpose register sets used by the central processing unit for processing, and switches to a predetermined general-purpose register set among the general-purpose register sets in response to an interrupt reception signal corresponding to an interrupt request signal. In a data processing apparatus for activating a processing program, a plurality of the interrupt request signals are grouped, and one general-purpose register set is assigned to each of the grouped groups; an interrupt request to be preferentially accepted is detected. Means for generating an acceptance status signal for each interrupt request; means for generating a different branch code for each interrupt request in each of the groups as encoding of the acceptance status signal; Means for controlling the start address of the interrupt processing program. Characterized in that the data interrupt process can be started branches for each of the interrupt requests of the same group.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. The data processing apparatus of this embodiment includes a CPU 20, a program memory 28, three sets of general-purpose registers (hereinafter referred to as register banks) used in an interrupt processing program, and one set of register banks used in a main program other than the interrupt processing program. Data memory 24, address bus 50,
Data bus 51, address decoders 26 and 27 for decoding addresses of data memory 24, interrupt request flag 15 provided for each interrupt request and indicating the state of occurrence of each interrupt request.
-1 to -12 (hereinafter referred to as IF1, IF2, ..., IC12),
When the interrupt request signals 40-1 to -12 are supplied, the interrupt priority control circuit 10 (hereinafter referred to as INTC) which determines the interrupt priority and the interrupt acceptance state, and registers a register bank designation code in response to each interrupt processing request. It comprises a register bank selection control circuit 12 to be generated, a branch code generation circuit 13 to generate a branch code for generating a start address of an interrupt program, and other peripheral circuits.

In the present embodiment, it is assumed that 12 interrupt request signals can be controlled, each is grouped, and one register bank is assigned to each group. For example, if INT1 to INT4 are in interrupt group 1, IN
T5 to INT8 belong to interrupt group 2, INT9 to INT12 belong to interrupt group 3, and RB1 and group 2
RB2 for group 3 and RB3 for group 3, respectively.

The CPU 20 sets P to specify the address of the program memory 28.
C21, PSW22, PC that stores the state during program execution
21 and a PSW 22, and a stack pointer 25 for specifying an address of the data memory 24 for saving the contents of the general-purpose register. The address output from the CPU 20 to the address bus 50 is decoded by the address decoder 27, and the corresponding address in the data memory 24 is selected. A register bank is arranged in the data memory 24, and a value of a register bank designation register (hereinafter referred to as RB) 23,
The register address output from the U20 to the address bus 50 is decoded by the address decoder 26 to select a register. In this case, one of the four register banks is selected by RB23, and each general-purpose register in the register bank is selected by the register address.

Next, register bank switching control will be described by taking, as an example, a case where the interrupt request signal INT2 is generated. When the interrupt request signal INT2 is generated, the interrupt request flag IF2 is set. The INTC10 searches IF1 to IF12 to determine whether or not the flag is set.If an interrupt request is generated by INT2 and it is detected that IF2 is set, the interrupt is enabled and the interrupt of INT2 is detected. Determine the priority. When it is determined that the interrupt is permitted and that the priority is higher than the process currently being executed, the interrupt selection signal 17-2 for INT2 is activated. At this time, the interrupt selection signals 17-1 to 17-12 other than 17-2 are inactive. Further, the INTC 10 activates the interrupt acceptance signal 41 for the CPU 20. Interrupt selection signal 17-2 to 17-
12 is supplied to the register bank selection control circuit 12 and the interrupt address branch code generation circuit 13, and performs the following control.

The register bank selection control circuit 12 outputs the interrupt selection signal 17
Using -1 to 17-12, the group to which the received interrupt request belongs is determined, the corresponding register bank designation code is selected from RB1 to RB3, and output to RB23. Here, since only the interrupt selection signal 17-2 is "1", the output of the OR circuit 30-1 is "1", the outputs of the OR circuits 30-2 and 30-3 are "0", and RB1 Is selected and stored in RB23.

The branch code generation circuit 13 generates a different code for each interrupt request in each group using the activated interrupt selection signals 17-1 to 17-12. here,
Interrupt selection signal 17-2 is "1", other request signals are "0"
, So that 31-2 of the OR circuits 31-1 to 31-4
Only "1" for others and "0" for others. The outputs of the OR circuits 31-1 to 31-4 are input to the encoder 34, converted into 2-bit binary data "10", and input to the branch code storage register 35 when the interrupt reception signal 41 becomes active. You.

Next, when the interrupt acceptance signal 41 is input, the CPU 20
2 will be described with reference to FIG. The bank designation code of the activated interrupt request is stored in the RB 23 by the register bank selection control circuit 12, and is switched to a predetermined register bank. The CPU 20 saves the contents of PC21 and PSW22 in the save area of the switched register bank. In addition, bits other than the lower two bits of the interrupt program start address PC1 preset in the switched register bank are set to corresponding bits of PC21, and the branch code storage register 35 generated by the branch code generation circuit 13 is set. The pc
Set to the lower 2 bits of 21. After that, an interrupt response signal 44 is transmitted to the INTC 10, the interrupt request flag is reset to “0”, and the interrupt processing is started from the address set in the PC 21. By resetting the interrupt request flag, another interrupt request signal can be received, and the interrupt selection signals 17-1 to 17-14 are made inactive to prepare for receiving the next interrupt request signal.

As described above, the program start address can be generated for each interrupt request based on the interrupt program start address set for each register bank corresponding to each interrupt group and the branch code. The processing can be branched and started for each interrupt request.

In this embodiment, the case where the number of interrupt requests is 12 and the number of register banks is 3 has been described. However, if the number of bits of the branch code storage register 35 is changed, the present invention can be easily applied to the case where the number of interrupt requests is large. Needless to say.

FIG. 3 is a schematic diagram for explaining a register bank portion in the second embodiment of the present invention. This embodiment has almost the same configuration as that of the first embodiment, and therefore different portions will be described here.

Interrupt selection signals 17-1 to 17-12 as in the first embodiment.
, A 2-bit value, for example, "10" is generated in the branch code storage register 35. Register bank 24a
, Interrupt processing program start addresses for the number of interrupts belonging to each interrupt group are set in advance.
The address output from the CPU 20 and the contents of the branch code storage register 35 are decoded by the address decoder 27, and a start address corresponding to the branch code storage register 35 is selected from the program start addresses and set in the PC. . For example, if the value of the branch code 35 storage register is "10", PC2 is selected and set as PC, and the interrupt processing program is started from address PC2.

As described above, by individually selecting the start address of the interrupt processing program for each interrupt request in each interrupt group, it is possible to start processing corresponding to each interrupt request.

〔The invention's effect〕

As described above, according to the present invention, a plurality of interrupt requests can be processed by the register bank switching method using a common register bank, so that interrupt requests that can be processed by the register bank switching method can be executed. The number is not limited to the number of register banks, and the system performance as a whole can be improved. Also, the number of register banks does not need to be increased in accordance with the increasing number of interrupt requests, and interrupt processing can be handled with the minimum necessary number of register banks. Utilization is planned.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data processing apparatus according to one embodiment of the present invention, FIG. 2 is a schematic diagram showing details of the register bank of FIG. 1, and FIG. 3 is a register bank in a second embodiment of the present invention. FIG. 4 is a block diagram of an example of a conventional data processing device, and FIG. 5 is a schematic diagram showing details of the register bank of FIG. 10: priority control circuit (INTC), 12, 112: register bank selection control circuit, 13: branch code generation circuit, 15-1 to-
12: Interrupt request flag, 16-1 to -3: Bank designation code, 17-1 to -12: Interrupt selection signal, 20, 120: Central processing execution unit (CPU), 21, 121: Program counter (PC), 2
2,122: Program status register (PSW), 23,123: Register bank designation register (RB), 24,124: Data memory, 25,125: Stack pointer, 26,27: Address decoder, 28,130: Program memory, 30-1 to 3, 31-1 ~
4 OR circuit, 32-1 to 3 ... register bank selection signal, 34
... Encoder, 35 ... Branch code storage register, 40-1
12,140-1 ... interrupt request signal, 41,141 interrupt acceptance signal, 44,143 interrupt response signal, 50 address bus,
51: data bus, 110: interrupt control unit.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/46

Claims (1)

(57) [Claims] A plurality of general-purpose register sets used by a central processing unit for processing are provided, and a plurality of general-purpose register sets are switched to a predetermined general-purpose register set among the general-purpose register sets in conjunction with an interrupt accepting signal corresponding to an interrupt request signal. In a data processing device for starting a program, a plurality of the interrupt request signals are grouped, and one general-purpose register set is assigned to each of the grouped groups; an interrupt request to be preferentially accepted and processed is detected. Means for generating an acceptance status signal for each interrupt request; means for generating a different branch code for each interrupt request in each of the groups as encoding of the acceptance status signal; Means for controlling the start address of the interrupt processing program. The data processing apparatus characterized by the write processing can be started branches for each of the interrupt requests of the same group.