JPH02128266A - Register with protective function - Google Patents

Abstract

PURPOSE:To protect memory data by preventing data write to a storage part when the memory data in a specific storage area in the storage part is coincident with the prescribed data. CONSTITUTION:A mode register (a register attached with a protective function) 10 can continuously write the data as long as a mode protect signal MDPR in an output terminal Q7 of a register 11 does not become '1,' namely, as long as data '1' is not written in a seventh bit. When the data '1' is written in the seventh bit, the data writing thereafter is prevented. Further, by initializing the data by an initializing signal INIT, the bit is restored to a data writable condition. Thus, the written data can be protected, and the safety of a system is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a register with a protection function suitable for use as a mode register or a data register in a controller or the like.

"Prior Art" When functions are added to a system such as a personal computer, various controllers (controllers for peripheral devices, etc.) constituting the system are improved accordingly. When a function is added to the controller, registers (mode register, data register) for realizing the new function are newly added to the controller.

Here, there is a case as shown in FIG. 5 as an example of register addition due to controller version upgrade. Fifth
Figure (a) shows an example of a register configuration in an old version controller.

This figure shows a register 1 used when the controller executes function A and a register 2 used when the controller executes function C. FIG. 5(b) shows an example of the register configuration in the new version of the controller.

In the register configuration shown in FIG. 5(b), a register B for a new function B is added to the register pool shown in FIG. 5(a). Also, some bits of register 2 were unused bits in the old version (indicated by "X" in Figure 5(a)), but in the new version, they have function C.
It is used as a bit to specify data K for specifying the operation of k. Here, when the data K is a certain value, the same function as the function C in the old version is executed. In this way, when functions are added to the controller, the definitions of some of the registers used in the old version may be changed or added.

In such a case, if a program created for an old version of the controller is executed on the new version of the controller, normal operation may not be obtained. For example, suppose that a certain program writes some data to the unused bits of register 2 (displayed as " Or all “1”s may be written). When this program is applied to an old version of the controller (register configuration shown in FIG. 5(a)), normal operation can be obtained because the contents of unused bits are ignored.

However, when applied to a new version of the controller (register configuration shown in Figure 5(b)), the data written to unused bits in the old version will be used as data, and the program will There is a possibility that the intended function C will not be executed.

Therefore, when developing a new version of the controller, by providing a mode register 4 (Fig. 5 (C)) and writing mode selection data to this register 4, the register configuration can be made compatible with the old version or the new version can be changed. I am trying to switch between versions. That is, when the old version application program is executed, the old version mode selection data is written to the specific bit V of the mode register 4 by the initialization program prior to execution. As a result, the controller controls data output to each register in accordance with the old version. For example, in the example of the register configuration shown in FIG. 5(b), the circuit configuration is switched to such that data to the bit labeled "K" in register 2 is ignored.

Also, writing to the added register B is switched to be ignored. Therefore, even when an old version application program is executed on a new version controller, normal operation can be obtained without unexpected operations being executed.

``Problems to be Solved by the Invention'' By the way, even when using the above-mentioned mode register to switch data input/output control for each register, the application program
If data is written to the mode register, normal operation will no longer be possible. For example, if the controller is
When the mode selection data for the new version is written to mode register 4 while the old version program is being executed, the register configuration changes to the fifth register configuration.
There is a possibility that the switching will occur as shown in Figure (b), and normal operation will not be obtained.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a register with a protection function that has a function of protecting written data.

``Means for Solving the Problems'' The present invention enables data to be written from the outside into a storage unit in synchronization with a write control signal, and by inputting an initialization signal, data can be stored in the storage unit. The register is capable of initializing data, and includes a write control means that prevents data from being written to the storage unit when stored data in a specific storage area in the storage unit matches predetermined data. It is characterized by the fact that it is equipped with

"Operation" According to the above configuration, unless predetermined data is written to a specific storage area of the register, data can be written to the register from the outside in synchronization with the write control signal. When predetermined data is written to a specific area of the register, writing of data to the register is blocked even if a write control signal is input, and the data stored in the register is protected. and,
When the initialization signal is input to the register and the storage area is initialized, the write inhibited state is released and data can be written to the register again.

"Embodiment" Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a mode register 10 with a protection function according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a controller incorporating this mode register IO, and FIG. FIG. 2 is a block diagram of a system configured using the controller shown in the figure.

The system shown in Figure 3 consists of a CPU (CPU) that controls the entire system.
central processing unit) RO where the 211 control program is stored
M (read-only memory) 22, RAM (random access memory) 23 used for temporary storage of data, and controllers C0NT1-CONTN are connected to the common bus C.
It is connected via B.

Controller C0NT 1 to C0 in this system
As shown in FIG. 2, the NTN usually has a built-in mode register IO for instructing some execution mode. Here, data on the common bus CB is input to the mode register IO via the buffer 14 and the internal bus rB. When the CPU 21 of the system of FIG. 3 writes mode data to the mode register 10 (FIG. 2), the CPU 2t outputs an address signal l1O-ADR specifying the mode register IO to the common bus CB. Then, the decoder 13 decodes this address signal I10-ADH and outputs a decoded signal specifying the mode register IO. As a result, data is written to the mode register IO. Then, from now on, this controller C0
In the NTi, data input/output control for the other register 5 is performed in accordance with the data stored in the mode register 10.

Next, the configuration of mode register (2)0 will be explained.

As shown in FIG. 1, the mode register 10 consists of a register 11 with an initialization function and an OR gate 12. The register 11 has a 5-bit storage area, and a data input end corresponding to each of these storage areas. ~ D8, D, data DTO-DT via common bus CB (Fig. 2, Fig. 3)
3, DT7 is input, and the initialization signal INIT is input to the initialization signal input terminal CL. Here, data DTO~
DT3 is used as mode selection data, and data DT7
is input to the register 11 as write control data.

Also, the output terminal Q in the register 11. The output signals of ~Q are sent to each part of the controller as mode selection data MODE, and the output signal of output terminal Q7 is used as a mode protect signal MDPR. The OR gate I2 has a decoder! at one input end. One of the output terminals of the register 11 is connected to the register 11, and the output terminal Q of the register 11 is connected to the other input terminal. And the output terminal of OR gate I2 is the register l
It is connected to the clock input terminal GK of 1.

The decoder 13 receives an address signal l1O-ADR1 write request signal ■10-wrt via the common bus CB.
An enable signal C8 is also input. Then, when the mode register IO is specified by the address signal IO-ADH, the decode signal MDW is sent from the decoder ①3.
R is output and this is input to the OR gate 12.

The operation of the mode register IO will be explained below using the time chart shown in FIG.

First, assume that at times t and a, the decode signal MDWR is output, and the mode selection data DTO-DT3 corresponding to mode N and the write control data DT7 (“0” in this case) are input. .

At this time, register! Since the mode protect signal MDPR output from the output terminal Q7 of 1 is "0",
Signal MDWR is input to register 11 via OR gate 12 as mode write signal MDST. Then, the rising point of the mode write signal MDST (time t, b)
Then, data DTO to DT3 and DT7 are written to register II. and the output terminal Q of register II. -Q3 outputs a mode selection signal MODE specifying mode N, and the controller performs input/output control to each register corresponding to this mode N.

Next, at times t and a, a decode signal MDWR is output, and data specifying mode F is output.
DT3 and write control data DT7 (in this case “
1") is input. In this case as well, the mote write signal MDST is output from the OR gate and input to the register 11. Then, at the rising edge of the mode occupying signal MDST (time t2b), the data DTO- DT3, DT
7 is written to register 11. And register 1
1 output end Q. A mode setting signal MODE specifying mode F is output from ~Q3. At the same time register 11
The mode protect signal MDPR at the output terminal Q, 7 of
stands up.

Next, assume that the decode signal M D WR is input at time t3. In this case, the output terminal Q of register 11
7, the mote protect signal M D P f (is “
1”, the output of the OR gate 12 is always “1”.
1'', and the mode write signal MDST is not output.

Therefore, data writing to the register 11 is blocked, and the mode of the controller remains F.

Next, when the initialization signal [NIT is input at time 4, the register 11 is initialized and the mote protect signal MDPR falls. As a result, data writing to the register 11 (eg, data writing at time t5 in FIG. 4) becomes possible.

In this manner, data can be continuously written to this mode register IO unless data "1" is written to the seventh bit. Also, data “1” is placed in the 7th bit.
If " is written, subsequent data writing is inhibited. Then, by initializing with the initialization signal INIT, the state returns to a state in which data can be written.

If such a mode register 10 is applied as a component of a controller, it becomes possible to protect the mode as necessary. For example, when an application program is being executed in the Nostem shown in FIG. Accidents such as destruction of the contents of the mode register of the controller can be prevented.

In the embodiments described below, the present invention is applied to a mode register, but it can also be applied to protection of data registers other than mode registers. For example, when a program writes to the register continuously, the write control bit is set to "0" and the data is written, and there is no plan to write data after that, and rather , when it is a problem if the data stored in the register changes, it can be used to write by setting the write control pit to "I".

``Effects of the Invention'' As explained in 2 below, according to the present invention, it is possible to write data from the outside to the storage unit in synchronization with the write control signal, and it is possible to input the initialization signal. For a register that can initialize data stored in the storage unit by , when data stored in a specific storage area in the storage unit matches predetermined data, preventing data from being written to the storage unit. Since the write control means is provided, the data stored in the register can be protected, and the safety of the system is improved.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a register with a protection function according to an embodiment of the present invention, Fig. 2 is a block diagram showing the configuration of a controller to which the embodiment is applied, and Fig. 3 is a system configured with the controller of Fig. 2. FIG. 4 is a time chart showing the operation of the register with protection function shown in FIG. 1, and FIG. 5 is a diagram showing an example where a new register is added to the controller due to version upgrade. 10...Mode register (register with protection function),
11...Register with initialization function! 2...
・OR gate.

Claims (1)

[Claims] It is possible to write data into the storage section from the outside in synchronization with a write control signal, and it is possible to initialize the stored data in the storage section by inputting an initialization signal. The register is characterized in that it is equipped with a write control means that prevents data from being written to the storage unit when stored data in a specific storage area in the storage unit matches predetermined data. Register with protection function.