JPH0239817B2 - WARIKOMISEIGYOHOSHIKI - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a multiprocessor system equipped with an interprocessor communication bus, when interrupts are pending for multiple processors at the same time and the interrupts are harvested by any one processor. In addition, by using the communication function of the inter-processor communication bus for all processors, the interrupt pending state is released, making it possible to reduce the number of signal lines related to common interrupts and simplify the related control circuits. There is.

[Industrial application field]

The present invention relates to an interrupt control method, particularly to a service processor (SVP) in a multiprocessor system.
The present invention relates to an interrupt control method such as an interrupt that simplifies interrupt-related circuits by using existing inter-processor communication circuits.

[Conventional technology]

FIG. 4 is a diagram for explaining the conventional method.

In the figure, 10, 10-1, 10-2, and 10-3 are processors that execute predetermined instructions and process data, 11 is a service processor (SVP), 12 is a system control interface (SCI),
40 represents an interrupt pending bit, and 41 represents a selection section.

The service processor 11 monitors the system,
This is a processing device that performs operations and controls all at once. In response to an interrupt request from the service processor 11,
The pending bit 40 of the SCI 12 is turned on, and the selection unit 41 looks at the interrupt masks of each processor 10, 10-1, etc., selects the interrupt destination processor, and raises the interrupt only to that processor. There is. Further, a reserved bit (not shown) provided for each processor is turned on by another signal.

In this way, conventionally, a plurality of processors 10, 1
For 0-1,..., if an interrupt is generated in only one processor and that processor executes the interrupt processing, there is only one system.
In the SCI12 or main memory controller (MCU) part,
It is designed to perform control to determine the interrupt destination processor.

[Problem that the invention seeks to solve]

According to the above conventional method, SCI12 (or
Signal lines for mask setting, interrupt acceptance, etc. are required between the interrupt control unit of the MCU (hereinafter the same) and each processor 10, 10-1, . . . , and there is a problem in that the number of signal lines increases. Also, SCI1
2 and the processors 10, 10-1, . . . , the number of interrupt-related control circuits also increases.

[Means for solving problems]

FIG. 1 shows a basic configuration diagram of the present invention.

In FIG. 1, numerals 10 to 12 correspond to those shown in FIG. 13 is a selection control circuit;
4 is a transmission control circuit, 15 is an order, 16 is a flag, 17 is an interrupt reception unit, 18 is an interrupt processing unit,
Reference numeral 19 represents a reception control circuit, 20 a pending bit indicating that interrupt processing is pending, and 21 an interprocessor communication bus.

The inter-processor communication bus 21 is a common bus conventionally used for inter-processor communication commands (signal processor commands). As is well known, inter-processor communication commands include, for example, CPU start,
Orders, which are 8-bit subcommand codes such as CPU stop, external call, and emergency, can be sent to other processors. The selection control circuit 13 is a circuit that performs control to select a communication destination processor in response to an order transmission request notified via the inter-processor communication bus 21.
The transmission control circuit 14 sends the selected processor
This circuit sends orders via the interprocessor communication bus 21.

In the present invention, when there is an interrupt request from the service processor 11, all processors 10, 10
-1, . . . , the pending bit 20 corresponding to the interrupt level is turned on and an interrupt is generated.
The interrupt accepting unit 17 is the processor that first accepts an interrupt, and when the own processor executes the actual processing in response to the interrupt request, the interrupt accepting unit 17 performs a Using the communication function,
Reset order 1 to release pending bit 20
5 and a flag 16 indicating which bits to reset.

In a processor whose reserved bit 20 has been turned off by another processor, the service processor 11
Normal processing continues as if there was no interrupt request from.

[Effect]

The present invention uses an inter-processor communication bus 21, and the processor that accepts the interrupt first sends a reset order 15 and a flag 16 indicating which pending bit in the processor is to be reset to all processors. In the processor,
Resets the interrupt pending bit. As interfaces related to this reset, an interprocessor communication bus 21, a selection control circuit 13, a transmission control circuit 14, etc., which are conventionally provided for communication between processors, are used. Therefore, there is no need to separately provide a dedicated interrupt signal line, etc., and the signal line and circuit can be simplified.

〔Example〕

FIG. 2 is a block diagram of an embodiment of a portion related to the present invention in a processor, and FIG. 3 is a block diagram of an embodiment of a portion related to the present invention in an SCI. 2 and 3, the same reference numerals as in FIG. 1 correspond to those shown in FIG.

In FIG. 2, the microinstruction control unit 22 is
This circuit executes and controls processing similar to microinstructions that process well-known interprocessor communication instructions. Control information from the microinstruction control unit 22 is sent to the control circuit 25 via the decoder 23, and transmission control regarding the order 15, flag 16, address 24, etc. is performed. That is, in a write cycle during instruction execution, write data
DATA is order 15, flag 16,
It is set in a register at an address 24 indicating the processor to be communicated with, and is sent to the SCI via a selection circuit 26 controlled by a control circuit 25. Data transmission to the SCI is performed using the interprocessor communication bus 21 in the same manner as for interprocessor communication commands.

The reset order and flag notified from the SCI via the interprocessor path bus 21 are cleared by the reception control circuit 19 and cause the corresponding bits of the reserved bits 20 to be reset.

As shown in FIG. 3, in the SCI, control similar to the conventional processing of interprocessor communication commands is performed. 30 is CPU0 corresponding to processor 10
The receiving section 30-1 is a receiving section for the CPU 1 corresponding to the processor 10-1. Receiving sections are similarly provided for other processors.

For example, when reset orders, flags, and addresses are sent from processor 10 (CPU0) in a time-sharing manner, these are
4. The information is latched in the register at address 35 and sent to the selection circuit 37. Based on the control signal from the reception control circuit 32, the selection control circuit 36 performs waste priority control between the reception sections corresponding to each processor, and performs gate control of the selection circuits 37, 37-1, . The transmission control circuit 14 includes the selection circuit 3
Send data from 7, 37-1, ... to register 3
8, and sends the reset order, etc. to each processor. In particular, in the case of the present invention, reset orders and the like are sent to all processors including the own processor.

Next, the control operation when an interrupt occurs will be explained.

When there is an interrupt request from the service processor 11, the interrupt is raised for all processors 10, 10-1, . . . and the pending bit 20 in each processor is turned on. It should be noted that a plurality of bits are prepared for the pending bit 20 in correspondence with the interrupt level, etc., but this point can be considered to be the same as the conventional one.

Each processor that enters the interrupt first checks its own pending bit 20. Pending bit 20
If OFF, it means that another processor has already issued a reset order, so no reset order is issued.

If the pending bit is on, a lock flag (not shown) provided, for example, in the interprocessor communication area (HSA) of the memory is checked. This lock flag is for exclusive contention control between processors, and if this flag is on, it means that another processor is already in the process of issuing a reset order, so it is not possible to issue a reset order. The reserved bits of the own processor are turned off without any processing.

If the pending bit is on and the lock flag in the HSA is off, a reset order is issued by turning on the lock flag and activating a microinstruction similar to an interprocessor communication instruction. Then, by the reset order issued by itself, the pending bit of its own processor is turned off. When the pending bit turns off, the lock flag in the HSA is turned off and processing for the interrupt request from the actual service processor 11 is executed. It goes without saying that only the processor that issued the reset order executes the processing for this interrupt request.

〔Effect of the invention〕

As explained above, according to the present invention, processing such as service processor interrupts is performed using the existing inter-processor communication function, so the number of signal lines related to interrupts can be reduced, and the number of signal lines related to interrupt control can be reduced. It becomes possible to simplify the circuit.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a block diagram of an embodiment of a portion related to the present invention in a processor, FIG. 3 is a block diagram of an embodiment of a portion related to the present invention in SCI, and FIG. FIG. 4 shows a diagram for explaining the conventional method. In the figure, 10 is a processor, 11 is a service processor, 12 is a system control interface (SCI), 13 is a selection control circuit, 14 is a transmission control circuit, 17 is an interrupt reception unit, and 20 is a pending bit.

Claims (1)

[Claims] 1. A system includes a plurality of processors 10, 10-
an inter-processor communication bus 2, which is composed of 1,... and used by communication instructions between the processors;
1, an information processing apparatus comprising: means 20 for storing an interrupt pending state in all the processors for an interrupt request to be processed by any one of the processors 10, 10-1, . . .; and the storage means. 20, and the processor that entered the interrupt first sends the inter-processor communication bus 2 to all processors.
1. An interrupt control method comprising: means 17 for issuing a reset order for releasing the interrupt pending state using the interrupt pending state.