JPH0619867A - Memory check system - Google Patents

Abstract

PURPOSE:To shorten memory check time at a multiprocessor system. CONSTITUTION:When a system is started, CPU 11 and CPU 12 check local memories 14 and 15 which they themselves have, refer to an allocation table in ROM 18 and recognize banks which they themselves share among a common memory 16. Thus, CPU 11 checks a bank 16-1, and CPU 12 banks 16-2 and 16-3. In such a case, the respective banks are in the same size and CPU 12 has processing speed twice as much as that of CPU 11. Thus, time which both CPU require for checking the memories becomes equal, and starting processing time as the whole system is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system having a plurality of central processing units and a memory, and more particularly to a memory check system at system startup.

[0002]

2. Description of the Related Art In recent years, a plurality of central processing units (hereinafter referred to as CP
A so-called multiprocessor system equipped with a U) is adopted. In this multiprocessor system, each CPU has its own local memory or a common memory connected to a common bus. Then, each CPU can perform the processing assigned to each CPU in parallel.

In such a system, each CPU checks its own memory when the system is started up or when it is restarted at the time of recovery after a failure occurs. That is,
Each CPU did not perform the process of checking the memory in cooperation with each other.

[0004]

By the way, in such a multiprocessor system, each memory provided has a large capacity, and a lot of time is required for the memory check at the time of system startup. The time required for this memory check occupies most of the system startup processing time, and the lengthening of the system becomes a problem.

However, as described above, in the conventional system, each CPU only checks its own memory. Therefore, for example, when a certain CPU has a very large memory capacity, However, if the speed of the CPU for checking this is slower than the other cases, the time required for checking the memory becomes long, and the startup processing time of the entire system also becomes long.

The present invention has been made to solve the above problems, and a plurality of CPUs cooperate with each other to check the memories held by each CPU in a well-balanced manner, thereby shortening the memory check time of the entire system. The purpose is to obtain a memory check method that can be performed.

[0007]

According to a first aspect of the present invention, there is provided a memory check system in a multiprocessor system having a plurality of central processing units and one or a plurality of memories for storing necessary data. An allocation table in which the one or more memories are divided into a plurality of areas as a whole and each divided area is allocated to each central processing unit is provided, and each central processing unit has a divided area allocated according to the allocation table. The memory check is performed.

A memory check system according to a second aspect of the present invention is characterized in that, in the first aspect, the allocation table is configured to allocate each divided area of the memory according to the processing capacity of each central processing unit. To do.

According to a third aspect of the present invention, there is provided a memory check method, a plurality of central processing units, a local memory provided for each central processing unit, and each of the local memories and the central processing units. In a multiprocessor system having a local bus connecting each of the above and a data transfer control circuit connecting each of these local buses, (i) a part of the local memory is divided into a plurality of areas, and each divided area is divided into a plurality of areas. An allocation table allocated to each central processing unit is provided, and (ii) the central processing unit that holds the local memory that is the target of the division performs a memory check on the divided area indicated by the allocation table of the local memory, (iii) The central processing unit that holds the local memory that was not the target of the division controls the data transfer control circuit. It is characterized in that data transfer is performed between the own local memory and the divided area indicated by the allocation table among the divided local memories, and the memory check of the divided area is performed. is there.

[0010]

In the memory check method according to the first aspect of the present invention, the memory provided in the multiprocessor system is checked by the plurality of central processing units according to the contents of the preset allocation table.

In the memory check system according to the second aspect of the present invention, the memory check in the system is performed according to the processing capacity of each central processing unit.

In the memory check method according to the third aspect of the present invention, a partial area of the local memory owned by a certain central processing unit is directly checked by the central processing unit, but the remaining area is subjected to the data transfer control circuit. The check is performed by the other central processing unit using the data transfer by.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows a multiprocessor system to which the memory check method according to the first embodiment of the present invention is applied. This system includes a CPU 11 and a CPU 12, which are connected to each other by a common bus 17. The CPU 11 has a local memory 14, and the CPU 12 has a local memory 15. The common memory 16 and the ROM 18 are connected to the common bus 17. CPU11 is 6MB / S, CPU12 is 12
Has a processing speed of MB / S, and has a local memory 1
4, 15 and the common memory 16 have access speeds that can follow the processing speeds of these CPUs. Here, it is assumed that the capacity of the local memory 14 is 1 MB and the capacity of the local memory 15 is 2 MB. The capacity of the common memory 16 is 3 MB.

FIG. 2 shows a bank allocation table stored in the ROM 18 shown in FIG. This table shows the CPU 11 and the CPU in the system of FIG.
Banks of the common memory 16 are assigned corresponding to 12 respectively. According to this allocation, the CPU 11 is allocated to the bank 16-1 of the common memory 16 and the CP
U12 is assigned to banks 16-2 and 16-3. Here, it is assumed that the capacity of each bank is 1 MB.

The memory check operation in the multiprocessor system having the above configuration will be described with reference to FIG.

When the system is powered on, the CP
Each of U11 and U12 performs a predetermined initial hard check (steps S101 and S201 in FIG. 3) to check the connected hardware circuit, for example, the state of the input / output circuit and the bus. Next, the CPU 11 checks its own local memory 14 (step S10).
2), the CPU 12 checks the local memory 15 (step S202). Specifically, the memory check is performed by, for example, writing prepared check data in a memory, reading the data, and comparing the read data with the original data.

After the CPUs 11 and 12 finish checking their own local memories, the ROs
The check allocation information of the common memory is read by accessing M18 and referring to the allocation table (step S10).
3, S203), based on this allocation information, the common memory 16
Check the bank 16-1 (step S10).
4). On the other hand, the CPU 12, based on the read allocation information,
The banks 16-2 and 16-3 of the common memory 16 are checked (steps S204, S205).

FIG. 4 shows a summary of the memory check distribution as described above. As shown in this figure, the CPU 11
Is a bank 16 of the local memory 14 and the common memory 16.
While checking -1, the CPU 12 checks the banks 16-2 and 16-3 of the local memory 15 and the common memory 16. In this case, the processing speed of the CPU 11 is 6 MB / S as described above.
The memory size checked by 11 is 2 MB in total.
On the other hand, the processing speed of the CPU 12 is 12 MB / S, and the check target memory size is 4 MB in total. Therefore, the memory check time by the CPU 11 and the CPU 12
The memory check time due to the above is almost the same, and there is no situation where any CPU waits for the other CPUs to finish the memory check. That is, as a whole system,
The memory can be checked in the shortest time with the best balance.

FIG. 5 shows a multiprocessor system to which the memory check method according to the second embodiment of the present invention is applied. In this system, CPU
21 is a local memory 23 via a local bus 29.
And ROM 26. On the other hand, the CPU 22
Local memory 24 and RO via local bus 30
It is connected to M28. The local bus 29 and the local bus 30 are connected to each other via the DMA circuit 27. Here, the processing speeds of the CPU 21 and the CPU 22 are both 6 MB / S, and the local memory 2
The size of 3 is 1MB, the size of the local memory 24 is 5
MB.

FIG. 6 shows ROMs 26 and 28 in FIG.
3 shows a bank allocation table stored in.
As shown in this figure, the CPU 21 has a local memory 2
4 banks 24-5 are assigned, and the CPU 22 is assigned banks 24-1 to 24-4. Each of these banks has a size of 1 MB. The memory check processing of the multiprocessor system having the above configuration will be described with reference to FIG.

When the power of this system is turned on, the CPU
21 and the CPU 22 both perform an initial hard check (steps S301 and S401 in FIG. 7), and then check a data transfer path (steps S302 and S40).
2).

Next, the CPU 21 refers to the bank allocation table in the ROM 26 and reads the check allocation information (step S303). Then, the CPU 21 checks its own local memory 23 (step S304), and then checks the bank 24-5 of the local memory 24 based on the read check allocation information (step S305). On the other hand, the CPU 22 is a ROM
The check allocation information in the local memory 24 is read by referring to the bank allocation table stored in 28 (step S403). Then, the CPU 22 determines the banks 24-1 to 24-1 of the local memory 24 based on the read allocation information.
The banks 24-4 are sequentially checked (step S40
4-S407).

Since the local memory 24 is a memory held by the CPU 22, its check is performed by the local bus 3
Directly via the CPU 22 via 0. Therefore, the processing speed in this case is 6 MB / S.

On the other hand, the local memory 2 by the CPU 21
The memory check of the bank 24-5 of No. 4 is performed by the DMA circuit 2
It is performed through 7. In this case, the processing speed of the CPU 21 itself is 6 MB / S, which is the same as the processing speed of the CPU 22, but the data transfer speed of the DMA circuit is 2 MB / S.
Memory check will be performed at 2 MB / S.

The memory check through the DMA circuit 27 in this case is performed according to the flow shown in FIG. That is, the CPU 21 first writes the check data in a predetermined area of the local memory 23 held by the CPU 21 (step S501 in FIG. 9), and the local memory 23
Under the control of the DMA circuit 27, the check data written in the above is transferred to and written in a predetermined area of the bank 24-5 of the local memory 24 (step S502). Here, specifically, the CPU 21 sets the memory address of the data transfer source and the memory address of the data transfer destination in the address register (not shown) of the DMA circuit 27, and also sets the data size to be transferred to the size register (see FIG. (Not shown) to give a DMA start command. Thereby, the DMA circuit 27 transfers the data of the designated size of the designated address of the local memory 23 to the designated address of the bank 24-1 of the local memory 24.

Next, the CPU 21 performs the D in the same manner as above.
Under the control of the MA circuit 27, the check data written in the bank 24-5 of the local memory 24 is written in an area different from the above area of the local memory 23 (step S503). Then, the CPU 21 compares the check data first written in the local memory 23 with the data written by DMA transfer from the local memory 24 later, and performs a memory check (step S504).
Then, until the check is completed for all the areas of the bank 24-5 of the local memory 24 (step S5
05; Y), the above steps S501 to S504
The process of is repeated.

Memory check targets of the CPU 21 and the CPU 22 are organized as shown in FIG. As shown in this figure, the CPU 21 has its own local memory 23 and CP.
The bank 24-5 of the local memory 24 of U22 is checked, and the CPU 22 checks the banks 24-1 to 24-4 of its own local memory 24. In this case, the checking speed of the local memory 23 by the CPU 21 is 6 MB / S, but the checking speed of the bank 24-5 of the local memory 24 by the CPU 21 is 2 MB.
/ S. On the other hand, the local memory 24 by the CPU 22
Check speed of banks 24-1 to 24-4 is 6
MB / S. Therefore, the memory check time of both as a whole becomes the same, and the check processing is ended almost at the same time. Therefore, one CPU does not wait for the completion of the memory check of the other CPU, and it is possible for the entire system to perform the most balanced and efficient memory check in the shortest time.

In each of the above first and second embodiments, the case of two CPUs has been described, but a similar bank allocation table is provided in a multiprocessor system having three or more CPUs. This makes it possible to balance the processing time of the memory check and perform this in the shortest time. Also in the above embodiment, it is assumed that storing the bank allocation table in ROM, not limited to this, for example, E ²
A non-volatile memory such as PROM may be used. Furthermore, it is possible to use a DIP switch as a storage means for storing the bank allocation table. Then, when the system is upgraded, for example, by adding a new memory or CPU to the system, by changing the allocation contents of the bank allocation table at the time of the configuration, such a system upgrade can be achieved. Can respond flexibly.

In each of the above two embodiments, the case where each CPU also has a local memory has been described, but it is needless to say that the present invention can be applied to the case where each CPU has only a common memory.

[0031]

As described above, according to the invention of claim 1, in the multiprocessor system, the plurality of central processing units perform the memory check according to the allocation preset in the allocation table. The memory check at the time of system startup is shared and shared among the central processing units. Therefore, by optimally setting the allocation table, the memory check can be performed in a well-balanced manner as a whole, and the memory check time can be shortened. Further, by appropriately changing the allocation table, there is an effect that it is possible to flexibly deal with system expansion / change and the like, and to optimize the system.

According to the second aspect of the present invention, since the memory check is performed according to the processing capacity of each central processing unit, the memory check can be performed in a well-balanced manner as a whole system. It is possible to eliminate the inconvenience that the entire system startup processing time is lengthened due to the lengthened memory check by the two central processing units.

According to the third aspect of the present invention, the central processing unit directly checks a partial area of the local memory held by a certain central processing unit, while the remaining area is subjected to data transfer by the data transfer control circuit. Since it was decided to check by other central processing units by using, even if each central processing unit is not connected by a common bus and has an independent bus configuration, each central processing unit There is an effect that the memory check can be shared among the processing devices.

[Brief description of drawings]

FIG. 1 is a block diagram showing a multiprocessor system to which a memory check method according to a first embodiment of the present invention is applied.

FIG. 2 is an explanatory diagram showing a bank allocation table used in this memory check method.

FIG. 3 is a flowchart showing the processing contents of this memory check method.

FIG. 4 is an explanatory diagram summarizing the memory check targets for each CPU in this memory check method.

FIG. 5 is a block diagram showing a multiprocessor system to which a memory check method according to a second embodiment of the present invention is applied.

FIG. 6 is an explanatory diagram showing a bank allocation table used in this memory check method.

FIG. 7 is a flowchart showing the processing contents of this memory check method.

FIG. 8 is an explanatory diagram summarizing the memory check target for each CPU in this memory check method.

9 is a flowchart showing in detail the processing contents of step S305 of FIG. 7. FIG.

[Explanation of symbols]

 11, 12, 21, 22 CPU 14, 15, 23, 24 Local memory 16 Common memory 18, 26, 28 ROM 27 DMA circuit

Claims (3)

[Claims] 1. A multiprocessor system having a plurality of central processing units and one or a plurality of memories for storing necessary data, wherein each of the one or a plurality of memories is divided into a plurality of areas as a whole. A memory check method comprising providing an allocation table in which a divided area is allocated to each of the central processing units, and each of the central processing units performs a memory check of the divided area allocated to each, according to the allocation table. 2. The memory check method according to claim 1, wherein the allocation table is one in which each divided area of the memory is allocated according to the processing capacity of each of the central processing units. 3. A plurality of central processing units, a local memory provided and held for each central processing unit, a local bus connecting each of these local memories and each of the central processing units, and each of these. In a multiprocessor system having a data transfer control circuit connecting between local buses, an allocation table is provided in which a part of the local memory is divided into a plurality of areas and each divided area is allocated to each central processing unit. The central processing unit that holds the local memory that is the target of the memory check the divided area indicated by the allocation table in the local memory, and the central processing unit that holds the local memory that is not the target of the division is , Controlling the data transfer control circuit so that the local memory owned by the self and the divided memory A memory check method characterized in that data is transferred to and from a divided area of the cull memory indicated by the allocation table, and the memory check of the divided area is performed.