JPH06259369A - Information processor - Google Patents

Abstract

PURPOSE:To reduce an economical load accompanying a change in device ID by reading an ID out of an ID storage part together according to an ID read instruction from a CPU provided to a control part. CONSTITUTION:An ID1 and an ID2 are read out when the processor is actuated. At this time, the CPU 2 outputs addresses assigned to an ID1 port 16 and an ID2 port 17 and an I/O read signal to a bus line (a). Consequently, a decoder 15 outputs an IDRD signal (g) and the ID1 is outputted from the IDI port 16. Further, the ID2 is outputted from the ID2 port 17 at the same time. Those ID1 and ID2 are outputted as a data signal (e) to the bus line (a). Consequently, the CPU 2 can read out the IDI of the side of a control board 11 and the ID2 of the side of an extended board 12. The CPU 2 recognizes memory capacity, the number of connected I/Os, and the number of extension slots on the basis of both the read ID1 and ID2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an expandable information processing apparatus, and more particularly to an ID recognition system for the apparatus.

[0002]

2. Description of the Related Art First, a conventional apparatus ID recognition method will be described with reference to FIGS. FIG. 4 is a block diagram showing the configuration of the conventional apparatus, and FIG. 5 is a block diagram showing the internal configuration of the ID storage unit 7 of FIG.

As shown in FIG. 4, a CPU 2 is provided in the device 1.
Is provided, and the device 1 is controlled by the CPU 2. A memory 3 stores an operation program of the CPU 2 and various data, and is connected to the CPU 2 via a bus line a. In the bus line a, I /
O device 4, 5, device expansion slot 6 and ID
The storage unit 7 is connected. The expansion slot 6 is provided on a control board (not shown), and the expansion board is inserted into the expansion slot 6 so that the function of the apparatus is expanded. An ID storage unit 7 is also provided on this control board.

As shown in FIG. 5, the ID storage unit 7 includes a decoder 8 and an ID port 9. The decoder 8 receives the address signal b of the bus line a and the I / O read signal (IOR
D) c is input, and the IDRD signal d is output when a predetermined address is input together with the I / O read signal c. This IDRD signal d is output to the ID port 9, and thus the ID of this device is output from the ID port 9. This I
D is output as a data signal e on the bus line a, so that the CPU 2 can read the ID of this device.

The device ID is read, for example, when the device is activated. At that time, the CPU 2 outputs the address assigned to the ID port 9 and the I / O read signal onto the bus line a. This allows the decoder 8 to send the IDR
The D signal d is output, and the ID of this device is output from the ID port 9. This ID is output as a data signal e on the bus line a, and the CPU 2 can read the ID of this device. Then, based on the read ID, for example, the memory capacity of this device, the number of I / Os connected, and the number of expansion slots are recognized.

[0006]

However, with the above structure, the control board has an expansion slot and an ID.
Since the storage unit is mounted, the control board must be recreated each time the number of expansion slots is changed, and the ID storage unit must be changed each time, which is not economical.

The present invention solves the above problems and provides an apparatus I
An object of the present invention is to provide an information processing device in which the economical burden associated with the change of D is reduced as much as possible.

[0008]

In order to solve the above-mentioned problems, the present invention divides a control unit for controlling the entire apparatus and an expansion unit, and the control unit stores an ID of the control unit. An ID storage unit for storing the ID of the expansion unit is provided in the storage unit and the expansion unit, and the IDs of these ID storage units are read together according to an ID reading command from the CPU provided in the control unit. Is.

[0009]

According to the present invention, since the ID storage section is provided separately for the control section and the extension section, when the extension section is changed, the I of the extension section is changed.
Since it is only necessary to change the D storage unit, it is possible to reduce the economical burden of changing the device ID.

[0010]

1 is a block diagram showing the configuration of an apparatus according to the present invention, and FIG. 2 is a block diagram showing the internal configuration of the ID1 storage unit 13 and the ID2 storage unit 14 of FIG. is there. FIG. 3 relates to the modified example of FIG. 2, and the ID is the same as in FIG.
1 is a block diagram showing the internal configuration of a first storage unit 13 and an ID2 storage unit 14. FIG.

As shown in FIG. 1, the apparatus 10 is provided with a control board 11 and an extension board 12, and the control board 11 and the extension board 12 have connection means f (connector, cable, board et).
c. ) Are connected by. 2 is a CPU, 3 is a memory, 4 and 5 are I / O devices, 6 is an expansion slot 6, a
Are bus lines, which have already been described in the description of the prior art.

Reference numeral 13 is an ID for storing the ID 1 on the control board 11 side (for example, memory capacity or the number of connected I / Os).
1 storage unit, 14 is an ID 2 (for example,
The ID2 storage unit stores the number of expansion slots).

The ID1 storage unit 13, as shown in FIG.
It has a decoder 15 and an ID1 port 16. ID2
The storage unit 14 has an ID2 port 17. The decoder 15 inputs the address signal b of the bus line a and the I / O read signal (IORD) c, and outputs the IDRD signal g when a predetermined address is input together with the I / O read signal c. The IDRD signal g is output to the ID1 port 16 and the ID2 port 17, whereby the ID1 port 16 outputs ID1 and the ID2 port 17 outputs ID2. The ID1 and ID2 are output on the bus line a as a data signal e. For example, I
6 bits are allocated to output D1, 2 bits are allocated to output ID2, and the data signal e of 8 bits as a whole is output on the bus line a. As a result, the CPU 2 can read the ID 1 on the control board 11 side and the ID 2 on the expansion board 12 side.

ID1 and ID2 are read, for example, when the device is activated. At that time, CPU2 is ID1
The address assigned to the port 16 and the ID2 port 17 and the I / O read signal are output onto the bus line a. As a result, the decoder 15 outputs the IDRD signal g and the ID1 port 16 outputs ID1. At the same time, ID2 is output from the ID2 port 17.
The ID1 and ID2 are output on the bus line a as a data signal e. As a result, the CPU 2 can read the ID 1 on the control board 11 side and the ID 2 on the expansion board 12 side. Then, the CPU 2 reads the read I
Based on both D1 and ID2, for example, the memory capacity of this device, the number of I / Os connected, and the number of expansion slots are recognized.

Next, another example of the ID storage unit will be described with reference to FIG. The ID1 storage unit 13 includes a decoder 15 and an ID1 port 16 as shown in FIG. The ID2 storage unit 14 includes a decoder 18 and an ID2 port 17. The decoder 15 inputs the address signal b of the bus line a and the I / O read signal (IORD) c, and when a predetermined address is input together with the I / O read signal c, ID
The RD signal h is output. The IDRD signal h is output to the ID1 port 16, and thus the ID1 port 16 outputs ID1.

The decoder 18 inputs the address signal b of the bus line a and the I / O read signal (IORD) c, and outputs I
The IDRD signal i is output when a predetermined address is input together with the / O read signal c. This IDRD signal i is I
Output to D2 port 17, which causes ID2 port 1
7 outputs ID2.

The ID1 and ID2 are output as a data signal e on the bus line a. For example, 6 bits are assigned to output ID1, 2 bits are assigned to output ID2, and the data signal e of 8 bits as a whole is output on the bus line a. This gives C
PU2 is ID1 on the control board 11 side and expansion board 1
The ID2 on the second side can be read.

ID1 and ID2 are read, for example, when the device is activated. At that time, CPU2 is ID1
The address assigned to the port 16 and the ID2 port 17 and the I / O read signal are output onto the bus line a. As a result, the decoder 15 outputs the IDRD signal h and the ID1 port 16 outputs ID1. At the same time, the decoder 18 outputs the IDRD signal i and the ID2 port 17 outputs ID2. This I
D1 and ID2 are output on the bus line a as a data signal e. As a result, the CPU 2 can read the ID 1 on the control board 11 side and the ID 2 on the expansion board 12 side. Then, the CPU 2 recognizes, for example, the memory capacity of the device, the number of I / Os connected, and the number of expansion slots based on both the read ID1 and ID2.

The two configurations of the ID storage unit have been described above. In the case of the configuration shown in FIG. 2, the control board 11 outputs the IDRD signal g to the extension board 12.
Therefore, a special signal line for outputting the IDRD signal g to the connecting means f is required. However, the number of decoders can be reduced as compared with FIG. On the other hand, in the case of the configuration shown in FIG. 3, the number of decoders increases. However, no special signal line is required for the connecting means f. Which one to choose should be determined by the nature of the device.

[0020]

According to the present invention, since the ID storage section is provided separately for the control section and the extension section, when the extension section is changed, only the extension section is remade and only the ID of the extension section is changed. Good. Therefore, the substrate can be shared, the development period can be shortened, and the economical burden can be reduced. Also,
Improves reliability.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an apparatus according to the present invention.

FIG. 2 is a block diagram showing an internal configuration of an ID storage unit according to the present invention.

FIG. 3 is a block diagram showing an internal configuration of another ID storage unit according to the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional device.

5 is a block diagram showing an internal configuration of an ID storage unit of FIG.

[Explanation of symbols]

 6 Expansion Slot 11 Control Board 12 Expansion Board 13 ID1 Storage 14 ID2 Storage

Claims (4)

[Claims] 1. An information processing apparatus configured to be expandable, comprising: a control unit for controlling the entire apparatus; an expansion unit; and a connection unit for connecting the control unit and the expansion unit, the control unit being provided in the control unit. A first ID storage unit that stores the ID of the control unit, a second ID storage unit that is provided in the expansion unit and that stores the ID of the expansion unit, and an ID read command from the CPU provided in the control unit. An information processing apparatus comprising: a read control means for reading each ID from the first ID storage section and the second ID storage section according to the above. 2. The control unit connects the first I to the bus line.
A D storage unit and a CPU are connected, the expansion unit is connected to the bus line to the second ID storage unit, and the connection unit is configured to connect the bus line of the control unit and the bus line of the expansion unit. The information processing apparatus according to claim 1, wherein the information processing apparatus is provided. 3. The read control means recognizes an ID read command from the CPU on the basis of an address signal of a bus line of the control section and outputs an ID from the first ID storage section and the second ID storage section. The information processing apparatus according to claim 2, wherein the information processing apparatus is controlled to output. 4. The read control means recognizes an ID read command from the CPU on the basis of an address signal of a bus line of the control section, and controls to output the ID from the first ID storage section. 3. The information according to claim 2, wherein the ID read command from the CPU is recognized based on the address signal of the bus line of the expansion unit, and the ID is controlled to be output from the second ID storage unit. Processing equipment.