KR900009212Y1 - Address control apparatus - Google Patents

Abstract

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Description

Address controller

1 is a schematic block diagram of a microcomputer system.

2 is a schematic block diagram of a system implementing the present invention by extending the address bus of the system of FIG.

3 is a timing diagram showing switching of an address signal and timing of generation of a read / write control signal.

* Explanation of symbols for main parts of the drawings

M1: first memory M2: second memory

6: 1st address bus 8: 2nd address bus

CPU 1: Central Processing Unit CPU 2: Data Processing Unit

7 data bus 17 selector means

The present invention relates to an apparatus for controlling addressing of a memory in a system such as a microcomputer, and more particularly, to an address control apparatus for a limited address bus.

In general, in the microcomputer system as shown in FIG. 1, the central processing unit PUC 1 and the memory M1 are provided (However, in the present specification, the memory M1 includes a plurality of memories connected to the address bus 1 and A plurality of I / O adapters assigned to memory addresses). The memory M1 has a plurality of addressable storage positions, respectively. The CPU 1 accesses a predetermined storage position of the memory M1 through an address bus 1 composed of a plurality of address lines (for example, 20 lines). Then, through the control line 3, for example, the L (low) level read control signal is sent to the memory M1 to read data from the memory M1, while, for example, through the control line 4, for example. The data is written to the memory M1 by sending an L (low) level write control signal to the memory M1. It should be noted that the CPU used has a unique number of address lines, and the memory space accessible by the CPU is determined as the number of the address lines. For example, if the address line is 20 lines, it is possible to individually designate addresses up to 2 ²⁰ = 1,048.576, thus using up to 1 Mbyte of memory space.

With recent advances in technology, so-called expansion and use CPUs having a large address space, i.e., a fixed number of address lines, are commercially available. However, if the presently used CPU is replaced with the above-mentioned expansion combined CPU to enhance the function of the presently used CPU and at the same time plan to serialize new and old products, the following problems cannot be avoided. For example, if the address line of the current CPU is 20 lines and the memory space is 1Mbytes, and the address line of the expansion and use CPU is 24 lines and the memory space is 16Mbytes, the design change for CPU replacement is minimized. It is desirable to expand the memory space to 16M bytes by expanding the memory currently in use having 20 address terminals. However, in the case of accessing 24 address lines to a memory having 20 address terminals, each memory cannot identify the signals of the four additional address lines, so that the CPU cannot actually access the memory correctly. .

On the other hand, if the memory is replaced with all 24 terminals, the memory currently in use with 20 address terminals becomes obsolete, and a significant design change is required, and the necessary cost is enormous.

The object of the present invention is to realize a compatibility with a so-called expansion-use CPU by using a memory having an address terminal before expansion as it is.

According to the present invention, a second memory (for example, having 24 address terminals) expanded with respect to a first memory (for example, having 20 address terminals) is provided simultaneously with these memories. Is connected to an address bus (eg has 24 address lines) to address 20 address lines for the first memory and 24 address lines for the expanded second memory. .

Furthermore, in order to prevent malfunction of read / write, the following selector means is provided. In other words, this selector means detects signals on address lines that are not used for addressing the first memory (e.g. four), and reads the CPU when it is a specific signal (e.g. all zeros). The write / write control signal is supplied only to the first memory, and if it is not one specific signal, the read / write control signal of the CPU is supplied only to the second memory.

As a result, the CPU reads / writes only one memory selected from the first memory and the second memory, thereby completely preventing the malfunction that data to be written into one memory is written into the other memory.

FIG. 2 shows an embodiment of the present invention which is extended from the conventional example of FIG. 1, and therefore, the same reference numerals are assigned to the same configurations as those of FIG. CPU2 is extended and combined with CPU1 shown in FIG. 1, while CPU1 has an address bus 1 composed of 20 lines, while CPU2 includes address buses 6 and 8 composed of 24 lines. . Of course, it will be understood that the present invention is not limited to the configuration having a specific number of address lines as described above. In addition, although the address buses 6 and 8 are not actually provided in two as shown in FIG. 2, here, for convenience, the address bus 6 which has 24 lines is comprised of the address bus which consists of 24 lines. ) And the address bus 8 having four lines will be described.

The memory M2 is an extended memory and has 24 addressing terminals. The memory M1 is addressed by 20 lines of the address bus 6, and the memory M2 is addressed by 24 lines of the address buses 6 and 8. Each of the memories M1 and M2 includes a read enable terminal R and a write enable terminal W, each of which is supplied with an L level signal from the R terminal or the W terminal of the CPU 2 to the data bus 7. Through this, data can be read from or written to the memories M1 and M2 from the CPU2.

The decoder DEC 12 is connected to the address bus 8. The decoder 12 outputs the H level signal to the line 13 when the signals of the four lines of the address bus 8 are all "0" (that is, the L level). When any one of the four lines of the bus 8 is "1", the L level signal is output to the line 13. The terminal and the W terminal of the CPU2 are connected to the input terminal of the selector SEL 17 via the lines 14 and 16. In addition, in FIG. 2, other control terminals, such as an interrupt control terminal of CPU2, are abbreviate | omitted for convenience of description. The selector SEL 17 is for switching a pair of signals of the R terminal and the W terminal of the CPU 2 to either the X port or the Y port. The X port is connected to the read enable R terminal of the memory M1 and the W enable terminal of the write enable via lines 18 and 20, and the Y port is connected to the memory M2 through the lines 22 and 24, respectively. Are connected to the R read enable terminal and the W enable enable terminal, respectively. The port selection operation of the selector SEL 17 is performed by a signal on the line 13 supplied from the decoder DEC 12. In other words, when the signal on the line 13 is H level, port X becomes valid and port Y is invalid. On the other hand, when the signal on the line 13 is L level, port Y is invalidated and port X is It is invalidated.

Now specify 24 lines of address buses 6 and 8 as A ₀ to A ₂₃ , of which A ₀ to A ₁₉ are used for addressing memory M1 and A ₀ to A ₂₃ for addressing memory M2. It shall be used.

First, if CPU2 generates an address signal such that A ₂₃ = A ₂₂ = A ₂₁ = A ₂₀ = 0 and A ₀ to A ₁₉ have any value, then A ₂₃ = A ₂₂ = A ₂₁ = A ₂₀ = 0. The DEC 12 detects and, accordingly, the H level signal is output to the line 13. In this case, since the SEL 17 validates the port X and invalidates it to the port Y, the CPU 2 reads to the R and W terminals of the memory M1 through the lines 14, 16, the ports X, and the lines 18, 20. It is possible to send / write control signals, and accordingly, data can be read or written from the CPU2 to the storage position of the memory M1 addressed as A ₀ to A ₁₉ from the CPU2.

Next, if CPU2 generates an address signal such that any of A _23, A _22, A ₂₁ , and A ₂₀ does not become "0" and A0 to R ₁₉ have any value, A _23, A _22, A ₂₁ , A _The DEC 12 detects that at least one of the values ₂₀ does not become "0", and outputs an L level signal to the line 13. As a result, the SEL 17 validates the port Y and invalidates the port X. Therefore, the CPU2 is connected to the R and W terminals of the memory M2 through the lines 14 and 16, the port Y and the lines 22 and 24. The read / write control signal can be sent. That is, it becomes possible to read out or seoip of data for the memory location of A ₀ to A ₂₃ an address designated by the memory M1 from the CPU2 through the data bus 7.

3 is a timing diagram showing the selection of the address signal and the timing of generation of the read control signal R and the write control signal W. FIG. In Fig. 3, timings T _n , T _{n + 1,} T _{n + 2} ,. The address signal is switched at. Then, the read control signal R and the write control signal W are delayed by? T from the switching timing of the address signal by timings T _r and T _w in response to a request from the CPU2. Since the port selection operation of the decoding operation SEL 17 of the DEC 12 is completed within this period t, for example, no port selection has yet been made at the time of the writing control signal W, and no malfunction It does not occur

In addition, it will be readily understood by those skilled in the art that the I / O address space of the present invention can be similarly operated.

As described above, according to the present invention, by providing a selector means for switching a read or write control signal from the CPU, the existing memory can be used as it is for a CPU having an extended address bus, and the design can be easily changed. It is possible to improve the performance by expanding the memory space of the system at a low cost.

Claims (1)

Has a plurality of addressable storage locations, has a first storage device M1 for reading or writing data in response to a control signal from the outside, and has a plurality of addressable storage locations, and controls from the outside A second memory device M2 for reading or writing data in response to the signal, a first address bus 6 comprising a plurality of lines for addressing the first memory device, and the first memory device; A second address bus 8 composed of at least one line for addressing the second memory device in combination with the address bus and exchange of data with the first and second memory devices via a data bus; Is performed, while at the same time supplying an address signal through the first and second address buses, performing data read or write control. And a data processing unit (CPU2) for generating the control signal, and detecting that the address signal on the second address bus is a specific signal, and supplying the control signal from the data processing device only to the first storage device. And selector means (12, 17) for detecting that the address signal is not a specific signal and supplying the control signal from the data processing device only to the second storage device.