JP3386457B2 - Semiconductor storage device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device having a cache memory therein. [Prior art] Conventionally, in order to improve the cost performance of computer systems, a low-speed, low-cost, large-capacity dynamic RAM (DRAM) is used for the main memory, and a small-sized high-speed buffer is It has been common practice to provide a high-speed memory having a large capacity. The above-described high-speed buffer is called a cache memory, and copies a block of data likely to be needed by the CPU from the main memory and holds it. When data at an address accessed by the CPU exists in the cache memory (cache hit), the CPU fetches necessary data from the cache memory. On the other hand, when the data at the address accessed by the CPU does not exist in the cache memory (cache miss), the CPU fetches necessary data from a low-speed main memory (DRAM). Incorporating the above-described cache memory system into a memory system requires an expensive high-speed memory, so that it cannot be used in a small-sized computer system that emphasizes cost. Therefore, a simple cache system has been configured by utilizing the high-speed access functions of the DRAM such as the page mode and the static column mode. Hereinafter, the page mode and the static column mode will be described with reference to the waveform diagram of FIG. In the figure, (a) shows a normal DRAM cycle, (b) shows a page mode cycle, and (c) shows a static column mode cycle. As shown in FIG. 2A, in the normal cycle, the signal ▲
▼ At the falling edge of (Row Address Strobe), the row address (Row Addres) is obtained from the multiplex address signal MA.
s) RA is taken into DRAM and signal ▲ ▼ (Columm Addr
At the falling edge of the ess strobe, a column address (Colum Address) CA is taken into the DRAM from the multiplex address signal MA. Then, the data of the memory cell selected by the row address RA and the column address CA is obtained as the data output _Dout . Since the normal cycle reads data in the above cycle, the access time is a time t _RAC from the falling edge of the signal ▲ ▼ until the data output D _out becomes valid.
(RAS access time). This access time t
_RAC is usually about 100 ns. Note that t _RP is a signal ▲
The precharge time of t, t _C, is the cycle time, which is usually about t _C = 200 ns. As shown in FIG. 7B, in the page mode cycle, data can be read out at a plurality of column addresses CA on the same row address RA. Therefore, the access time depends on the signal ▲ ▼
The time t _CAC (CAS access time) from the falling edge of the data until the data output D _out becomes valid is about half of the access time t _RAC in the normal cycle, usually 50
ns. Here, t _CP is a precharge time of the signal ▼, and t _PC is a cycle time. As shown in FIG. 9C, the falling edge of the page mode signal ▼ is not required in the static column mode, and the column address CA is operated as if it were a static RAM. Therefore, the access time is the time t _AA (address access time) from the time when the multiplex address MA changes to the time when the data output D _out becomes valid, and t
_CAC same usually becomes about half of the access time t _RAC in the cycle, which is usually about 50ns. FIG. 7 is a configuration block diagram showing a basic configuration of a conventional DRAM element capable of a page mode or a static column mode. As shown in the figure, a row address buffer 1 and a column address buffer 2 take in a row address RA and a column address CA, respectively, from a multiplex address signal MA. When the falling edge of the signal ▼ is input to the row address buffer 1, the row address RA is sent to the row decoder 3, and the next stage word driver 4 is driven, thereby the memory cell array selected by the row address RA. Activate one word line (not shown) in 5. Then, data of all memory cells connected to the activated word line is sent to the sense amplifier 6 via all bit lines (not shown) in the memory cell array 5. The sense amplifier 6 detects and amplifies the obtained data. Therefore, the data for one row of the specified row address RA is latched in the sense amplifier 6 at this time. Thereafter, when accessing the same data with the same row address RA, the above-described page mode and static column mode can be used. That is, in the page mode, when the falling edge of the signal ▼ is input to the column address buffer 2, the column address CA is sent to the column decoder 7, and one of the data groups stored in the sense amplifier 6 is enabled. Thus, a data output D _out is obtained via the output buffer 8. Multiplex address for startup even in static column mode
The same operation is performed except for the change in MA. 9 is an I / O switch for controlling data input / output, 10 is an input buffer, and _Din is a data input. FIG. 8 is a block diagram of a conventional memory system having a simple cache system using a page mode (or a static column mode). As shown in the figure, this memory system has eight 1M × 1 configuration DRs.
This is a 1-Mbyte memory system configured using AM elements 11 to 18. Therefore, there are 20 address lines (2 ²⁰ = 1048576 = 1
M) requires, but in practice, address multiplexer 21
Multiplexed address signal MA divided into row address RA (10 bits) and column address CA (10 bits)
Ten address lines are connected to each of the DRAM elements 11-18. FIG. 9 is a waveform diagram showing a cache operation of the memory system shown in FIG. FIG. 9 and FIG.
The operation of the memory system shown in FIG. 8 will be described with reference to FIG. It is assumed that the row address RA1 accessed immediately before is already latched in the latch 22, and all data of the row address RA1 is already latched in the sense amplifier 6. In such a state, a 20-bit address signal Ad of data required by a CPU (not shown ₎ is generated by an address generator.
Generated from 23. From this address signal _Ad , the row address RA
2 is input to the comparator 24, and the comparator 24 determines the row address RA2 and the row address R stored in the latch 22.
A1 is compared with A1, and if RA1 = RA2, sense amplifier 6
Is accessed (cache hit), and the comparator 24 is activated (“H” level). The cache hit signal CH (Cache Hit)
To the state machine 25. The state machine 25 that has received the activated signal CH performs a page mode control of toggling the signal ▼ (falling after rising) while keeping the signal ▲ at the “L” level, and the address multiplexer 21 performs the DRAM operation. Multiplex address for elements 11-18
The column address CA is supplied as MA, and the data selected by the column decoder 7 is extracted from the data group stored in the sense amplifier 6 of each of the DRAM elements 11 to 18. In the case of such a cache hit, output data _Dout is obtained from the DRAM elements 11 to 18 with a high access time t _CAC . On the other hand, when RA1 ≠ RA2 is determined in the comparator 24, access is made to a data group other than the data group held in the sense amplifier 6 (cache miss), and the comparator 24 is inactivated (“L "Level" signal CH. At this time, the state machine 25 outputs the signal ▲
Normal cycle DR that toggles in the order of ▼, ▲ ▼
Controls the AM elements 11 to 18, and controls the address multiplexer 21.
Supplies a multiplex address MA to the DRAM elements 11 to 18 in the order of a row address RA2 and a column address CA. When such a cache miss, precharging to indicate signal ▲ ▼ in FIG. 9, further so that the output data D _out with slow access time t _RAC obtained from DRAM devices 11 to 18. Therefore, the state machine 25 generates a wait signal Wait and waits for the CPU. Further, when the latch 23 receives the inactive cache hit signal CH from the comparator 24, the latch 23 holds the new row address RA2. [Problems to be Solved by the Invention] A conventional simple cache system uses a cache hit signal CH based on a cache hit signal CH obtained from the outside.
Since a cache miss is determined, there is a problem that one extra external control signal must be used for determining a cache hit / cache miss. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to obtain a semiconductor memory device having a cache system without externally increasing external control signals. [Means for Solving the Problems] A first aspect of a semiconductor memory device according to the present invention is a semiconductor memory device comprising: a main memory having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each of which stores information; A cache memory that stores information read from the main memory, and is connected between the main memory and the cache memory, and is a memory cell array operation activation instruction signal for the main memory. According to a row address strobe signal, when the row address strobe signal is at a first level indicating a cache miss, the information of the main memory is transferred to the cache memory and at a second level indicating a cache hit. Transfer means for not transferring the information in the main memory to the cache memory. You. A second aspect of the semiconductor memory device according to the present invention includes a main memory having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each of which stores information, wherein the main memory includes a plurality of memories. The cell is divided into a plurality of blocks in a plurality of columns, and has a plurality of storage elements,
A cache memory for storing information read from the main memory, wherein the cache memory stores information read in blocks from the main memory in units of blocks; Transfer means for transferring information read from the main memory to the cache memory according to a cache control signal indicating a cache hit or cache miss and a write and read control signal indicating a write or read operation. Furthermore, the transfer unit has a plurality of transfer units each corresponding to each block of the main memory, each transfer unit has a plurality of transfer gates, and blocks from the main memory according to the cache control signal. The information read in units When transferring to the cache memory, a plurality of transfer gates of a transfer unit corresponding to a block of the main memory from which the information is read are turned on, and a plurality of transfer gates of the remaining transfer units are turned off [ Operation] Since the transfer means of the first aspect of the semiconductor memory device of the present invention transfers information read from the main memory to the cache memory in accordance with the row address strobe signal, the row address strobe signal also serves as control means of the transfer means. be able to. Further, the transfer means according to the second aspect of the semiconductor memory device of the present invention transfers the information read from the main memory to the cache memory in block units in accordance with the cache control signal and the write control signal. Can change the control content. [Embodiment] The external control signal ▲ (row address strobe) of the DRAM serves as a start signal for normal DRAM reading and writing at the falling edge. However,
As shown in FIGS. 6 (b) and 6 (c), no function is performed in the page mode cycle and the static column cycle, and the signal ▼ does not necessarily need to keep the “L” level during this period. Therefore, the signal RAS is defined as follows in the page mode cycle and the static column cycle. Signal RAS "H" level = cache hit Signal RAS "L" level = cache miss FIG. 1 is a block diagram showing a basic structure of a DRAM element of a memory system having a cache function according to an embodiment of the present invention. In the figure, 1-4, 8-10 and ▲
Since ▼, MA, RA, and CA are the same as those in the related art, description thereof will be omitted, and only points different from the related art will be described below. As shown in the figure, the memory cell array 5 is divided into blocks B1 to B1.
Since B4 is divided into four parts, the transfer gates 31 (31a to 31d), which are transfer units, and the data registers 32 (which are cache memories) are provided between the sense amplifier 6 and the I / O switch 9 corresponding to the blocks B1 to B4. 32a to 32d) are inserted. As shown in the detailed block diagram of FIG. 2, each of the transfer gates 31 is controlled by a block decoder 34, which is a selecting means, so that the data of the memory cell array 5 is blocked (B1 to B1) by its conduction / non-conduction. B4) The data can be transferred to the corresponding data registers 32a to 32d via the sense amplifier 6 in units. The activation of each of the block decoders 34a to 34d is controlled by an AND gate G1 which receives as input signals the upper two bits of the column address CA and an inverted signal of the signal ▼. That is, when the signal ▼ is at the “L” level, one of the block decoders 34a to 34d selected by the upper two bits of the column address CA is activated, and when the signal ▼ is at the “H” level,
None of the block decoders 34a to 34d is activated. That is, the transfer gate 31 outputs the row address strobe signal.
Conduction / non-conduction is controlled based on RAS. When any of the block decoders 34a to 34d is activated, the corresponding transfer gates 31a to 31d are turned on. On the other hand, the column decoder 7 receives the column address CA as an input signal and enables one of the I / O switches 9. FIG. 3 is a block diagram showing a memory system having a cache function according to an embodiment of the present invention.
As shown in the figure, unlike the conventional case, the four latches 22a to 22a
2d is provided. Further, a selector 36 is provided as a selection means for the latches 22a to 22d, the selector 36 is all bits and a column address of the row address RA from the address signal A _d
The latch 22 to be compared with the comparator 24 based on the upper 2 bits of the column address CA as an input signal with the upper 2 bits of CA as an input signal.
a to 22d, and at the time of a cache miss in which the cache hit signal CH output from the comparator 24 is inactive, the value of the row address RA is set to the selected one of the latches 22a to 22d.
2d. Hereinafter, the operation of the memory system according to the embodiment of the present invention shown in FIGS. 1 and 2 will be described with reference to waveform diagrams at the time of cache hit and cache miss in FIG.
Note that the latches 22a to 22d have already latched the row addresses RA1a to RA1d accessed immediately before in the respective blocks B1 to B4, and the data registers 32a to 32d have all the data of the blocks B1 to B4 at that time. Is already latched. In such a state, the address generator 23 generates a 20-bit address signal _Ad required by a CPU (not shown). Row address RA2 from the address signal A _d is input to the comparator 24. On the other hand, when the upper two bits of the column address CA of the address signal A _d is inputted to the selector 36,
The selector 36 enables only one of the latches 22a to 22d corresponding to the selected blocks B1 to B4. Here, assuming that the block B2, that is, the latch 22b is selected for convenience of explanation, the comparator 24 compares the input row address RA2 with the row address RA1b stored in the latch 22b, and if RA1b = RA2 If the cache hit signal is activated (“H” level)
Send CH to state machine 25. Then, upon receiving the activated cache hit signal CH, the state machine 25 sends an “H” level signal ▼ to each of the DRAM elements 11-18. At this time, since the signal ▼ changes to “H” level, all the block decoders 34 are not activated, all the transfer gates 31 are not conductive, and all the data registers 32 and the sense amplifier 6 are electrically disconnected. ing. On the other hand, the state machine 25 performs page mode control for toggling the signal ▲ while keeping the signal ▼ at the “H” level, and the address multiplexer 21 controls the DRAM elements 11 to 18 as the column address as the multiplex address MA.
CA is supplied, and data selected by the column decoder 7 is extracted from the data group stored in the data register 32b of each of the DRAM elements 11 to 18 via the I / O switch 9. When a cache hit occurs in this way, output data _Dout can be obtained from the DRAM elements 11 to 18 with a fast access time t _CAC . When RA1 ≠ RA2 is determined by the comparator 24, it is regarded as a cache miss and an inactive (“L” level) cache hit signal CH is sent to the state machine 25 and the selector 36. Then, the inactive cache hit signal CH
The state machine 25 receives the “L” level signal ▲
Is sent to each of the DRAM elements 11-18. At this time, since the signal ▼ becomes “L” level, only the block decoder 34b is activated, the transfer gate 31b is turned on, and the data register 32b and the sense amplifier 6 are electrically connected. Note that the other data registers 32a,
32c, 32d and the sense amplifier 6 remain electrically disconnected. On the other hand, the state machine 25 that sent the signal ▲ ▼
Next, DRAM elements 11 to
The address multiplexer 21 controls the multiplex address MA in the order of the row address RA2 and the column address CA.
Supply to DRAM elements 11-18. Then, the data selected by the column decoder 7 from the memory cell array 5 via the sense amplifier 6, the transfer gate 31b, the data register 32b, the I / O switch 9 and the output buffer 8 is output to the output data.
_Read as D _out . This is at the time of a cache miss so, the output data D _out with slow access time t _RAC from the DRAM device 11 to 18 is obtained. Therefore, the state machine 25 generates a wait signal Wait and waits for the CPU. The new row address RA2 is held in the latch 22b selected by the selector 36. (Other latch 2
The values in 2a, 22c and 22d do not change. As described above, since the memory management of the DRAM elements 11 to 18 at the time of a cache hit or a cache miss can be performed in units of the blocks B1 to B4, each of the blocks B1 to B4 independently stores the data group corresponding to the row address in the data register. 32
, The number of entries is four. As a result, it is possible to cope with a case where a program routine over two consecutive row addresses is repeatedly executed, and the cache hit rate is improved. In addition, signals that are always connected to normal DRAM elements
By using ▼ for determining a cache hit or a cache miss, there is no need to add another external control signal, and the number of external terminals does not increase. In the embodiment shown in FIG. 1, the cache control is performed according to the signal ▼ regardless of the reading and writing of the memory. However, as shown in FIG. 5, the signal ▼ and the inverted signal of the writing signal ▼ are shown in FIG. By inputting the inverted signal of the output of the OR gate G2 with the input signal as an input signal to the AND gate G1, at the time of writing (▲ ▼ = “L”),
The output of the AND gate G1 is fixed to "L" regardless of the signal "H" or "L" of the signal ▲ ▼, so that all the block decoders 34 are not activated. Switching such as “conduction” can also be realized. Then, at the time of reading (▲ ▼ =
"H") is, as in the embodiment shown in FIG. 1, operated by judging a cache hit / miss based on "H" and "L" of the signal ▼. Thus, the write signal ▲ ▼ and the signal ▲
By controlling the activation / deactivation of the block decoder 34 based on ▼, more precise control can be performed. It should be noted that the combination of the write signal ▲ and the signal ▼ can also be realized in the same manner as the combination other than the combination shown in FIG. Further, in this embodiment, the memory cell array 5 has a configuration of four blocks B1 to B4 (the number of entries is four). However, it is needless to say that the number of divided blocks can be appropriately increased or decreased. [Effects of the Invention] As described above, according to the first aspect of the semiconductor memory device of the present invention, the transfer unit transfers information read from the main memory to the cache memory in accordance with the row address strobe signal. Since the row address strobe signal also serves as the control means of the transfer means, there is an effect that it is not necessary to add a new external control signal. According to the second aspect of the semiconductor memory device of the present invention, the transfer means transfers information read from the main memory to the cache memory in accordance with the cache control signal and the write and read control signals. By changing the control content at the time of reading,
More detailed control can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram of a configuration of a DRAM device in a memory system having a cache function according to an embodiment of the present invention. FIG. 2 is an explanatory diagram of a detailed configuration of the DRAM device of FIG. FIG. 3 is a block diagram of a memory system having a cache function according to one embodiment of the present invention, FIG. 4 is a waveform diagram showing a cache operation of one embodiment of the present invention, and FIG. FIG. 6 is an explanatory diagram of a configuration of a DRAM device in a memory system having a cache function according to an embodiment. FIG. 6 is a waveform diagram showing a high-speed access function in the DRAM. FIG. 7 is a configuration of a DRAM device in a memory system having a conventional cache function. FIG. 8 is a block diagram of a conventional memory system having a cache function, and FIG. 9 is a waveform diagram showing a conventional cache operation. In the figure, 5 is a memory cell array, 6 is a sense amplifier, 22a to 22d are latches, 24 is a comparator, 31a to 31d are transfer gates, 32a to 32d are data registers, 34a
~ 34d is a block decoder, 36 is a selector, ▲ ▼
Is a row address strobe signal. In the drawings, the same reference numerals indicate the same or corresponding parts.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Kazuyasu Fujishima               4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric               KIKI Co., Ltd. (72) Inventor Yoshio Matsuda               4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric               KIKI Co., Ltd. (72) Inventor Mikio Asakura               4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric               KIKI Co., Ltd.                (56) References JP-A-56-61082 (JP, A)

Claims (1)

(57) [Claims] A main memory having a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing information; a cache memory having a plurality of storage elements and storing information read from the main memory; When the row address strobe signal is at a first level indicating a cache miss in accordance with a row address strobe signal which is connected between a main memory and the cache memory and is a memory cell array operation activation instruction signal for the main memory. Transfer means for causing the information in the main memory to be transferred to the cache memory and not transferring the information in the main memory to the cache memory when the second level indicates a cache hit. 2. The transfer unit controls the active state and the inactive state based on the row address strobe signal and transfers information read from the main memory to the cache memory by a selection unit that receives a part of a column address signal. 2. The semiconductor memory device according to claim 1, wherein whether to perform the operation is controlled. 3. The main memory is configured such that a plurality of memory cells are divided into a plurality of blocks in units of a plurality of columns, the cache memory stores information read from the main memory in units of blocks, in units of blocks, A plurality of transfer units each corresponding to each block of the main memory, each transfer unit having a plurality of transfer gates, and information read out from the main memory in block units according to a row address strobe signal. When transferring to the cache memory, a plurality of transfer gates of the transfer unit corresponding to the block of the main memory from which the information is read are made conductive,
2. The semiconductor memory device according to claim 1, wherein a plurality of transfer gates of the remaining transfer section are turned off. 4. The plurality of transfer gates of each transfer unit of the transfer unit are provided corresponding to the transfer unit, and active and inactive states are controlled based on the row address strobe signal and a part of a column address signal is transferred. 4. The semiconductor memory device according to claim 3, wherein the conduction state and the non-conduction state are controlled by the receiving block selecting means. 5. 5. The semiconductor memory device according to claim 3, wherein a plurality of storage elements in each block of said cache memory are provided in a same number of columns as a plurality of columns in each block of said main memory. 6. A main memory having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each of which stores a plurality of memory cells, wherein the plurality of memory cells are divided into a plurality of blocks in a plurality of column units; Further comprising a cache memory for storing information read from the main memory, the cache memory storing information read in blocks from the main memory in units of blocks, The information read from the main memory is connected to the cache memory according to a cache control signal indicating a cache hit or a cache miss and a write and read control signal indicating a write or read operation, connected between the memory and the cache memory. A transfer unit for transferring, the transfer means Has a plurality of transfer units respectively corresponding to each block of the main memory, each transfer unit has a plurality of transfer gates, and is read from the main memory in block units according to the cache control signal. When transferring information to the cache memory, a plurality of transfer gates of a transfer unit corresponding to a block of the main memory from which the information is read are turned on, and a plurality of transfer gates of the remaining transfer units are turned off. Semiconductor storage device. 7. The transfer means establishes a connection relationship between the main memory and the cache memory when the write and read control signals indicate writing, regardless of the state of the cache control signal, and the write and read control When the signal indicates a read, if the cache control signal indicates a cache hit, the main memory and the cache memory are disconnected, and if the cache control signal indicates a cache miss, the read from the main memory is performed. 7. The semiconductor memory device according to claim 6, wherein the transferred information is transferred to said cache memory. 8. The plurality of transfer gates of each transfer unit of the transfer unit are provided corresponding to the transfer unit, and an active state and an inactive state are controlled based on the cache control signal and the write / read control signal. 7. A conductive state and a non-conductive state are controlled by a block selecting means for receiving a part of a signal.
13. The semiconductor memory device according to claim 1. 9. The block selecting unit sets a plurality of transfer gates of all transfer units of the transfer unit to a non-conducting state when the write and read control signals indicate a write, regardless of a state of the cache control signal. And when the read control signal indicates a read, if the cache control signal indicates a cache hit, the transfer gates of all the transfer units of the transfer means are turned off, and the cache control signal indicates a cache miss. 9. The device according to claim 8, wherein the plurality of transfer gates of the transfer unit corresponding to the block of the main memory from which the information is read are turned on, and the plurality of transfer gates of the remaining transfer units are turned off. Semiconductor storage device.