JPS6238590A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To write data at a high speed by installing a DRAM and an SRAM on the same semiconductor substrate and giving a means for transmitting data of one line in the DRAM or the SRAM to the SRAM or the DRAM and an additional address bit for exclusive use of SRAM. CONSTITUTION:The potential of a row word line selected by the additional address bits A9-A12 in the SRAM is raised, and a voltage corresponding to the contents in the row of the SRAM is outputted every column. A data transfer control part 51 raises the gate voltage TR of a data transfer gate 50, opens the gate 50, drops an SAE when a BL, the inverse of BL develop some difference, activates a sense amplifier 25, increase a difference voltage between bit lines, raise the potential of the word line WL1 of the prescribed row in the DRAM selected by address bits A0-A8, and writes data in the cell of the DRAM to which the word line belongs. In this write mode, data is sequentially written in the SRAM at a high speed, and one line of data is transferred at once and written in the DRAM. Thus data can be written far speedily.

Description

[Detailed description of the invention] [General] High-speed transfer means? A built-in storage device, which includes DRAM and SRAM on the same chip, and is provided with means for transferring data one row at a time from either one of them to the other.
Make SRAM look like cache memory.

[Industrial application field]

The present invention relates to a semiconductor memory device incorporating high-speed transfer means, and particularly to a memory device having DRAM (dynamic random access memory) and SRAM (static random access memory) on the same chip.

[Conventional technology]

Conventionally, configuring a cache memory required an individual high-speed memory, and a bus had to be provided for data transfer between the main memory and the cache memory, making the configuration complicated.

On the other hand, it is being considered to incorporate a high-speed transfer means into a semiconductor memory device and make it into a single chip. So-called 2 baud) R
These are AM, SCRAM, etc., and schematic diagrams of them are shown in Figures 7 and 8.

The two-bottom RAM shown in FIG.
One row of data stored in the shift register is transferred to the shift register 2 at a time, and by giving the first address from the DRAM address, one row of data stored in the shift register is cyclically and sequentially output to the port P2 in accordance with the clock of the shift register.

- Data can also be read from port P1 of 1,000 DRAM as usual, and this storage device has an output port of 2.
It is called RAM because there are 2 ports).

In the SCRAM shown in FIG. 8, 1 is a DRAM area, 4 is a sense amplifier lattice, and 5 is a stacked column decoder. One row, for example, 5 rows, is output in succession, the data is latched into the sense amplifier latch f4, and a column decoder constituted by a static circuit outputs one of the words in one row. In this case, there is only one output port.

[Problem that the invention seeks to solve]

However, in the 2-bot RAM shown in FIG. 7, the data in shift register 2 cannot be taken out randomly, so this! It cannot be used as a cache. Furthermore, in the SCEAM shown in FIG. 8, only one row, which is latched, can be accessed at high speed randomly, which is not sufficient to use it as a cache.

[Means for solving problems]

In the present invention, as shown in FIG.
AM11 and SRAM12 are provided, and the DR memory 11
Or transfer one row of data from SRAM12 to SRAM or DRA.
It has a means 13 for transferring data to M and an additional address bit dedicated to 5RAII, so that the SRAM functions as a cache.

[For production]

In the conceptual diagram of FIG. 1, DEAM 11 has 512 lines.

The SRAM 12 is configured with 512 columns and 16 rows and 512 columns 1; 16 rows of information on the DEAM side can be transferred to the SRAM 12 one row at a time. The transferred information in the SRM 52 can be rapidly transferred using the column address of the DRAM and the additional address dedicated to the SRAM.

On the other hand, it is also possible to write all the data into the SRAM 12C at high speed, and then transfer one row Y once to the ζ2 DRAM 11f via the data transfer means.

〔Example〕

FIG. 2 shows a configuration diagram of an embodiment of the present invention.

In Figure C2, the DEAN cell array 21 is similar to Figure 1.
is 512 x 512, 5RAkf self' L/(2
2×512×16, and a data transfer gate 50 is provided between the two. 25 and 25 are the column decoder and sense amplifier/I10 gate of DRAM 11, respectively, and 24 and 26 are the SRAM 1
2 column decoder and I10 gate. 27 again
28 is a DRAM row decoder, and 28 is an SRAM row decoder. AO to A8 are DRAM addresses,
A column address and a row address are taken in by a column address buffer 55 and a row address buffer 56, respectively, and the column address is taken in by a column decoder 25 of the DRAM.
and SRAM column decoder 26 (: commonly given,
The row address is given to the DRAM row decoder 27C. A9 to AI2 are row addresses dedicated to the SRAM, and are given to the row decoder 28C via the SRAM row address buffer 40'a'. 31 and 33 are DRAM output and input cover sofas; 52. ! 4 is an SRAM output and input buffer. Reference numerals 61 and 62 at the bottom of FIG. 2 are various control units for the DRAM, respectively.

Various control units for the SRAM are represented, and 51 is a control unit for the data transfer gate.

The DEAM control unit 61 (= is given RAS (row address capture timing), CAS (column address capture timing) and WEl (write timing), and the SRAM control unit 62 is provided with cg
(timing to activate static circuits),
Control signals WEl (write timing) and OE (output timing) are provided. Further, the data transfer control unit 511: is given a TR (data transfer timing) control signal.

FIG. 3 shows the circuit portion in the column direction of FIG. 2, and the same parts as in FIG. 2 are designated by the same numbers.

The operation modes of this embodiment can be roughly divided into the following four modes.

■ Writing and reading on the DRAkf side.

■Writing and reading on the SRAM side.

■ Send data on the DRAM side to SRAM.

■ Send data on the SRAM side to DEA#2.

The following describes each of these modes using the time chart in Figure 4 and the time chart in Figure 5.
This will be explained in conjunction with the waveform diagram in FIG.

Writing and reading of the DRAM (2) is equivalent to that of a normal DRAM. At this time, TR is “H”, CE is “H”,
Transfer gate 50 is closed and the SRAM side is not activated.

■ In SRAM write and read mode, TR is “H”
The transfer gate 50 remains closed and the normal operation is performed. At this time, CE becomes "L" as shown in FIG.

(2) Mode for sending data from the DRAM to the SRAM Referring to FIG. 5, first the TR is lowered and the data transfer control section 51 ratifies this.

Next, the RAS drops and is the same as a normal read cycle.
The voltage of the DEAM type cell array 1 increases, and the cell data is output to the bit lines BL and EL.
In the figure, BL is at "L" level and EL is lowered.

At this time, the SAE of the sense amplifier decreases and is activated. Next, select the row you want to write in the SRAM at the row address (A9~
A12. (additional address bit), and the potential of the word line WLα of the selected row increases.

Next, the output TR of the data transfer gate goes up, the transfer gate 50 opens, and the data is transferred from the DRAII to the SRAM.
The data is transferred to the bit lines EL and B of 5RAIII.
The voltage of L starts to reverse and BL is reversed as shown in the figure, and 5
RAII writing is completed. In this way, DRA
Transfer the data on the M side to SRAM one row at a time and perform SR.
Can be written to AM.

In this mode (■), the row addresses of the SRAM word lines Wα, wb, etc. are taken in at the timing of the DRAM RAS (see Figure 4).
In addition to O-A8, additional 4 address bits A9-A12 are required (=1).

When reading the SRAM written in this way, as shown in FIG.
Read out cell data using each address in columns AQ to A8 and rows A9 to A12. In addition, it may be made to do so (falling down as shown by the broken line in FIG. 4 CAS).

■In the mode where data from the SRAM side is sent to the DRAM, as shown in Figure 6, TR and WEL are lowered, and the data transfer control i
51 and DRM control section 61c (Next, turn off the sense amplifier with SAE and precharge the bit lines BL and BLf.

Next, raise the potential of the word line (WLα) in the row selected by additional address bits A9 to A12 of the SRAM, and apply the corresponding voltage to the contents of the SEAM cell in that row (Nα, Nα) 1 for each column. I'll put it out there. Here, the data transfer control section 51 raises the gate voltage TRf7 of the data transfer gate 50 and opens the gate 50. As a result, when there is a difference in the degree that EL and BL t: SAE l: is lowered, the sense amplifier 25 is activated, and when the voltage difference between the bit lines is made sufficiently large, the predetermined address pin (address pin) selected by AO to A8 is activated. Raise the potential of the word line WL1 of the row DRA) yf to
Input 1 data sound into the cell (data N1).

According to the write mode of this ■, SRAM is faster one after another: Nidata? You can write, transfer one row at a time, and write to DRAM I: Reset and write like the normal write mode of DRAM.

Writing can be performed much faster than writing with repeated reset cycles.

Although the embodiments have been described above, the present invention can be modified in various ways. For example, the column decoder 26 on the SRAM side and the DRA
The column decoder 23 on the M side may be combined into one. Also, the data bus for SRAM and DRAM is 1
It can be shared.

〔Effect of the invention〕

As is clear from the above, according to the present invention C2, a CDRAM and an SRAM can be provided on the same semiconductor substrate, and the SRAM can be used as a cache, and unlike the conventional cache memory, a bus for data transfer is not required. Moreover, by transferring the data in the C21 row once, it is possible to increase the number of transfer bits compared to the conventional method.

[Brief explanation of drawings]

Figure 1 is a conceptual diagram of the present invention. Fig. 2 is a configuration diagram of the embodiment, and Fig. 5 is a circuit diagram (partial diagram) of the embodiment. FIG. 6 is a waveform diagram of data transfer from SRAM to ORAM. FIGS. 7 and 8 are plan views showing the outline of conventional examples, respectively. Main code 11...DRAId 12...SRAM 13...Data transfer means

Claims (1)

[Claims] 1. Dynamic random access memory and static random access memory on the same semiconductor substrate
1. A semiconductor memory device comprising: a memory; and means for transferring one row of data at a time between both memories from one of the two memories to the other. 2. The semiconductor memory device according to claim 1, further comprising a dedicated address bit for selecting a predetermined row of the static random access memory.