KR100193193B1 - High-density memory with on-chip caches associated with N-direction sets and systems using them - Google Patents

Abstract

A memory is described that has a two-way set associated cache capability on-chip and system to use the same as cache and main memory. The memory may be sensed by a local sense amplifier in which each group of rows has loadable sense content in a multiple (eg two) set of main sense amplifiers for storage. At this time, the main sense amplifier can be called in the form of static column decode, where the column group is specified by the Y address, and the main sense amplifier set is associated with the designated group selected by the multiple clock signal (e.g., the only column address strobe Signal is associated with each set). The multidirectional set association of memory provides improved cache hit performance. In addition, the above-described system includes a CPU and a controller, which performs a cache comparator, dirty bits, and LRU stack functions as a conventional cache controller, but as a conventional dRAM controller (such as multiplexing of reproduction, row and column addresses, etc.). It also performs memory control functions. Therefore, this system can use not only cache memory but also the same memory device as main memory.

Description

High-density memory with on-chip caches associated with N-direction sets and systems using them

1 is a block diagram showing the relevance of a cache memory constructed in accordance with the present invention.

2 is an electrical diagram illustrating the operation of a single memory array in block form.

3 is a schematic diagram illustrating a memory constructed in accordance with the present invention comprising multiple of the arrays of FIG.

4 is an electrical diagram schematically showing a connection state between a local sense amplifier and a main sense amplifier in the memory of FIG.

FIG. 5 shows an address word for memory of FIG.

6 is an electrical diagram showing, in block form, a memory system using the memory of FIG.

7A-7C are flowcharts illustrating the system operation of FIG.

FIG. 8 is a timing diagram illustrating the system operation of FIG. 6 in accordance with an exemplary sequence of operations.

9 is an electrical diagram illustrating in block form the operation of a single memory array in accordance with an alternative embodiment of the electrical diagram of FIG.

FIG. 10 is an electrical diagram schematically illustrating a connection state between a local sense amplifier and a main sense amplification in the memory of FIG. 3 for an alternative embodiment of the present invention with respect to the electrical diagram of FIG.

* Explanation of symbols for main parts of the drawings

2: memory array 4A, 4B: address

4A _O , 4B _O : sub-register 6: sub-array

12: row decoder 14: local sense amplifier

16, 18: main sense amplifier 18: pass gate

20: column decoder 24: data line

50: CPU 52, 54: Multiplexer

60: controller

TECHNICAL FIELD The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory having on-chip cache capability.

A continuing trend in the semiconductor arts is to increase the density of memory bits per chip in semiconductor memory devices, such as dynamic constant speed call memory (dRAM). In the past decade, each new dRAM generation has four times the memory capacity of the previous generation, with the latest dRAM chips each containing four megabits. This radical increase in memory density has heightened tension to increase memory bandwidth, ie the speed at which a user can call bits in memory. Unless the memory bandwidth has been improved with increasing memory density, the extra bits provided by the new memory generation will reduce the user's usefulness.

In addition to improving only memory call time, various construction techniques have been directed toward improving memory bandwidth. Modern dRAM devices are provided with static column decode calling capability, where each bit in an accessed row can only be called by providing a column address without having to provide a row address or column address strobe. Examples of dRAMs with static and thermal decode capability are TMS4C1027 dRAM manufactured and sold by Texas Instruments Incorporated and issued on June 14, 1988, and assigned to Texas Instruments Inc. DRAM as described in US Pat. No. 4,750,839. For video and graphics applications, U.S. Patent Nos. 4,639,890, issued January 27, 1987, and assigned to Texas Instruments Inc., and U.S. Patents 4,636,986 and January 1989 A video dRAM device as described in US Pat. No. 4,807,189, issued February 21, may be loaded with multiple bits from the called line and continuously output asynchronously with a constant speed call of the memory array, which is called a constant speed call. Contains registers that are output serially independently from.

A common technique used in data processing systems for improving system memory utilization is the use of cache memory. Cache memory is a relatively small and fast memory that stores data from multiple main memory locations around an addressed memory location. The theory of cache operation is that a system central processing unit (CPU) can often address memory locations (in terms of address values) adjacent to recently addressed memory locations. Each data group stored in the cache is associated with a tag, or a memory address portion common to the data stored in the cache, and the comparator compares the memory address portion provided by the CPU with a tag, or with tags associated with data stored in the cache. do. If a good memory address matches the tag value (that is, a cache hit occurs), the cache can be called to provide good data faster than if the main memory is addressed, thereby improving the effective memory bandwidth of the system. Can be.

If an appropriate portion of a good memory address does not match a tag (ie cache miss') with respect to the data stored in the cache, then the main memory is addressed with a delay associated with the cache call, then The cache portion is generally data from main memory, refilled to an approximate location to the newly addressed main memory location. The additional time required to call the main memory instead of the cache, plus the additional time required to fill the cache with new data from the approximate address to the new memory address, is commonly referred to as a miss penalty. The time required to reload the cache, or the initial call to main memory for a good memory address, varies with the main memory cycle time, and the number of bits in the cache (or the portion of the cache associated with a given tag, generally referred to as a cache line). Proportional to As a result, if the failure condition becomes large, the effective memory bandwidth of the system may decrease even if the failure rate is relatively low. As cache bandwidth improves, it is important not only that system performance improves, and that the cache failure rate decreases, but also that the failure conditions associated with each cache failure decrease.

It has been proposed that dRAM with static column decode features as described above be used in cache structures. Jay, published in The 11th Annual Symposium on Computer Architecture (IEEE Computer Society Press, 1984). See The Use of Static Column RAM as a Memory Hierarchy, pages 167-174, by J. Goodman and M-C, Chiang. However, since this memory stores the entire memory row in the static column buffer, a cache hit requires that the address be in a single row. Although the size of the rows stored in the static column buffer may allow for multiple cache hits (eg, multiple sequential addresses may be addressed), multiple row addresses may be stored at least partially in the buffer. In this case, the likelihood of available cache hits is reduced.

It is an object of the present invention to provide a memory in which a failure rate is reduced due to multiple-way_set association in an on-chip-cache.

Another object of the present invention is to provide a memory that can be effectively used in a dRAM chip.

Another object of the present invention is to provide a memory that requires the smallest off-chip logic to take advantage of cache capabilities.

Another object of the present invention is to provide a memory capable of reproducing a data array without affecting the contents of the cache.

Another object of the present invention is to provide a memory capable of reproducing data in the memory while updating a portion of the cache.

Another object of the present invention is to provide a system using such a memory.

The present invention can be used in a semiconductor memory chip by providing multiple latches associated with each column of a memory array where each latch can selectively connect to a column of sense amplifiers. The latches are grouped into sets corresponding to the column sets of the memory array. From the selected memory row, data can be read and written, and loaded into the selected latch set. Selection of multiple latches associated with each set of columns is accomplished by a multi-column address strobe method.

Hereinafter, embodiments of the present invention will be described similarly with reference to the accompanying drawings.

1 shows the structure of a memory array 2 according to the set relevance of the present invention to illustrate an improved state of cache operation that can be achieved by using the present invention. The array 2 is a rectangular aligned memory cell, such as one transistor one capacitor memory cell, used in modern dRAM devices such as row and column aligned memory cells. To illustrate the operation, array 2 includes 32 rows, numbered from 0 to 31. The array 2 is subdivided into four groups of columns, so each row contains four groups of columns each. Thus, the array 2 consists of four sub-arrays 6 ₀ to 6 ₃ . Of course, less or more than four sub-arrays 6, which vary depending on the required architecture and cache performance of the array, are optionally used.

Array 2 is associated with registers 4A and 4B. The number of bits contained in each register 4A and 4B is equal to the number of columns in the array 2. In addition, registers 4A and 4B are subdivided into sub-registers 4A ₀ through 4A ₃ and 4B ₀ through 4B ₃ , each sub-register being associated with one array of sub-arrays 6. Therefore, each sub-array 6 has a pair of sub-registers 4A and 4B associated with the sub-array.

The improved cache operation is made available according to the present invention by the availability of multiple sub-registers 4A and 4B for the array 2. A structure such that the contents of two rows of sub-arrays 6 are each cached can be referred to as a two-way set association. Of course, an additional sub-register 4 can be provided for each sub-array 6 providing n-direction set relevance (where n is a sub-register that can store the contents of the sub-array row). Is the number of). Multiple sub-registers 4A and 4B that store data from different rows of each sub-array 6 increase the likelihood of cache hits, thereby improving cache performance. Referring to FIG. 1, the sub-array 6 ₀ has rows 4 and 21 that emphasize that these two rows are stored in registers 4A and 4B. In this example, the contents of row 4 of sub-array 6 ₀ are stored in sub-register 4A ₀ , and the contents of row 21 are stored in sub-register 4B ₀ . Therefore, when the memory receives the address of the bit in row 4 or row 21 and the column address in the group associated with the sub-array 6 ₀ , a cache hit occurs and the data is cached in the memory Not only does it decode the row address during the cycle period, it can also decrypt (or write) without activating the row.

Other sub-arrays 6 ₁ to 6 ₃ may have data from different rows stored in their respective sub-registers 4A and 4B. For example, the sub-array ₍₆₁₎ to (7) information, the sub-of-stored in the array (4A _1), the sub-information, sub-line 13 of the array _(61), - a register (4B _Is stored in ₁ ). The contents of each row are stored in the sub-registers 4A or 4B, and as shown in FIG. 1, the sub-array 6 ₁ is divided into two rows of upper sub-arrays 6 ₁ . (7) may be stored in the lower sub-register 4B. Regarding the sub-array 6 ₂ , the contents of the row 4 are stored in the sub-register 4B ₂ , and as described above, the contents of the row 4 from the sub-array 6 ₀ are stored. Stored in the sub-register 4A ₀ . Thus, the contents of the same row in different sub-arrays 6 may be stored in one of the different registers 4A and 4B.

Referring to FIG. 2, there is shown the operation of memory array 10 configured in two-way set association as described above with respect to FIG. Array 10 is a rectangular memory cell, such as a dynamic memory cell, arranged in rows and columns as is known in the art. The row decoder 12 receives the row address portion of the address signal provided externally through the address line Xn, and decodes the row address to activate the row in the array 10 corresponding to the row address value. Of course, the clock circuit, the read / write control circuit, the input / output circuit, and other circuits not conventionally shown in FIG. 2 but customarily included according to the needs of the dynamic RAM can be provided.

In a conventional dRAM, the array 10 is associated with a local sense amplifier 14 where each row is local. For each memory cell of the array 10 in which a row is selected by the row decoder 12, one of the local sense amplifiers 14 can operate to sense the stored data state in a conventional manner, ( Set of local sense amplifiers 14 to implement the n-direction set association of the present invention, in the case of a read cycle or a write cycle of a column that has not been sensed in a memory cell. It cannot be used as a cache because it destroys the data state. Thus, a latch set is provided in the memory according to the present invention capable of storing n sets of data to be stored in cache mode. Moreover, such latch alignment can provide partitioning of the array 10 without subdividing the array 10, since a call to a set of cache lines can only call a portion of the data of a physical row. By using latch alignment, more memory cells can be regenerated by activating a row than is associated with a single cache segment.

Although a single line is shown as connected between the local sense amplifier 14 and the array 10, a pair of complementary bit lines are connected between each local sense amplifier 14 and a column in the array 10. . In general, as a sense amplifier senses different changes between a pair of bit lines, communication is facilitated in a modern dynamic RAM device, where one bit line is connected to a selected memory cell, of which The other bit line is connected to a dummy or reference cell. Moreover, while the other of the lines of FIG. 2 through which data are communicated is shown as a single line, the present invention is equally applicable when lines of complementary pairs are used for such communication.

The main sense amplifier 16 is used in the embodiment of FIG. 2 to implement the n-direction (in this case bidirectional) set association according to the invention. Each local sense amplifier 14 is associated with the main sense amplifier 16 (ie, 16A and 16B) and thus communicates through one of the pass gate 15 and the pass gate 18A or 18B. Pass gate 15 is controlled by a line select signal RL driven from a column address provided to the memory and selects a good cache line that is part of a row in a particular sub-array as described above with reference to FIG. . In the example shown in FIG. 2, each line is associated with each line select signal RL in the order of RL _O , RL ₁ ,... RL _n . When the associated line select signal RL is high, the pass gate 15 connected thereto is conductive to communicate the data state of the local sense amplifier 14. In the example of FIG. 2, the line select signal RL _O is related to the local sense amplifiers 14 ₀ , 14 ₁ and 14 ₂ . Thus, through the line select signal RL and the pass gate 15, partitioning of the array 10 within the sub-arrays associated with the cache line is achieved, and the entire physical row of the array 10 is decoded by the row decoder 12. Playback is performed by selecting a row by.

The two-way set relevance of the preferred memory of FIG. 2 is controlled by the set select signals SSA and SSB respectively associated with pass gates 18A and 18B. As described below, the set select signals SSA and SSB are well derived from the clock signal provided to the memory in a manner similar to the conventional column address strobe (CAS_) clock provided to the conventional dynamic RAM. When the set select signal SSA is asserted, communication of the contents of the local sense amplifier 14 to the main sense amplifier 16A, via the pass gate 18A, for the line selected by the appropriate line select signal RL is established. Is enabled. Similarly, when the set select signal SSB is asserted such that the pass gate 18B is conductive, the contents of the local sense amplifier 14 associated with the selected line cannot be communicated to the main sense amplifier 16B.

The set select signals SSA and SSB are also communicated to the column decoder 20. The column decoder 20 also receives a column address portion of the address provided to the memory shown by the address line Yn. In this embodiment, the column decoder 20 is for enabling the better of the main sense amplifiers 16 to receive data from the local sense amplifiers 14 in the selected line when the cache line is loaded, It is also intended to connect one of the main sense amplifiers 16 selected from the main sense amplifiers 16 to the data lines DA and DB in order to read or write data when a particular bit can be called.

In the embodiment of the present invention, the column decoder 20 may be functionally related to two parts, that is, the LSB part 20a and the MSB part 20b. The LSB portion 20a is a set select signal (SSA and SSB) for selecting whether the main sense amplifier 16A or 16B set is enabled to sense the data state on the line communicated through the pass gates 18A and 18B. It includes. The MSB portion 20b indicates that the bits in the cache line are the data lines (DA or DB) [data lines for the set of main sense amplifiers 16A (DA) for communication to the set data lines for the main sense amplifiers 16B (DB). Decodes a column address indicating that it is called to select one (or more than two) of the sense amplifiers 16 primary sense amplifiers. Of course, any other optional configuration of column decoder 20 for enabling a set of main sense amplifiers 16 corresponding to the selected line can be used as is known to those skilled in the art.

An alternative embodiment for controlling the operation of the memory in accordance with the state of the SSA and SSB signals is shown in FIG. In the embodiment of the present invention, the SSA and SSB signals are not communicated to the column decoder 20 but instead to the output enable circuit 21. The output enable circuit 21 also receives data lines DA and DB from the main sense amplifier 16. In response to the signal SSA and SSB being activated (selecting either set A or set B of the main sense amplifiers 16 in the selected cache line, respectively), the output enable circuit 21 is connected to the data line DA or the like. The data line DB is connected to the data line D for communication with an external circuit. An alternative embodiment of the present invention may provide improved cache decryption performance beyond that shown in FIG. 2, so that the column decoder 20 responds to the state of the signals SSA and SSB. In contrast, the signals SSA and SSB are unnecessary during the cache hit decryption operation up to the point in the memory cycle following the decoding of the column address by the column decode 20. Therefore, the cache controller connected to the memory of FIG. 9 determines whether a cache hit is generated, such as the column decoder 20 decodes the column address during the cache tag comparison operation (by the assertion of the signal from which the SSA and SSB are generated). Additional time is required to determine whether or not it appears.

Referring to FIG. 3, a layout of a valid 4M bit memory 100 used in the present invention is shown. The illustrated memory is physically oriented as 4096 rows x 1024 columns, where the memory cell comprises 32 sub-arrays 10. Each sub-array 10 has 256 physical rows and 512 physical columns of memory cells. The row decoder 12 is divided into two parts: one decoder at each end of the memory 100 selects one of the 2048 rows related thereto. Since more columns are physically than rows and are achieved in the conventional manner by providing row addresses in relation to row address strobes in terms of multiplexed address memory regeneration, one or more rows may be enabled and selected for each cycle. In this example, the row is selected by each portion of the row decoder 12, with the highest column address bit being selected such that the two selected rows are selected as input / output. Of course, the invention described herein is applicable to square arrays of rows and columns, or other rectangular configurations, in accordance with other various addressing structures.

Between each array 10 is a bank of local sense amplifiers 14. In a preferred embodiment of the invention, local sense amplifier 14 is filed on October 31, 1988, and assigned to pending US patent application No. 265,112, assigned to Texas Instruments Incorporated. Share between adjacent arrays 10 as described. The local sense amplifier 14 in this configuration, as described in US Pat. No. 4,701,885, issued Oct. 20, 1987, and assigned to Texas Instruments, Inc. Quasi-fold bit line structures may be advantageously used. Of course, other arrangements of local sense amplifiers well known to those skilled in the art may optionally be used.

Each bank of local sense amplifiers 14 is in communication with main sense amplifiers 16A and 16B as described above, with the selected communication controlled in a manner to be described below. A pair of banks of main sense amplifiers 16A and 16B are associated with eight arrays 10 in a quadrant of memory 100. As shown in FIG. 3, each bank of main sense amplifiers 16A and 16B associated with a group of eight arrays 10 is subdivided into four parts. These portions correspond to cache lines in memory 100. In this example, memory 100 has two sets for each of 16 cache lines, each set storing 128 consecutive bits from the selected row in one array 10. As described above with respect to FIG. 1, each two sets of 16 cache lines store 128 bits from different address lines, as well as other sets for the same cache line in the example of FIG. This means that adjacent cache lines can store 128 bits from the rows of different arrays 10. In the example of FIG. 3, the cache lines are grouped according to a quarter, so eight sets of each quadrant can only store data related to eight arrays 10 within a quarter. Since the selective alignment of the main sense amplifier sets 16A and 16B is known to those skilled in the art, such alignment is necessary for the placement of cache lines into the array 10 in view of the cost of complex placement and interconnection. You can change the flexibility of the assignment.

The column decoder 20 is disposed between opposite banks of the main sense amplifiers 16A and 16B related to two quarters of the array 10 on the same side of the memory 100. In the preferred embodiment of the present invention, the column decode 20 is subdivided into two parts to select one of the columns of the entire memory (if the memory 100 has a single input and a single output). Of course, other conventional decoding schemes can be used to select the columns needed for good placement. The configuration of FIG. 3 is particularly advantageous for large dynamic RAMs such as 4M bit memory.

Referring to FIG. 4, the communication of each bank of main sense amplifiers 16A and 16B and local sense amplifier 14 to a quarter of the memory 100 shown in FIG. Array 10 is not shown in FIG. 4 for clarity, but is disposed between each horizontal group of local sense amplifiers 14 as shown in FIG. In the example of FIG. 3, there are eight arrays 10 associated with banks of main sense amplifiers 16A and 16B for one quarter, with banks of main sense amplifiers 16A and 16B respectively from eight arrays. Each is divided into four cache lines that can each receive data.

Referring to FIG. 5, an address map for the 4M bit memory 100 shown in FIGS. 3 and 4 in the case of one by one (single bit input and single bit output) memory structures is shown. To address all 4M bits (2 ²² bits), 22 address bits are required, as in the conventional multiplexed dynamic RAM, the top 11 bits are the row address portion and the bottom 11 bits are the column address portion. Since the row address portion of the address signal as described above selects two rows on each side of the column decoder 20, a row is selected within each quadrant of the memory 100. As shown in FIG. The three most significant bits of the row address signals select that each of the eight arrays includes the selected row, and the eight least significant bits determine which row in the selected array 10 is selected. Regarding the column address portion of the address, the four most significant bits determine that sixteen cache lines are to be selected (i.e., in this example are selected to generate line selection signals RL0 to RL15), and that of the column address. The seven least significant bits select the good bits in the selected cache line.

Referring again to FIG. 4, the selection of a group of local sense amplifiers 14 to be communicated to the main sense amplifier is shown. The line select signals RL0 to RLn described above in connection with FIG. 2 are used to connect the contents of the local sense amplifiers in the selected line to the main sense amplifiers 16A and 16B. Since multiple groups of local sense amplifiers are used in the embodiments of the present invention, a row address must also be used to select which group of local sense amplifiers 14 is sent to the associated main sense amplifier 16. Thus, the gate of pass transistor 15 has a decoded signal (decoded signal shown in FIG. 4, such as signals for eight arrays AR0 through AR7 associated with a given cache line) and line selecting the appropriate array. It is controlled by the logical AND of the selection signals RL0 to RLn.

Due to the shared sense amplifiers shown in the schematic diagram in FIG. 3, there are no eight banks of local sense amplifiers 14 provided in a 1-1 correspondence to the eight arrays 10 in each quadrant, but instead 9 There are two physical banks. This specification is described to correspond to the memory location of the eight arrays 10 in each quadrant rather than at the physical location of the local sense amplifier 14.

In the decryption operation, if the cache line associated with the line select signal RL0 is selected by the four most significant bits of the column address, the pass transistor 15 associated with the local sense amplifier 14 is enabled for the selected row. Can be. For example, if the selected row is in the second array from the top of the quarter, the logical AND of the signals AR1 and RL0 is enabled, shown in columns 4 and 4 in FIG. 128 pass transistors 15 may be enabled that receive signals from the top associated with a second set of local sense amplifiers 14. The contents of these local sense amplifiers 14 are then placed on the main data lines 24 ₀ and 24 ₀ _ for communication to a good set of main sense amplifiers 16A and 16B for all 128 bits in the cache line. Can be.

As discussed above, signals SSA and SSB are clock signals that determine which set associated with the good cache line is to receive data from local sense amplifier 14. The clocks SSA and SSB are also used as column address strobe signals conventionally used in multiplexed address dynamic RAM when a good one of the clocks SSA and SSB is provided during the column decoding needed to select a good cache line. Can be used. Therefore, since one of the associated pass gates 18A or 18B is enabled in each column of the address cache line, the state of the main data lines 24 ₀ and 24 _{0_} is good through the main sense amplifiers 18A and 18B. Can be communicated in a set.

To achieve the decryption operation, column decoder 20 receives the column address signal and enables main sense amplifiers 16A and 16B to a good set to receive and store main data lines 24 ₀ and 24 _{0_} . You can. This function is determined from the logical operation on the four most significant column address bits with the clock signals SSA and SSB. The main sense amplifiers 16A and 16B of the unselected cache line and the main sense amplifiers 16A and 16B associated with the unselected set of the selected cache line determine the data state (uncertain state) on the associated main data line 24. An enable is required to prevent detection. Of course, such sensing can destroy embedded data.

The main sense amplifier 16 can be configured according to conventional design schemes. Examples of such sense amplifiers are described in US Pat. No. 4,716,320, issued Dec. 29, 1987, and assigned to Texas Instruments. Such sense amplifiers include active pull-up and pull-down devices that enable sensing operation, and if diavis is on-state, Accordingly latch the state of the sense amplifier. Moreover, the sense amplifier includes an equalization transistor that is turned on during precharge such that the sense node is equal at the common potential before the sense operation.

In the memory 100 according to the embodiment of the present invention, the operation of the main sense amplifier 16 depends on whether the associated cache line is selected by controlling the voltage at the pull-up, pull-down, and gate of the equalizing transistor. Accordingly controlled by the column decoder 20. For clarity, the line connecting the column decoder 20 to the main sense amplifier 16 is not shown in FIG. In the main sense amplifier 16 associated with the selected cache line and the set loaded with new data during the decode operation, the column decoder 20 turns off the pull-up and pull-down transistors in the main sense amplifier 16 and The equalization transistors can be turned on such that these main sense amplifiers 16 are precharged to receive new data states. When new data is provided on the bit lines 24 for these main sense amplifiers 16, the column decoder 20 pulls up and pulls down transistors during the appropriate cycle time to sense and latch the associated data state. Can be activated and the equalization device can be turned off.

In the main sense amplifier 16 associated with the unselected cache line and the main sense amplifier 16 associated with the unselected set of selected cache lines during the decryption operation, the column decoder 20 is active pull-up and pull-down. By keeping the -down transistor on and the equalizing transistor off, the data remains internally latched.

The column decoder 20 also connects to the data line DA or DB one of the main sense amplifiers 16A and 16B in the selected set of cache lines selected for external output to the memory 100. Selects the required bits in the selected cache line via pass transistors 22A and 22B.

In the write operation, the data line DA or DB associated with the good set can be driven to a good data state to be stored in the memory 100. After column decoding is achieved, the driven state on the data line (DA or DB) may optionally be communicated to the main sense amplifier 16A or 16B of the selected column in the selected cache line, with the data written being good in the cache line. Stored in a set. In write back operation, the entire cache line is written into the local sense amplifier 14 for the selected line, so that the pass transistor 18A or 18B is enabled when writing into the memory cell in the selected row. Therefore, the contents of main sense amplifier 16A or 16B are placed on main data lines 24 and 24_, respectively, for the selected set. The pass transistor 15 for the group of local sense amplifiers 14 in the selected cache line can be enabled during a read operation, and the local sense amplifier 14 is in a recovery operation as a conventional dynamic memory (but not in the selected line). Receive the data state on main data lines 24 and 24_ with memory cells in the selected row that receive the data state in all local sense amplifiers 14.

Other optional structures for controlling the response of the main sense amplifier 16 in the selected set of selected cache lines and retaining data already stored in the other main sense amplifiers 16 are known to those skilled in the art. have. FIG. 10 shows an alternative embodiment that is desirable to reduce the power consumption necessarily incurred in back write operations at the expense of silicon regions. In the embodiment of the present invention, the pass gates 18A and 18B are not only controlled by the SSA and SSB signals, but also by the cache line address. The pass gates 18A associated with the main sense amplifier 16 in the cache line 0 are logical AND of the clock SSA and the cache line select signal RL0, not by the clock SSA as in the example of FIG. It has gates controlled by. Similarly, pass gates 18A associated with main sense amplifier 16 in cache line 1 have gates controlled by the logic AND of clock SSA and cache line select signal RL1. Similar logic ANDs control other cache lines and pass through gate 18B with respect to clock SSB. In the control of the pass gate 18, as described above, the control of the internal transistors of the main sense amplifier 16 by the column decoder 20 becomes unnecessary. The active power can be saved with the alignment during backwrite operations, so that the main sense amplifier 16 is in the unselected cache line but is associated with the same set that is active on the selected cache line (ie, selected by the SSA or SSB signal). ) Eliminates the need to drive the full capacitive load of data line 24 during the write back operation of the selected cache line.

Referring to FIG. 6, there is shown a system using the memory 100 configured as described above with respect to FIGS. 3 and 4 and its operation. The central processing unit (CPU) 50 performs a conventional data processing operation including a memory call by an address bus including an X address portion and a Y address portion as shown in FIG. The handshaking control signals I (REQUEST and ACKNOWLEDGE) are conventional, such as asserting a signal on the line REQUEST and receiving a signal on the line (ACKNOWLEDGE) from a peripheral device receiving the signal on the REQUEST line. Is provided by the CPU to enable the peripheral device in a manner.

In the system of FIG. 6, the peripheral device is a memory controller 60. The memory controller 60 in the embodiment of the present invention not only provides the control functions well known in the art for controlling the operation of the cache memory when the memory 100 is the above-mentioned dynamic memory, but also operates the dynamic memory. Useful for controlling Therefore, the controller 60 may be configured as a block of integrated circuits for performing the functions described below, and may be a custom integrated circuit (or circuit set) for performing the functions described above. Those skilled in the art believe that the controller 60 can be configured when providing the functional requirements described below.

In order to control cache calls and operations, the controller 60 may include a cache tag comparator that compares the address portion and cache lines that specify row addresses with known cache calls and operations that would typically be stored within the cache lines of the cache memory 100. Includes features In the above embodiment, the cache line is designated by Y, or the most significant four bits of the column address (figure 5). This comparison is done in a conventional manner by the controller 60, namely the SN74ACT2151, SN74ACT2152, SN74ACT2153, and SN74ACT2154 cache tag comparators manufactured and marketed by Texas Instruments Incorporated.

Other cache control functions included in the controller 60 include a stack or some other circuit for determining that the cache line is replaced in case of cache failure. Various known techniques for making replacement decisions can be used, one of which techniques is when the circuit keeps track in the order in which the most recently used line is called to replace the cache line in case of failure. Recently used (LRU) stack method.

The preferred replacement algorithm for the system shown in FIG. 6 is described in detail below. Other techniques, including any replacement scheme, may optionally be used in a manner well known in the cache memory art. Another control function well provided by the controller 60 is a flag, commonly referred to as a dirty bit, indicating whether a write operation is performed on a particular cache line. One set of dirty bit flags may be embedded in the controller 60, where one set of bits corresponds to each of the cache lines of the memory.

Regarding the dRAM control function, the controller 60 calls the memory 100 as a constant velocity call memory in a manner similar to the SN74ALS2967, SN74ALS2968, SN74ALS6301, SN74 ALS6302, and THCT4502B dynamic memory controllers manufactured and marketed by Texas Instruments Inc. To control the operation. These memory control functions include clock signals (RASB, CAS1B and CAS2B) to the cache memory 100; And communication of signals CAS1B and CAS2B for generating the SSA and SSB set selection signals described above with respect to cache memory 100. The controller 60 also receives the read / write signal R / W from the CPU 50 and provides a corresponding signal on the line WRITEB to the cache memory 100. To achieve this goal, each of the signals described above, designated at the end by the letter B (ie, RASB, AS1B, CAS2B and WRITEB), means that a low logic level can be achieved. The controller 60 also controls the control line to select between the X address provided by the controller 60 itself and the Y address provided by the CPU 50 for assertion on the address bus connected to the cache memory 100. The control unit 51 controls the address multiplexer (MUX) 52. The functionality of the multiplexer 52 can be used within the controller 60 in a manner similar to the THCT4502B dynamic RAM controller described above. Similarly, the controller 60 is connected to the Q (output) and D (input) lines of the cache memory 100 that change depending on the state of the read / write (READ, WRITE) signals asserted by the CPU 50. The data multiplexer 54 is controlled through the control line 53 to connect the data input DATA IN and DATA OUT buses to the bidirectional DATA bus connected to the CPU 50.

Incidentally, the controller 60 determines the case where the reproduction of the memory 100 is required, and performs the function of performing the reproduction by the generation of the required signal to the memory 100 well. The above-described THCT4502B controller includes circuitry for achieving regeneration including a timer for determining when regeneration is needed. In the system of the present invention, the replay of the memory 100 is preferably made in a distributed form rather than a burst form because the cache call can be continued during the reproducing operation unless a cache failure is encountered. As is well known, this is done by periodically replaying a single row of memory, where the replay period is a specific replay period (e.g. 4 msec) and the entire memory (e.g., It is determined by dividing by the number of regeneration cycles (25 ms) required to regenerate 256. In contrast, burst regeneration is performed by continuously performing all necessary regeneration cycles at the transition of the regeneration period (e.g., 256 consecutive regeneration cycles are performed during a transition period of 4 msec). Since the likelihood of a cache failure is considerably higher during the period required to perform all replay cycles, and significantly lower during the period during which a single replay cycle is performed, the cache performance of the system shown in FIG. 6 is distributed replay, not burst regeneration. It is optimal when this is done. Thus, the controller 60 according to an embodiment of the present invention periodically generates a requirement for a single regeneration cycle, the period of which varies depending on the specific regeneration time of the memory 100 and the number of regeneration cycles for which the entire regeneration is required.

Memory 100 according to a preferred embodiment of the present invention has an on-chip counter for storing a row address corresponding to the next row to be reproduced. Upon completion of the refresh cycle, memory 100 increments the contents of the on-chip counter in proportion to the next refresh operation. An on-chip counter is included in the dynamic memory of US Pat. No. 4,207,618, issued June 10, 1980, and assigned to Texas Instruments Inc. Since such on-chip storage is good, the controller 60 does not need to provide the memory 100 with a replay address on the address bus unless a cache failure occurs, but instead continues the memory 100 in cache mode. You need to call it. Another advantage of the on-chip regenerative address counter is that the controller 60 does not have to incorporate the additional circuitry needed to store and increase the contents of the counter. The Konwledge of the actual value stored in the on-chip regeneration counter is that the oscillation time of the controller 60 is not important for the present system as long as all necessary regeneration cycles are initiated within a particular regeneration time.

In the system of FIG. 6, multiple memories 100 have Q (output) and D (input) terminals, respectively, each of which receives clock and address signals in parallel. Multiple memories of memories 100 are each associated with one line in the DATA IN and DATA OUT buses, with the number of memories 100 corresponding to the width of the data words on the DATA BUS. Those skilled in the art know that multiple banks of memory 100 may be provided, where the selection control of a good bank is achieved in a conventional manner by a decoded clock signal. This additional bank is, of course, required when a good address space is larger than the capacity of a single memory 100.

The control function of the system shown in FIG. 6 is used as a controller 60 which is a separate integrated circuit or circuit from the CPU 50 or the memory 100. Alternatively, the controller functions can be used with memory 100 as described in pending US patent application No. 175,875, assigned to Texas Instruments Inc. However, the multiple memories 100 do not duplicate the circuitry for each memory 100 when the data words are used extensively or in incidental use in multiple banks as described above, but the control functions are single for all memories. I think it is more effective to use in a circuit. Of course, increasing memory arrays by multiple banks of memory 100 not only complicates address decoding and selection, but also adversely affects system performance due to the physical lengths of the conductors connecting the memories and buses that require such systems. . The adverse effects on the specifically required application should be considered. Moreover, in alternative embodiments, the functionality of the controller 60 may be used in the same integrated circuit as the CPU 50 in good cases.

Referring to Table 1, a truth table for the operation of the example system shown in FIG. 6 is shown. Each memory 100 includes two flag bits C (cache) and R (replay) bits except for the example circuit described above with respect to FIG. The flag bit C may be in the event of a cache failure and in the 0 state during operation and the 1 state during the cache hit cycle, which is performed to rewrite and reload the cache. The flag bit R may be in the 0 state during cache hit and cache failure cycles when the replay operation is no longer in progress, and may be in the 1 state for the cache bit cycle while the replay operation is taken in a timely manner. In the embodiment of the present invention, the flag bit R may not be in one state as described later in connection with the operation of the system of FIG. 6, but the flag bit C is in the zero state. In the preferred embodiment of the present invention, the flag bits C and R affect the operation related to the clock signals RASB, CAS1B and CAS2B provided in the memory 100. In an embodiment of the invention, the flag bits C and R are generated inside the memory 100 and are not directly decrypted or set except through the cycles described herein. Of course, other alternative implementations of controlling cache and playback operations (and their status) include storing these bits in the controller 60 and providing additional lines to the memory 100 for controlling the operation of the memory. Such alternative embodiments are known to those skilled in the art. Internal storage and setting of all flag bits C and R in memory 100 may be good in terms of operational performance and integration.

Referring to FIGS. 7A-7C with Table 1, the general operation of the system shown in FIG. 6 is shown in detail. FIG. 7A shows the operation sequence of the system in the cache hit and non-playback modes. In this case, the C flag bit in memory 100 is in one state and the R flag bit in memory 100 is in zero state. In this mode, at the start of the operation, in the judging section 700 in FIG. 7A, the controller 60 determines whether a regeneration cycle is required. As is well known in the art, conventional dynamic memory controllers may be operable to determine the need for a refresh cycle to enable memory attempted to perform a refresh. These functions preferably include the function of the controller 60 as described above. When it is determined whether a refresh cycle is required, the controller 60 asserts all three signals (RASB, CAS1B and CAS2B) in the low state to all connected memories 100 as shown in FIG. (R / B, CAS1B, and CAS2B in the low states shown in FIG. 7A as 0/0/0, i.e., the rules indicating the states of the three signals asserted by the controller 60 are shown in FIGS. 7B and 7C. May continue to be applied). In response to the three signals going low in this mode, the memory 100 of the embodiment of the present invention sets its internal R flag bits to one state (process 702), and the cache hit and play mode is set to 7c. As described above with reference to the drawings (via FIGS. 7A and 7C and the connector C).

In the case where the controller 60 determines that the playback operation has not been performed, the controller 60 has four most significant bits of the Y address (hereinafter referred to as cache address) on the X address and the address pin from the CPU 50. And in an embodiment of the present invention, the controller 60 is configured to provide a multiplex (i.e., multiplex) to provide the Y address portion of the address provided by the CPU 50 (i. 52. [Process 704 of Fig. 7A] [0059] Further, as shown in the determination unit 706, the controller 60 has an address required by the CPU 50 for the cache portion of the memory 100. (I.e., cache hits) that are within (i.e., cache hits) This determination determines the X address received from the CPU 50 in the case of the memory 100 having the memory allocation of FIG. The cache shown by the four MSBs of the Y address Compared to the X address stored in the cache tag memory for a line by is performed according to a well known method of operation of the above-described cache tag comparator.

In case of cache failure, controller 60 may assert RASB, CAS1B and CAS2B all at a high logic level (ie 1/1/1 / of FIG. 7a). This may appear in the memory 100 where a cache failure occurs, the memory 100 may be placed in their 0 states within their C flag bits, respectively, and the operation of the memory in the cache failure mode may be performed ( Described below in relation to FIG. 7b). In the case of a cache hit, the controller 60 determines that the set related to the address cache line is enabled (determination unit 710 in Fig. 7a). In the memory 100 configured as described above in a two-way set related manner, the determining unit 710 may determine whether the main sense amplifier 16A or 16B can be enabled. This determination is made by a cache tag comparison operation in the case where two sets of cache tags (i.e., X addresses) can each be stored in a cache line address (i.e., four MSBs of Y addresses). As the set is required, one of CAS1B or CAS2B is asserted low by the controller 60 while the other line remains high. For example, if set A (i.e., main sense amplifier 16A) drives line CAS1B to a low level and drive line CAS2B to a high level, the call of set B is It is enabled by the low state of the controller drive line CAS2B and the high state of the line CAS1B. Then, a required set of addresses of addressed cache lines is achieved (processes 712a and 712b). The state of the line WRITEB generated by the controller 60 is enabled in the conventional manner in the read-write operation, and the data input bus (one of the data input buses connected to the D terminal of one of the memories 100). Bit] or data-output bus (one bit of the data output bus connected to the Q terminal of one of the memories 100) to the data bus connected to the CPU 50 via the control line 53 The multiplexer 54 can be controlled. At this time, the memory 100 may respond to a signal asserted in a conventional manner to achieve a read or write operation in relation to the selected set of addressed cache lines.

Also, in the case of a write call to the memory 100, the system of FIG. 6 writes only to a good set in the address cache line when the memory 100 is configured as described above, and all to the array in the memory 100. It is not written. Therefore, updating the cache line set requires a write back operation as described below. In addition, the advantages of the system shown in FIG. 6 may be provided when the memory 100 is configured to be written in its entirety. Conventional tradeoffs between overall system performance can determine that the two methods are suitable for a given application. In a preferred embodiment of the present invention, the memory 100 is configured in a write back manner.

After the good call is completed, the system can maintain the cache hit and non-replay mode and resume the comparison of the next cache address and the decision needed for replay, as shown in FIG. 7A via connector A. FIG.

Referring to FIG. 7B, the system of FIG. 6 in cache failure mode is shown. In this mode, both the C flag bit and the R flag bit of the memory 100 may be set to zero state. In the state where the system enters the cache failure mode in the connector B of FIG. 7B, the controller 60 causes all three signals (RASB, CAS1B, and CAS2B) to be asserted at a high logic level (FIG. 7A). And FIG. 7c). At this time, the memory 100 enters the conventional row precharge portion of the operation cycle in the processor 720. As described above, the system and memory 100 of the preferred embodiment of the present invention are configured in a write back manner. Thus, after determining the cache failure (decision section 706 in FIG. 7A), the controller 60 determines that the cache line and its associated set are deleted from the cache of the memory 100.

As mentioned above, there are a number of conventional ways to mediate the set of lines being deleted from the cache. The preferred method for the system shown in FIG. 6 is to use the actual four MSBs of the Y address as cache line addresses and to replace the recently used set (A) or set (B). This method allows the same Y address provided by the CPU 50 to be loaded with new data and to address the write back cache line to call the first cache (if necessary). In addition, this method does not require the additional step of translating the four MSBs of the Y address from the CPU 50 into different address values for addressing cache lines. The determination of whether a set (A) or (B) is replaced with an addressed cache line during a failure is done well by the controller 60 during row precharge of the memory in process 720.

After the controller 60 determines that the set of addressed cache lines is to be replaced with new data, the controller 60 looks up the dirty bit flag DBIT to determine whether a write operation occurs to the set to be replaced. . If no writes have occurred at all (ie, the DBIT is in the clear state), the write back operation cannot be performed and the loading of new data into the set can be performed (process 732 in FIG. 7B). If a write is performed (ie, a DBIT is set), the cache set to be replaced must first be written to a location in the array 2 of memory 100 before replacing the set with data from a different memory location. . As can be seen from the preferred embodiment of the present invention where data written to the cache set to be replaced may be lost when the write back operation is not performed, the memory 100 of the embodiment of the present invention may enter the cache hit mode. It cannot be filled in except to pass it. Thus, even without the write back operation (or, optionally, the possibility of write-through), the written data cannot be loaded into the array 2.

The write back operation selects the controller 60 which places the X address (old X address) on the address bus via the multiplexer 52, and selects the old X address provided by the controller 60 to the address bus. Is achieved by the controller multiplexer 52 via the control line 51. This old X address corresponds to the row of array 2 in memory 100 with respect to the contents of the cache set being replaced. At this time, the controller 60 asserts the RASB signal low in accordance with the conventional row address portion of the dynamic memory cycle and maintains the CAS1B and CAS2B signals high. The controller 60 then provides the multiplexer 52 with the stored values of the four MSBs of the Y addresses provided by the CPU 50 on the Y address bus (i.e., cache line address) and applies them to the address bus. Control multiplexer 52 via control line 51 to select four bits. The least significant bits, rather than four MSBs, are dont cares for this operation. However, since the Y address remains in the state provided by the CPU 50 during this period, the easiest configuration of the multiplexer 52 allows to select the full X address or the full Y address for placement on the address bus. At decision block 728, the controller 60 executes the write back operation in either set A or B in connection with driving the WRITEB signal low to achieve data writes into the array 10. It determines what is enabled to enable and asserts the appropriate one of the CAS1B or CAS2B signals based on it (respective processes 730a and 730b for sets A and B).

After completion of the write back operation or when the write back operation is unnecessary due to the DBIT in the clear state in the determination unit 722, the update of the cache may be performed. The controller 60 controls the multiplexer 52 to place the X address portion requested by the CPU 50 on the address bus. At this time, the controller 60 asserts the RASB signal to the low state, and the CAS1B and CAS2B signals to the high state (0/1/1 /), so that the memory 100 performs conventional row decoding and enabling. You can perform the operation. In process 734, controller 60 controls multiplexer 52 to place the Y address provided by CPU 52 on the address bus. This X address is the same Y address that is provided incidentally by the CPU 50. Its four MSBs determine the cache line to be updated with new information, the least significant bit of which specifies the bit to be called. Then, the controller 60 sends a new signal through the determination unit 736 in communication with the signal WRITEB enabling the decryption of the array 2 into the cache line addressed through the processes 738a and 738b. Achieve the selection of a good set (A or B) [i.e., main sense amplifier 16A or 16B] to be loaded with information, and for the appropriate CAS1B signal [for set (A)] or CAS2B signal [set (B) To achieve a subsequent drive low state. After the addressed cache set is loaded with the addressed data, a call of the bit required by the least significant bit of the Y address occurs, and the decryption operation is performed when the line WRITEB remains high, or the write operation is performed. This is done by asserting WRITEB low level after sufficient time has been allocated to the cache set to be updated. In this case, the memory 100 sets the C flag bits to 1 state in the processor 740. Controller 60 then enters cache hit mode through connector A of FIGS. 7A and 7B which asserts the RASB high.

Referring to FIG. 7C, the operation of the system shown in FIG. 6 in cache hit and play mode is shown. In this mode, the C flag bit and the R flag bit in each memory 100 are in one state. This mode is entered from the cache hit mode when the controller 60 determines that a regeneration operation is required (determination section 700 in FIG. 7A). As described above, the good reproducing operation is a distributed reproducing operation in which a single reproducing cycle that varies in accordance with the reproducing time designated in the memory 100 and the number of reproducing cycles required for the entire reproducing operation is started periodically. In addition, as described above, the memory 100 preferably has an on-chip refresh counter, so the controller 60 needs to store and forward the refresh address to the memory 100 at the start of the refresh cycle. There is no. To initiate the playback operation, the controller 60 asserts all three signals (RASB, CAS1B and CAS2B) to the low level (see operation portion 702 of FIG. 7A), so that the RASB is in an active low level state. Keep it. The signals CAS1B and CAS2B are then decoded, enabled, and detected in a conventional manner in dynamic RAM to reproduce the contents in the rows of the memory 100 corresponding to the contents of the on-chip reproducing address counter. And is driven high by the controller 60 (operation unit 750) to initiate a recovery operation.

In an embodiment of the invention, a local sense amplifier 14 of memory 100 is used to sense and recover the sensed data state in a selected row of the selected array 10, and cache data is sent to the local sense amplifier 14; Since it is stored in the main sense amplifier 16 that is buffered from, it may be possible for the cache operation to continue for a period of time during which the memory 100 is in a regeneration operation. Therefore, after causing the controller 60 to start the playback operation by placing the contents of the playback counter on the address bus, the controller 60 can start the next start call operation.

Therefore, the cache call described above with respect to FIG. 7A can proceed as long as the system continues to have a cache hit. In conventional dynamic RAM, it is contemplated that the refresh cycle may be taken for about 150-200 nsec, and that cache call cycles may be achieved at higher speeds, eg, about 25-50 nsec. Therefore, multiple cache calls are made during a period in which rows in each memory 100 are played back simultaneously. However, the replay operation is not continually distributed in case of cache failure, because the discrepancy in the local sense amplifier 14 is lost when the row is selected as an update or write back operation during the period in which the replay operation of the different rows is performed. Because it occurs. In the embodiment of the present invention as described below, the system of FIG. 6 may lock-out a cache failure (i.e., row) call during a playback operation.

The process 752 of FIG. 7C receives a new cache address (i.e., four MSBs of X address and Y address) from the CPU 50 after the playback is enabled by the controller, and the CPU ( Control multiplexer 52 such that the Y address portion of the address provided by 50 is disposed on the address bus. In the same manner as the cache hit mode described above, the controller 60 performs cache tag comparison in the determination unit 754 to determine whether a cache hit or a cache failure has occurred. In case of cache failure, the controller 60 continues to drive the RASB signal to the low level state until the time required for the reproducing operation has elapsed, and continues to drive the CAS1B and CAS2B signals to the high level state (reader ( 756)]. As is well known, dynamic memory specifies a refresh cycle time for a period during which a suitable signal can remain active. Upon completion of the refresh cycle time, the controller 60 drives the RASB signal to a high level state. Although the assertion of the RASB signal to the high level state is shown as a decision block (blocks 756 and 768 of FIG. 7C) to facilitate explanation, the controller 60 indicates that the end of the playback operation is independent of the cache call. In the case asserts the RASB signal to a high level state at the end of the refresh cycle time in the same way as it involves the cache hit or fail operation.

Upon receiving the RASB signal in the high level state indicating the end of the reproduction operation, the memory 100 clears each of the R flag bits to 0 state to indicate that the reproduction operation is completed (process 758). When a cache failure is detected by the controller 60 at the determination unit 754, the memory 100 clears each of the C flag bits to zero (process 760), and the cache failure mode described above with reference to FIG. 7b. May be entered via the connector (B).

When a cache hit is detected by the controller 60 at the determination unit 754, the controller 60 may determine that a set (A or B) for the cache line determined by the four MSBs of the Y address is called. (Via the determination unit 762). In the same manner as in the cache hit and non-regeneration mode, the controller 60 selects the CAS1B signal or CAS2B signal (at high level) to enable a good set of main sense amplifiers 16A or 16B to the addressed cache line. Can be asserted to a low level state. Decryption or invocation into the preferred cache set is accomplished in processes 764a and 764b in the same manner as described above with respect to FIG. 7A.

As discussed above in connection with cache failure, the controller 60 determines whether the playback operation has time to complete. Until the end of the required cycle time, the controller 60 keeps the RASB in a low level state (see the judgment section 768 for explanation), the R flag maintains the set state in the memory 100, and the operation control The process then returns to process 752 where the cache address is received by the controller 60, the Y portion placed on the address bus, and the cache address that compares the stored cache tag again to indicate when a match occurs.

In describing the required regeneration operation cycle time, the controller 60 may simultaneously appear in the memory 100 by asserting all three signals (RASB, CAS1B and CAS2B) to a high logic level. Each memory 100 may reset the R flag bit to zero and enter the cache hit mode described above with respect to FIG. 7A via connector A. FIG. In this manner, subsequent cache failures allow the system to immediately enter cache failure mode without incurring the closure time required to complete the playback operation.

In this manner, the system of FIG. 6 operates in the same way that the memory 100 configured as described above with respect to FIGS. 1-5 acts as a cache memory and a main memory. n-direction set relevance (in the embodiment of the present invention, n = 2) provides the ability of an improved cache hit rate to improve overall system performance. Embodiments of the present invention that describe system operations include operations in cache hit mode, followed by write back and set load operations in cache failure mode, and operations in cache hit and play mode. 7A-7C are flow charts illustrating the operation of the system regardless of the particular order.

For clarity, the specific order of operations will be described with reference to the timing diagram shown in FIG. 8 shows a timing signal generated (or asserted) by one of the memories 100. This exemplary sequence includes the decryption and write cycles of cache hit and non-playback modes, the cache failure writeback and set load, and the cycles of cache hit and playback modes.

Upon initiating the cache hit and non-playback modes, the address bus indicates that a new Y address is provided by the controller 60 as described above. In the mode as described above, the C flag bit is in one level state, and the R flag bit is in zero level state. In this mode, as long as the hit continues, the controller 60 keeps the line RABS at a high logic level. Since the first cycle of FIG. 8 is in the read operation for the set B of cache lines, line CAS1B is asserted to a high level and CAS2B remains in a low level. In response to these signals, the memory 100 can provide the data state (in this case, one data state) of the cell addressed at the Q terminal at a similar timing as in the case of a call from a conventional static column decode memory. . An example of dynamic memory with static thermal decode call capability is the TMS4C10271 Mbit dRAM manufactured and marketed by Texas Instruments.

The second cycle shown in FIG. 8 is a write operation into one bit in the set A of the cache lines addressed by the new Y address provided on the address. In this cycle, lines CAS1B and WRITEB are asserted in a low logic level state, and lines CAS2B are asserted in a high logic level state, writing to the addressed bits in set A of addressed cache lines. Data to be supplied is provided from the CPU 50 via the multiplexer 54 to the D terminal of the memory 100 (FIG. 6). As described above, since the memory 100 is constructed in accordance with the write back structure, data is not written into the array 10 of the memory 100 by this operation, but only written into the cache line set.

In the cache write operation shown in FIG. 8, a new Y address (called Ymiss in FIG. 8) appears on the address, so that the Y address is provided to the memory 100 when a cache hit occurs. However, in this order, controller 60 determines whether the X address provided by CPU 50 matches the X address associated with cache line address Y (i.e., four MSBs in the Y address portion) that causes a cache failure. Determine whether or not. As the case of cache failure is shown in FIG. 8, the lines (RASB, CAS1B and CAS2B) are all asserted to a high state causing the memory 100 to reset the C flag bit to zero.

For the sake of understanding, since the dirty bit in the controller 60 is a set indicating that the cache set to be replaced is written, its contents may be different from that stored in the corresponding position in the memory array. To complete the write back operation, the controller 60 causes the X address associated with the cache set to be replaced by the address bus, as shown in FIG. 8, and asserts the line RASB to the active low logic level. This allows memory 100 to enter the row address decode and enable portion in accordance with conventional multiplex call dynamic memory cycles. The controller 60 then places Y address Y (at least four MSBs) on the address bus in this case to select the cache line to be replaced with the same cache line addressed by the CPU 50. In addition, controller 60 asserts line CAS1B to a low logic level, and line CA2B remains high, which is an addressed cache written into array 10 in the row selected by the old X address. Indicates a set (A) of lines. In this example, the set A is selected for replacement by the controller 60 by detecting that the set A or set B for Y's cache line has recently been called. The structure as described above simply provides for the write back and update operations of the cache without requiring an address translation to be performed. Also, line WRITEB is asserted to an active low level state to enable the write back operation. The D or Q terminal becomes inactive. That is, the data output is high impedance and the data input is dont care.

Following a write subsequent cycle, the memory 100 is for entering the update mode when the cache line (i.e., Y) associated with the address asserted by the CPU 50 is loaded in the good set. Therefore, controller 60 enables multiplexer 52 to place the X address (i.e., the new X address) required by CPU 50 on the address bus, and puts line (RASB) to a low logic level. By asserting, the conventional row address decode and row enable portion of the cycle is resumed. Then, the controller 60 places the Y address portion (i.e., the value Y) of the address requested by the CPU 50 on the address bus, so that the cache lines associated with the four MSBs are selected, and the line CSA1B is Configured to a low logic level, line CAS2B is driven to a high logic level so that main sense amplifier 16A (i.e., set A) associated with the address cache line is loaded with new data. After the new data is loaded into the set A of addressed cache lines, a good decryption operation is performed, in which a bit is selected in the cache line corresponding to the least significant bit of address Y and thus the data state (in this case, 1). It is driven by the Q terminal of the memory 100. In response to the line configured as high (RASB) at the end of this cycle, the C flag bit in memory 100 is set to one state indicating that the operation is transferred to cache hit mode.

In the flowchart of FIG. 8, the next cycle is a conventional cache hit and non-replay cycle, where a new Y address is placed on the address bus and the call is made with the transferred bits [in this case, a set of addressed cache lines B Decrypt operation causes zero at the Q terminal. However, in a subsequent sense, the controller 60 indicates that a regeneration operation is required by asserting the line RASB to a low level and asserting the lines CAS1B and CAS2B to a high level. In response, the memory 100 sets the R flag bits to the 1 state, respectively, but the cache operation is [decryption operation for each set of cache lines A for the new Y address and set of cache lines B As before, the RASB remains low level until the playback operation is completed. As discussed above, the on-chip regeneration address counter is used by the memory 100 to activate a row of regeneration memory arrays using the local sense amplifier 14. In response to the RASB going high and the lines CAS1B and CAS2B going high, the memory 100 resets the R flag bits to zero, respectively, and cache hits and refreshes in cache hit and non-play mode. Exit the mode.

The memory 100 and system of FIG. 6 constructed in accordance with the present invention provides significant advantages in terms of memory system performance and efficiency. Multi-directional set-related on-chip caches with disassembly of the array improve the cache hit rate and the efficiency of backwrite and update operations. Moreover, the regeneration of the memory is done in a fairly obvious manner while the cache call is retained in the chip's borders with the main memory and cache.

Further, future system architectures are advantageous for the memory structure described herein and claimed in the appended claims. Moreover, the scale of integration has tended to increase the deployment of more functions on a single chip, and includes wafer-scale integration. Examples of future architectures include Patterson et al., Design Considerations for Single-Chip Computers of Future, IEEE Trans. on Computers, Vol. C-29, No. 2 (IEEE, 1980, 2), pages 108-115. This example is described in the use of dynamic and static memories as local memories for one million transistor integrated circuits. The present invention does not require dynamic memory cells and static memory cells, but rather integrates wafers to provide an advantage in memory performance in which a single type of memory cell (e.g., a dynamic RAM cell) is fabricated on the same wafer. It is used for super-scale integration that entails. Moreover, the system of FIG. 6 performs cache memory control and main memory control to achieve the efficient performance of two functions in a single chip or wafer-scale integration application, as well as the single control block achieves the benefit of improved performance. To do it. It is also contemplated that the present invention is particularly advantageous for the application of multiprocessor systems as described above where multiple processors are integrated on a wafer scale.

Preferred embodiments of the present invention have been described with reference to a memory configured as a dynamic decryption / write constant velocity call memory. The present invention believes that there is a particularly obvious advantage to such a memory, but the present invention can also be obtained from a static decryption / write memory. Moreover, various modifications of the detailed description of the embodiments of the present invention and further embodiments of the present invention can be made by those skilled in the art. Such modifications and further embodiments can be made without departing from the spirit of the invention within the scope of the appended claims.

Claims (18)

A memory device of the type having a plurality of memory cells arranged in rows and columns, comprising: a row decoder for selecting a plurality of memory cells in a row in response to a row address signal, the data state of the memory cells selected by the row decoder A plurality of sense amplifiers for respectively sensing a plurality of sense amplifiers, a first set of latches each associated with one of the cell sense amplifiers, and a second set of latches each associated with one of the sense amplifiers, Each of the plurality of sense attenuators is associated with a latch in the first set and the second set, Connecting each of the plurality of sense amplifiers to an associated latch of the first set in response to a first set select signal, and each of the plurality of sense amplifiers in the second set to respond to a second set select signal. Means for connecting to an associated latch, and a column decoder for selecting one of the first set or the second set for external access responsive to a column address signal. 2. The plurality of sense amplifiers of claim 1, wherein the plurality of sense amplifiers comprise first and second lines of sense amplifiers associated with first and second column groups of the plurality of memory cells, respectively, and within the first and second column groups. And a memory cell is selected by the row decoder. 3. The method of claim 2, wherein the first and second sets of latches comprise first and second lines of latches associated with the first and second lines of sense amplifiers in the first and second sets, respectively, Connect the first line of an amplifier to the first line of latches in the first set responsive to the column address signal and the first set select signal, and connect the first line of a sense amplifier to the column address signal And means for connecting the first line of latches in the second set responsive to the second set select signal, and the second line of a sense amplifier responsive to the column address signal and the first set select signal. Connect the second line of the sense amplifier to the second line of latches in the first set, the second line of the sense amplifier being in response to the column address signal and the second set select signal. And means for connecting to said second line of latches. 4. The memory device of claim 3, wherein each sense amplifier corresponds to a single column of the plurality of memory cells. 5. The method of claim 4 wherein the first value of the column address signal portion corresponds to a column associated with the first line of a sense amplifier and the second value of the column address signal portion corresponds to a column associated with the second line of a sense amplifier. And a memory device. 4. The method of claim 3, wherein said means for connecting said first line of sense amplifiers to said first and second sets of latches and connecting said second line of sense amplifiers to said first and second sets of latches. Wherein said means for each comprises a pass transistor. 2. The memory device of claim 1, wherein said memory cell is a read / write memory cell. 2. The memory device of claim 1, wherein the memory cell is a read-only memory cell. 2. The method of claim 1, wherein the plurality of sense amplifiers comprise first and second sense amplifier groups associated with first and second row groups of the plurality of memory cells, wherein each column of the plurality of memory cells is And a sense amplifier in the first group and a sense amplifier in the second group. 10. The local data line of claim 9, further comprising: a local data line each associated with a column of said plurality of memory cells, said local data line responsive to said row address signal selecting said first sense amplifier group any row within said first row group; Means for connecting to the local data line responsive to the row address signal selecting any row in the second row group and means for connecting the group of second sense attenuators. Memory device. 11. The method of claim 10, wherein each of said first and second sense amplifier groups further comprises first and second lines of sense amplifiers respectively associated with groups of first and second columns of said plurality of memory cells. And a memory device. 12. The first and second sets of latches of claim 11, wherein the first and second sets of latches comprise lines of first and second latches associated with the first and second sense amplifier lines in the first and second groups. Connect the local data line associated with the line of the first column to a line of the first latch in the first set responsive to the column address signal and the first set select signal, the sensing included in a second set; Means for connecting a first line of an amplifier to a first line of said latch in said second set responsive to said column address signal and said second set select signal, and said local data line associated with a second line of said column; Connect a second line of the latch in the first set responsive to the column address signal and the first set select signal, and connect a second line of the sense amplifier to the column address signal And means for connecting to a second line of the latch in the second set responsive to the second set select signal. 13. The apparatus of claim 12, wherein the means for connecting a first group of sense amplifiers selects a row within the first group of the first line of the sense amplifiers in the first group. The row address and the second for connecting a second line of the sense amplifier in the first group to select a row within the first group in response to the column address selecting one line; And in response to said column address selecting a line, said means for connecting said second group of sense amplifiers to connect said first line of sense amplifiers in said second group within said second group. Local data associated therewith in response to the row address for selecting a row and the column address for selecting a first line in A local data line associated with said line in response to said row address selecting said row in said second group and said second address of said sense amplifier in said second group and said column address selecting said second line And a memory device. A data processing device capable of performing an operation according to the data, providing a memory address, and receiving data, a primary array arranged in rows and columns, and a first array for storing data corresponding to other rows in the same column of the array; Having a second cache set, connected to an address bus to receive a memory address, and connected to and providing an address to the data processing device to receive a memory address connected to the data processing device to provide data A memory controller connected to an address bus, wherein the memory controller determines whether a memory address provided by the data processing apparatus corresponds to data stored in the first or second cache set of the memory. The memory address provided by the Providing an address to the address bus for delivering data stored at a location of a first cache set corresponding to the provided address to the data processing device, and for providing a first set select signal to the memory; Whether it corresponds to a location in the first cache set, The memory address provided by the data processing apparatus provides an address to the address bus such that the memory delivers data stored at a location of a second cache set corresponding to the provided address to the data processing apparatus, and a second set Whether the memory address corresponds to a location in the second cache set of the memory for providing a selection signal to the memory, and the memory address provided by the data processing apparatus is such that the memory corresponds to the memory address. Whether to correspond to data stored in said first or second cache set of said memory for providing an address to said address bus and delivering a control signal to said memory for delivering data stored at a location of said data processing device to said data bus. Characterized by determining Data processing system. 15. The data processing system of claim 14, wherein the memory is a read / write memory, and wherein the memory controller provides a read / write control signal to the corresponding memory for the requested operation. 16. The memory device of claim 15, wherein the memory is a dynamic read / write memory, and the memory controller determines whether a playback operation is necessary, and transmits a control signal to the memory to perform playback in response to determining that a playback operation is required. A data processing system further comprising. 15. The apparatus of claim 14, wherein the first and second cache sets comprise first and second cache lines, respectively, and wherein the address portion provided by the data processing device is any one of the first or second cache lines. A data processing system characterized by determining whether it should be selected. 18. The system of claim 17, wherein the memory controller is a row stored in the first cache line of the first cache set, a row stored in the second cache line of the first cache set, and the first cache of the second cache set. Storing a memory address portion corresponding to a row stored in a line, and a row stored in the second cache line of the second cache set, wherein the memory address provided by the data processing apparatus compares the memory address portion with the stored portion Determining whether it corresponds to data stored in said first or second cache set of said memory.