WO1998003918A1

WO1998003918A1 - Cache memory device and information processing system

Info

Publication number: WO1998003918A1
Application number: PCT/JP1996/002020
Authority: WO
Inventors: Atsushi Nakajima; Masabumi Shibata
Original assignee: Hitachi, Ltd.
Priority date: 1996-07-19
Filing date: 1996-07-19
Publication date: 1998-01-29

Abstract

In a highly associative cache memory device, a memory such as an SRAM, which is accessed through row access and column access is used as a data memory and the data of all ways of the same set number are arranged in the same row. A cache control circuit (5) executes the row access to the data memory before a cache hit is judged. When a cache hit is judged to have occurred, column access is executed by using a hit way number. When a cache miss is judged to have occurred and write back is performed, column access is executed by using a replace way number. When a cache miss is judged to have occurred and no write back is performed, column access is suspended. Therefore, when an SDRAM chip is used as a data memory externally installed, the access latency and the memory bank busy time are shortened and the number of pins of an LSI which receives data is decreased. Since the row access becomes effective for reading out write back data even when a cache miss occurs, the efficiency of use of the data memory bank does not drop.

Description

Cache memory device and information processing system

Technical field

The present invention relates to a cache memory device in an information processing system, and more particularly to a cache memory device using a DRAM such as a DRAM (Synchronous Dynamic Random Access Memory) and an information processing system using the same. About. book

Background art

In computer systems, in order to improve the processing performance of a processor, it is common practice to provide a cache memory consisting of a small-capacity high-speed memory between a high-speed processor and a main storage device that is slower than the processor. By storing part of the data in the main memory in the cache memory and accessing the cache memory instead of the main memory, the apparent access speed from the processor to the main memory can be increased. In general, the design goals for cache memory are to increase the hit rate and reduce access latency. In order to improve the hit rate, it is necessary to increase the capacity of the cache memory and increase the associativeness. This has a trade-off relationship with the access latency. Conventionally, access latencies have been reduced by using SRAM devices for data memory. However, there is a limit to increasing the capacity of SRAM devices in terms of integration. By using a DRAM such as a synchronous DRAM (hereinafter referred to as S DRAM) as a data memory, it is possible to achieve a larger capacity than ever, but there is a problem of an increase in latency and an increase in the busy time of a memory bank. In particular, the problem is that the latency of row access is large. Conventionally, in a memory system using a DRAM, as described in Japanese Patent Application Laid-Open No. 62-82592, a method of hiding the latency of row access by utilizing the edge mode function has been devised.

On the other hand, when the data memory is realized by an external memory chip, the associativity of the cache memory and the data are received, and a trade-off occurs between the SI hin and the data. Kojitsu Electronics, from January 30, 1995 (No. 627) to 97 An article on page 108 describes a method of saving LSI pins by reading only data in one way at a time in a 2-way set-associative cache using sink-mouth eggplant SRAM.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce access latency while reducing the number of bins of an LSI for receiving data when a memory cell with an external memory is used in a highly associative cache memory device, and to provide a busy memory bank. The goal is to reduce time. Disclosure of the invention

[Means for solving the problem]

In order to solve the above problems, in the present invention, in a multiple associative cache memory device using SDRAM as a data memory, data of all ways having the same set number is arranged in the same row address of the DRAM. At the time of cache access, a row access to the data memory is executed before the cache hit determination is determined, and when the cache hit determination is made in the cache hit determination, the number of the hit way is used. When a column miss of the data memory is performed, and a cache miss is determined in the cache hit determination, and it is necessary to write back the way to be re-raced to the memory, the number of the way to be replaced is Performs a column access to the data memory, and executes the cache A means is provided for interrupting column access to the data memory when cache miss is determined in the hit determination and the rib race target way does not need to be knocked in the memory.

[Action]

According to the present invention, it is possible to configure a cache memory device having a large capacity, a high associativity, and a short access latency while using an external SDRAM chip as a data memory and reducing the number of pins of an LSI for receiving data. It becomes possible. By performing data memory row access prior to the determination of the cache hit determination result, cache access latency can be reduced. When the cache hit judgment result is determined, the hitway and the refresh way can be read only by changing the column address. Therefore, even in the case of a cache miss, the preceding access to the data memory bank is not wasted. Therefore, In a system with a high cache memory dirty ratio (the probability that the data stored in the cache is updated and differs from the contents in the memory), the use efficiency of the data memory bank is reduced as compared to the case where the preceding row access is not performed. Access latency can be reduced without lowering it. If it is not necessary to write back the rib raceway due to a cache miss, the preceding row access of the data memory bank will be wasted, creating an unnecessary busy hour for the bank. However, by providing a plurality of data memory banks as shown in the following embodiments, it is possible to reduce the damage caused by the bank busy time when the subsequent cache access is unnecessary. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a configuration diagram of a computer system including a cache memory device according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating a detailed configuration of an address selector. Also, FIG. 3 is a time chart when the bank 0 data memory 15 is read, FIG. 4 is a time chart when the bank 0 data memory 15 is written, and FIG. 5 is a bank 0 data chart. It is. 6 FIG, 7 showing a detailed configuration of Adoresuratchi in FIG. 1 is a diagram showing a detailed configuration of the tag memory entry, 8 ^off: there when determining cache hits in load request from the mouth processor 1 Les, Is a time chart of bank 0 data memory 15 read at write back. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration diagram of a computer system including a cache memory device according to one embodiment of the present invention. In FIG. 1, 1 is a processor (CPU), 2 is a main memory, 3 is a cache system, 200 is a processor bus connecting processor 1 and cache system 3, and 300 is a main memory 2 and a cache. This is a memory bus that connects to system 3. The cache system 3 includes a tag memory 4, a cache control circuit 5, an address selector 7, an address latch 8, a data buffer 12, a processor bus interface 13, a memory bus interface 14, and a bank 0 data memory 15. And bank 1 data memory 16. Further, the bank 0 data memory 15 and the bank 1 data memory 16 have an SDRAM control circuit 6 and a DRAM mat 11, respectively.

In this embodiment, the cache capacity is 16 MB, and the associativity is a 4-way setter. Socially, the line size (block size) is 64 bytes, the number of data memory banks is 2, 64 bytes interleaved, and each DRAM mat 11 has a configuration of 2048 rows x 2556 columns XI 6 bytes, the capacity of the main memory 2 is 2 Gbytes, and the data transfer unit between the processor 1 and the cache system 3 and between the cache system 3 and the main memory 2 is 64 bytes. .

In the following, 16 words are double words (DW) and 4 double words in 64 bytes are double word 0, double word 1, and double word 2 in ascending order of double word address. , Defined as doubleword 3.

The processor 1 has means for sending a mouth address on the processor bus 200 and requesting the cache system 3 to load data. Further, the processor 1 has a means for transmitting a storage address and a storage data on the processor bus 200 and requesting the cache system 3 for a data storage. Since the data load requesting means and the data requesting means of the processor 1 are not an essential part of the present invention, they are not shown and their detailed description is omitted.

When the processor 1 issues a data load request, the processor bus interface 13 sets the mouth address to the address latch 8, and then loads the load data set in the data buffer 12 via the processor bus 200. To the processor 1 When the processor 1 issues a data store request, the processor bus interface 13 sets the store address in the address latch 8 and then sets the store data in the data buffer 12.

In response to a load request from the cache system 3, the main storage device 2 reads the data from the memory using the memory address received via the memory bus 300, and reads the load data together with the load address. It has means for sending to the cache system 3 via the memory bus 300. In addition, the main storage device 2 stores the store data received via the memory bus 300 in response to a store request from the cache system 3, and stores the store data also received via the memory bus 300. It has a means of memory restoration using dresses.

The memory bus interface 14 sends the mouth address received from the cache control circuit 5 to the main storage device 2 via the memory bus 300. When the load data and the load address are sent from the main memory 2, the memory bus interface 14 sets the load address to the address latch 8 and stores the read data in the data buffer 12. Set.

Also, the memory bus interface 14 stores the address from the cache control circuit 5 and the storage data from the data buffer 12 into the memory bus 300. (Not shown) for sending to the main storage device 2 via

The bank 0 data memory 15 and the bank 1 data memory 16 are composed of SDRAM (Synchronus DRAM) that operates at high speed in synchronization with an external clock. Hereinafter, the data arrangement on the DRAM mat 11 will be described.

Bank 0 data memory 15 An even set number is assigned to 5, Bank 1 data memory

16 is assigned an odd set number. In each bank, 16 double pads belonging to 4 ways of the same set number are assigned to 16 consecutive column addresses of the same address. At this time, four double cards belonging to the same way are arranged in a continuous column address. Arrange them in ascending order of double-address in the direction in which the column address increases.

The order of way queries is arbitrary, but in the present embodiment, they are arranged in ascending order of way numbers in the direction in which the column address increases.

Thus, as shown in FIG. 1, the position of the port number i of the bank 0 data memory 15 and the power ram numbers 16 j, 16 j + l, l 6 j + 2, 16 j + 3 The double numbers 0, 1, 2, and 3 belonging to the set 0 of the set number (16i + j) X2 are assigned. In addition, the set number (16i + j) is placed at the position of the port number i of bank 0 data memory 15 and the column number 16j + 4, 16j + 8, 16j + 12 ) Allocate double word 0, which belongs to X 1, 2, 3 respectively. In the case of the present embodiment, 1 is a natural number from 0 to 2047, and j is a natural number from 0 to 15.

FIG. 2 shows the detailed configuration of the address selector 7.

The bit width of the output signal 112 of the address selector 7 is 11 bits, which are described as Z10 to Z0. Z 10 is the MSB (most significant bit) and Z 0 is the LSB (least significant bit). The address bits 21 to 7 transmitted from the address latch 8 via the signal lines 104 and 102 are described as A21 to A7. Way decode bits 1 and 0 sent from the cache control circuit via the signal line 107 are described as Wl and WO. When the value of the signal line 109 is a logical value 1, the values A 21 to A 11 on the signal line 104 are output to the output signal line 1 1 ′ λ. If the value of signal line 109 is logical value 0, the output signal lines 1 1 2 Z 1 0 to Z 8 will be logical value 0, Z 7 to Z 4 will be the values A 10 to A 7 on signal line 102, Z3 to Z2 output values on signal line 107 from W1 to WO, and Z1 output from Z0 output logical value 0.

The SDRAM control circuit 6 sends the data from the cache control circuit 5 via the symbol line 110 and the signal line 111 to the end by the instruction of the SDRAM access command. It has the function of performing row access and column access of the DRAM mat 11 using the SDRAM access address sent from the dress selector 7 via the signal line 112. SDRAM control circuit 6 operates in synchronization with an externally applied clock. The SDRAM control circuit 6 has a function of holding the burst length set at the time of initialization and automatically incrementing the column address in the case of column access. In this embodiment, it is assumed that the burst length is set to 4.

FIG. 3 shows a time chart when the bank 0 data memory 15 is read. At time t0, an active command is sent via signal line 110, and row address i is sent via signal line 112. This causes the SDRAM control circuit 6 to start accessing the row number i.

At time t1, a read command is sent via the signal line 110 and a column address 16j is sent via the signal line 112. As a result, the SDRAM control circuit 6 starts reading the column numbers 16 j, 16 j +1, 16 j +2, and 16 j +3. The minimum time interval between time ij t 0 and time t 1 is called an active column command delay.

At times t2, t3, t4, t5, double words 0, 1, 2, and 3 belonging to way 0 of set number (16i + j) X2 are read on signal line 1 13 respectively. Will be issued. The time interval from the time t1 to the time t2 is called the column access delay. The time intervals between times t2 and t3, between times t3 and t4, between times t4 and t5, and between times 5 and t6 are as follows: Is the cycle time of the clock given to After time t6, the data on ίcode line 1 1 3 is not guaranteed.

To end data access on row number i, a precharge command is sent on signal lines 113. Until the precharge command is sent, column access to data on row number i can be performed. FIG. 3 shows a case where the data access on the port number i ends at t6. In this embodiment, the earliest and Arichiya one Jikoman de at _t 4 is to be issued.

An active command can be issued after a time interval called a bricharge-active command delay has elapsed after the british command is issued. In FIG. 3, after time t 13, (Send an active command on code line 1 13.

Figure 4 shows the time chart for writing to the bank 0 data memory 15. At time t7, an active command is sent via signal line 1 I0, Row dress i is sent via 1 2. This causes the SDRAM control circuit 6 to start accessing the row number i.

At time t8, a write command is sent via signal line 110, and a column address 16j is sent via signal line 112. In addition, data A, B, C, and D are transmitted via signal lines 113 at times t8, t9, t10, and t11, respectively. As a result, the SDRAM control circuit 6 starts writing the data A, B, C, and D to the positions of the column numbers 16 j, 16 j +1, 16 j +2, and 16 j +3, respectively. . The minimum time interval from time t7 to time t8 is the active one column command delay. The time interval between the times t8 and t9, between the times t9 and t10, between the times t10 and t11, and between the times 11 and t12 is SDR

This is the cycle time of the clock supplied to the AM control circuit 6.

When terminating data access on row number i, a precharge command is sent on signal lines 113. Until the precharge command is sent, column access to data on row number i can be performed. FIG. 4 shows a case where the data access on row number i ends at t12. In this embodiment, the precharge command can be issued at t14 at the earliest.

After the precharge command is issued, the active command can be issued after the elapse of the precharge-active command delay time. In FIG. 4, after time t15, an active command can be sent on the signal line 113. FIG. 5 shows a time chart when only the row access is performed to the bank 0 data memory 15 and the column access is not performed.

At time t16, an active command is sent via the signal line 110, and the signal line

The row address 送 is sent via 1 1 2. This makes the SDRAM control circuit

6 starts accessing row number i.

At the earliest, at time t17, a precharge command can be issued. The time interval between times t16 and t17 is called an active precharge command delay.

After time t18, an active command can be sent on signal line 113. The time interval between times t17 and t18 is a precharge-active command delay.

FIG. 6 shows the detailed configuration of the address latch 3.

Address latch 3 has a bit width of 26, where bit 6 is the least significant bit (LSB) and bit 31 is the most significant bit (MSB).

The 4-bit value from address latch bit 7 to bit I0 is Connected to the address selector 7 via the signal line 102 as a part of the AM column address. The 16-bit value from bit 6 to bit 21 of the address latch is connected to tag memory 4 via signal line 103 as a set number. The value of 11 bits from bit 11 to bit 21 of the address latch is transmitted to the address selector 7 via the signal line 104 as the address of the SDRAM. 26 bits from bit 6 to bit 31 of the address latch are connected to the cache control circuit 5 via the signal line 105.

The tag memory 4 has a 4-way configuration, and the number of entries is 64K. The access entry of the tag memory 4 is specified using the value on the signal line 103. The read data and the write data of the tag memory 4 are connected to the cache control circuit 5 via the signal line 106. The cache control circuit 5 has means for reading from and writing to the tag memory 4.

FIG. 7 shows a detailed configuration of the entry of the tag memory 4.

Reference numeral 401 denotes an address field, which holds 10 bits from bit 31 to bit 22 of the address. 402 is a memory load flag. When the logical value is 1, it indicates that a load request to the memory for the address indicated by this entry is being made. 403 is a duty flag. When the logical value is 1, it indicates that a store has been issued from processor 1 for the address indicated by this entry (the memory and the value are different = duty). .

The cache control circuit 5 performs a cache hit determination or a refresh race determination when a load request or a store request is sent from the processor 1 or when a cached data is sent from the main storage device 2.

When a load request or a store request from the processor 1 or load data is sent from the main storage device 2 and an address is set in the address latch 8, the cache control circuit 5 Selects the data memory bank to be accessed from the value of address bit 6 sent via. Next, using the values of the address bits 21 to 11 sent via the signal line 105, it is determined whether or not to perform row access to the selected bank. In the selected bank, if an active command has been issued to the same port number as the value of address bits 21 and 11 and precharge has not been issued (Case 1), the row is deactivated. It is determined that access is unnecessary. In cases other than Case 1, it is determined that row access is required, a logical value 0 is sent on the signal line 109, and an active command is sent on one of the signal lines 110, 111 according to the selected bank number. . Next, a detailed procedure of the cache hit determination will be described.

The cache control circuit 5 reads the bits 31 to 22 of the address latch 8 sent via the signal line 105 and the read data of the tag memory 4 sent via the signal line 106. Is used to make a cache hit determination.

The logic of the cache hit determination differs between when a load request or a store request is sent from the processor 1 and when the load data is sent from the main storage device 2.

1) When a mouth request or store request is sent from processor 1

The value of bits 31 to 22 of the address latch 8 transmitted via the signal line 105 and the address field 401 of the read data of the tag memory 4 transmitted via the signal line 105 are weighed. The result of the comparison is ANDed with the inverted value of the memory load flag 402 for each way. If there is a way with a logical value of 1 as a result of AND, it is a cache hit and this way is a hitway. If there is no way for which the logical value of the result of A N D is 1, it is a cache miss.

2) When load data is sent from main storage device 2

The value of bits 31 to 22 of address latch 8 sent via signal line 105 and the address field of read data of tag memory 4 sent via signal line 105 4 0 1 Is compared for each way, and the result of the comparison is ANDed with the value of the memory entry flag 402 for each bay. If there is a way with a logical value of 1 as a result of AND, it is a cache hit, and this way is defined as a hitway. If no way has a logical value of 1 as a result of A N D, it is cache miss. In this embodiment, it is assumed that the way in which the logical value of the memory load flag 402 is 1 is not a target of the replacement pay. Therefore, when the load data is sent from the main storage device 2, a cache miss does not occur.

Next, the detailed procedure for determining the replacement way will be described.

The cache control circuit 5 determines a release way when a cache miss is determined. As a method of determining the replacement way, a random method, an LRU method, or the like is known. However, in this embodiment, since the selection of the determination method is not important, any one of the random method, the RU method, and the like is appropriate. A simple method shall be used. Note that, as described above, in the present embodiment, the way in which the logic value of the memory load flag 402 is 1 adopts a method that is not a target of the rib raceway. This need not be adopted. No. of way decided as riff raceway When the logical value of the ti flag 403 is 1, write-back is performed.

The cache control circuit 5 performs the following operation based on the results of the cache hit determination and the live raceway decision described above.

(Operation 1)

At the time of a cache hit, the hitway number is encoded into 2 bits as an access way number and sent on the signal line 107. At the time of a cache miss, the rib raceway number is encoded as an access way number into two bits and sent on the signal line 107.

(Operation 2)

At the time of a cache miss in the load request from the processor, the word line.The value of bit 31 from address bit 6 sent from address latch 8 via 105 is used as the load address to memory on signal line 108. Send to Also, at the time of write Novec, the values of address bits 6 to 21 sent from address latch 8 via signal line 105 and the address field 401 of the way determined as the replacement way are used. Combine with the value and send on signal line 108 as a store address to memory.

(Operation 3)

When a cache hit is determined and write-back is performed, a logical value of 1 is output on the signal line 109. Also, a column access command (a read command is used for a command with a read command) to the SDRAM control circuit 6 of the bank 0 data memory 15 or the bank 1 data memory 16 via the signal line 110 or 111. ).

(Operation 4)

When a cache miss is determined in response to a load request from the processor 1 and the like, the address latch 4 bit 2 of the address latch 4 is stored in the address field 410 for the tag memory 4 replacement way entry. Write the value of, and write the logical value 1 to memory load flag 402.

When a cache miss is determined in response to a store request from processor 1, address latch 401 is assigned to address field 410 of address space of tag memory 4 bits 31 to 2 of address latch 8 Write the value of 2 and write the logical value 1 to the dirty flag 403.

When a cache hit is determined for the load data sent from the main storage device 2, a logical value 0 is written to the memory load flag 402 for the entry of the hitway of the tag memory 4 to be dirty. Write logical value 0 to flag 4003. FIG. 8 shows a time chart at the time of cache hit determination or writeback in response to a load request from the processor 1. It is assumed that the load address is included in bank 0 data memory 15.

At time t 20, the address latch is set to the address latch 8. At the same time that tag memory 4 is read, an active command is sent to the bank 0 data memory. At time t21, the cache hit determination is determined, and at time t22, a read command is sent to bank 0 data memory 15. Although not described in FIG. 8, the address sent to bank 0 data memory 15 at time t22 is the address of the hitway at the time of cache hit determination, and the address of the replaceway at the time of writeback. It is an address. At the time of cache hit determination, load data is output at time t23. At the time of light knocking, write-back data is output at time t23. The time interval from t22 to t23 is the column access delay. FIG. 8 shows a case where the time interval (hit judgment latency) from time t 20 to t 21 is smaller than the active one column command delay. When the hit determination latency is the same as the active one-time ram command delay, the times t 21 and t 22 are the same.

As described above, by performing the row access of the data memory prior to the determination of the cache hit determination result, the latency of the cache access can be reduced. When the cache hit determination result is determined, the hit-and-replace way can be read only by changing the column address. Therefore, even in the event of a cache miss, the preceding access to the data memory bank is not wasted. Therefore, in a system where the duty ratio of the cache memory (the probability that the data held in the cache is updated and differs from the contents in the memory) is high, the data memory bank of the data memory bank is compared with the case where the preceding row access is not performed. Access latency can be reduced without reducing usage efficiency.

In addition, when it is not necessary to write back the replacement way due to a cache miss, the preceding row access of the data memory bank is wasted, and the time required to create an unnecessary bank busy time is reduced as shown in the above embodiment. By providing a plurality of memory banks, it is possible to reduce damage caused by one hour of bank visits in which subsequent cache access is unnecessary.

According to the above embodiment, in a cache system using SDRAM, it is possible to efficiently overlap cache hit determination and data memory access.

As described above, the embodiment of the present invention has been specifically described based on S. It is needless to say that the present invention is not limited to this and various changes can be made without departing from the gist of the present invention.

For example, in the above embodiment, the SDRAM was used as the memory element of the data memory, but any memory element such as a general DRAM that can be accessed by two steps of mouth access and column access may be used. That is, if such a memory element is used as the memory element of the data memory, the row access is executed before the cache hit determination is determined and the column access is executed after the cache hit determination is performed at the time of the cache access. Needless to say, this can reduce access latency.

Also, in the above embodiment, the cache with the processor chip (level 1 cache) is not particularly described. However, the level 1 cache with the processor chip and the SRAM such as the SDRAM shown in the above example are usually used. A cache memory is often composed of a level 2 cache consisting of external memory chips. In the computer system having such a configuration, if the cache memory device of the present invention is applied to the level 2 cache, the access latency of the level 2 cache can be reduced, and the performance of the entire 2-level cache memory can be improved. It goes without saying that you can do it. It is needless to say that a level 3 cache or the like positioned on the main storage device side is provided, and the present invention can be applied to the level 3 cache or the like. Industrial applicability

According to the present invention, the matching between a hierarchical memory structure and an information processing device having a direct memory access (DMA) function, particularly between hierarchical memories (for example, a main memory and a cache memory) when a DMA process occurs. By applying the assurance to the information processing device that performs snub processing, it is possible to improve the system performance by reducing the memory access time while guaranteeing the consistency of the hierarchical memory questions when DMA occurs. become.

Claims

The scope of the claims

1. A cache memory device including a data memory for storing data and a tag memory for storing an address,

The data memory is composed of memory elements accessed by two steps of row access and column access,

A cache memory device, wherein a row access of the data memory is executed before a cache hit determination is determined upon a cache access.

2. The cache memory device according to claim 1, wherein at the time of cache access, a column access is performed after a cache determination is determined.

3. It has a data memory for storing data and a tag memory for storing addresses, and uses a memory element accessed by two steps of row access and column access as the data memory, and an indexer of the tag memory. A multiple associative cache memory device in which a plurality of ways exist for a set number as a dress,

A cache memory device wherein data of all ways having the same set number is arranged at the same address of the data memory.

4. A data memory for storing data, a tag memory for storing addresses, and a cache control means, wherein a memory element accessed by two steps of row access and column access is used as the data memory, A multiple associative cache memory device in which a plurality of bays exist for a set number which is an index address of a tag memory,

The data of all ways having the same set number is allocated to the same address in the data memory,

The cache control means executes a row access of the data memory before a cache hit determination is determined at the time of a cache access,

When a cache hit is determined in the cache hit determination, a column access of the data memory is executed using the number of the hit way, and

If a cache miss is determined in the cache hit determination, and it is necessary to write back the rebrace target way to the memory to be cached, the data memory column access is performed using the rebrace target way number. Run A cache memory characterized in that column access to the data memory is interrupted when a cache miss is determined in the cache hit determination and it is not necessary to write back the replacement target cache to the cache target memory. apparatus.

5. The data memory comprises a plurality of banks.

4. The cache memory device according to 4.

6. The cache memory device according to claim 1, wherein the data memory comprises a DRAM.

7. The cache memory device according to claim 1, wherein the data memory comprises a synchronous DRAM.

8. A processor, a main storage device, a cache memory device that retains a part of data stored in the main storage device, a processor bus connecting the processor and the cache memory device, the main storage device and the cache. An information processing system having a memory bus for connecting a flash memory device,

The processor has means for requesting a data load to the cache memory device via the processor bus, and means for requesting a data store to the cache memory device via the processor bus,

Means for sending requested data to the cache memory device in response to a load request from the cache memory device via the memory bus; and a switch from the cache memory device via the memory bus. Means for storing the data received in response to the store request.

The cache memory device g includes a data memory that stores data, and a tag memory that stores an address. The data memory is configured by a memory element that is accessed by two steps of row access and column access. In this case, the information processing system executes a row access of the data memory before a cache hit determination is determined.

9. The information processing system according to claim 8, wherein at the time of cache access, a column access is executed after a cache determination is determined.

10. A processor, a main storage device, a cache memory device for holding a part of data stored in the main storage device, a processor bus connecting the processor and the cache memory device, and the main storage device. And an information processing system having a memory bus connecting the cache memory device And

The processor has means for requesting the cache memory device to load data via the processor bus, and means for requesting a data store from the cache memory device via the processor bus.

The main storage device includes: a unit that sends requested data to the cache memory device in response to a cache request from the cache memory device via the memory bus; and the cache memory device via the memory bus. Means for storing the data received in response to the storage request of

The cache memory device includes a data memory for storing data, a tag memory for storing an address, and cache control means, and a memory element accessed in two steps of row access and column access is referred to as the data memory. A multiple associative cache memory device in which a plurality of ways exist for a set number, which is an index address of the tag memory.

Placing data of all ways of the same set number in the same address of the data memory,

When a cache hit is determined in the cache hit determination, a column access of the data memory is executed using a hit way number,

If a cache miss is determined in the cache hit determination and the way to be rebraced needs to be written back to the main storage device, column access to the data memory is performed using the number of the way to be replaced. Run

An information processing system for suspending column access of the data memory when a cache miss is determined in the cache hit determination and a way to be rebraced does not need to be written back to the main storage device. .

11. The information processing system according to claim 8, wherein the data memory is configured by DRAM.

12. The information processing system according to claim 10, wherein said data memory is configured by synchronous DRAM.