JPH0240760A - Information processor - Google Patents

Abstract

PURPOSE:To make the whole constitution small in size and simple by supplying a program that a sub-CPU executes from a main processing part to a subprocessing part and storing the program in the RAM of the subprocessing part. CONSTITUTION:The program of the subprocessing part 20 is read out of the ROM 12 of the main processing part 10 and supplied to a data bus DBM. At this time, a data bus buffer circuit 33 is ready for transfer and program data read out of the ROM 12 is supplied to the data bus DBS of the sub-processing part 20. The processing part 20 stores the RAM 23 with the program data supplied from the side of the processing part 10 in order. In this constitution, the processing part 20 is provided with only the RAM 23, where the program data that the sub-CPU 21 executes are stored, so the ROM for program storage is reduced and the whole constitution is therefore made simple and small in size.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an information processing device, and is particularly suitable for application to one in which a sub CPU (central processing unit) executes control of an external device.

[Prior Art] For example, a floppy disk drive device has many mechanical components, so its processing speed is slower than that of a CPU. Therefore, a sub CPU is provided in addition to the main CPU, and the sub CPU executes the access operation of the floppy disk drive device.
A device as shown in FIG. 3 has been proposed in which the PU can perform other processing to improve overall processing efficiency.

In FIG. 3, this conventional information processing apparatus is roughly divided into a main processing section 10 and a sub-processing section 20, and each processing section 10.20 is provided with a CPU 1l, 21, respectively. Here, the sub CPU 21 controls the access operation of the floppy disk drive device 30, and the main CPU 11 controls all other processes executed by the information processing device.

The main processing unit 10 includes a read-only memory (ROM>12) that stores programs to be executed by the CPU 11, and a random access memory that is used as a working memory to store data used for execution and data obtained as a result of execution. It is equipped with a memory (RAM>13) and an input/output interface circuit 14 that transfers data to and from the sub-processing unit 20. It is connected to the.

Reading and writing of the ROM 12 and RAM 13 are controlled by a memory control circuit 15. The memory control circuit 15 controls reading or writing according to a control signal from the CPU 11. ROM12 and RA
When M13 receives a read command from the memory control circuit 15, it reads data from an area corresponding to the address of the address bus ABM and outputs it to the data bus DBM. Further, when the RAM 13 is given a write command from the memory control circuit 15, the address bus A
Write data on the data bus DBM to an area corresponding to the address of the BM.

The input/output interface circuit 14 is controlled by an input/output control circuit 16.

The input/output control circuit 16 controls the input/output interface circuit 14 according to control signals from the CPU II. That is, the handshake operation is executed via the handshake data line MSL that connects the main processing section 10 and the sub-processing section 20.

The sub-processing unit 20 also has almost the same configuration as the main processing unit 10, and the codes of the corresponding parts are the same as those of each part in the main processing unit 10, with the last digit being the same as each part, and the second digit is the same as the code with "2" added. , and the explanation thereof will be omitted. Note that the sub processing unit 20
The input/output interface circuit 24 of the main processing unit 10
It not only transfers data to and from the floppy disk drive device 30, but also transfers data to and from the floppy disk drive device 30.

Further, the conventional device shown in FIG. 3 has a reset switch 31, and when this reset switch 31 is pressed, a reset signal generation circuit 32 sends a signal to each CPU II and 21 of the main processing section 10 and the sub processing section 20. A reset signal is provided. At this time, CPU II and 21 are reset once, and ROIVI 12 and 22 are reset.
The process will be executed from the first processing step.

In the above configuration, when the CPU 1l of the main processing unit 10 executes a program stored in the ROM 12, for example, if the CPU 1l desires data on the floppy disk loaded in the floppy disk drive device 30, the input/output control circuit 16 controls the input/output interface circuit 14 to enable data transfer, and sends identification data of the desired data to the sub-processing unit 2.
Give to 0.

At this time, the CPU 21 of the sub-processing section 20 controls the input/output control circuit 26 to take in predetermined data from the floppy disk drive device 30 via the input/output interface circuit 24 and temporarily store it in the RAM 23.
When all or a predetermined amount of predetermined data is stored in the RAM 23, a transfer preparation end signal is given to the main processing unit 10 via the data line MSL, and then the main processing unit 1
When receiving a response signal from 0, the data stored in the RAM 23 is transferred.

When the CPU 11 of the main processing unit 10 receives the transfer preparation end signal, it sends back a response signal and causes the RAM 13 to sequentially store data that will arrive thereafter.

Incidentally, when data is stored in the floppy disk loaded in the floppy disk drive device 30, a similar process is executed, so the explanation thereof will be omitted.

[Problem M to be Solved by the Invention] By the way, since the sub-processing section 20 only executes the access processing to the floppy disk drive device 30, the used capacity of the ROM 22 and the RAM 23 is small, and in reality, the problem shown in FIG. As shown in , the address “0000J (hexadecimal) to rlF
Allocate up to FFJ and store the program in area ARI corresponding to these addresses.Meanwhile, allocate addresses r4000J to r7FFF to RAM23 and store appropriate data in area AR2 corresponding to these addresses according to processing. That's what I was doing.

However, recently, the capacity of commercially available RAMs is large, and as mentioned above, even after allocating areas for use, there remains a large amount of empty area, and an area with a capacity that can be used by the ROM 22 remains.

Even if an address is assigned in an attempt to use this empty area, an area with an address that overlaps with the ROM 22 cannot be used. Therefore, it can be said that the capacity of the RAM 23 is not used effectively.

In addition, considering the miniaturization of the device, ROM22 and R
Considering the commonality of AM23 as a memory, it is possible to use these ROM22 and RAM23 as one memory, but if ROM is used as the memory, data cannot be written, and If a RAM is used as the memory for the program, there is a risk that the program will be lost due to malfunction or the like.

The present invention has been made in consideration of the above points, and an object thereof is to provide an information processing device whose entire configuration can be made smaller and simpler by effectively utilizing one memory.

[Means for Solving the Problems] In order to solve the problems, the present invention provides an information processing system that includes, in addition to the main central processing unit, a sub central processing unit that controls data exchange with external devices. In the processing device, a second program to be executed by the sub-central processing unit is stored in a first storage means for storing a first program to be executed by the main central processing unit, and the second program to be executed by the sub-central processing unit is stored in the first storage means for storing the first program to be executed by the main central processing unit. At startup, the second program stored in the first storage means is transferred to the second storage means accessed by the sub-central processing unit.

[Operation] The second program executed by the sub central processing unit is also stored in the first storage means that stores the first program executed by the main central processing unit, and the second program is started or restarted. At times, the second program stored in the first storage means is transferred to the second storage means accessed by the sub central processing unit, and the second program is thereafter transferred and stored in the second storage means. The second program is executed by a sub-central processing unit.

As a result, the number of memories can be reduced compared to conventional devices, the overall configuration can be made simpler and smaller, and the memory can be used more effectively.

[Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 1, in which parts corresponding to those in FIG. 3 are denoted by the same reference numerals.

In this embodiment, the sub-processing section 20 uses R for program storage.
It is possible to execute access control of the floppy disk drive device 30 without having an OM.
21 is given a program to be executed, and the program is stored in the RAM 23.

Therefore, unlike the conventional device, the ROM 22 is omitted, and the ROM 12 of the main processing section 10 stores a program for the sub processing section 20.

Transfer of such a program is intended to occur at significant intervals of the reset signal. In this embodiment, the reset signal generation circuit 32 includes a reset switch 31
When is pressed, a reset signal is sent out which remains at a significant level for a period longer than the sufficient time required to transfer the program as described above, and the program is transferred during this significant period.

The address for reading the program for the sub-processing section from the ROM II of the main processing section 10 is output from the address generation circuit 17. This address generation circuit 17 has
A reset signal is given from the reset generation circuit 32, and during a period when this reset signal is at a significant level, the address is sent to the sub-processing unit 2.
It is generated while sequentially incrementing the address of the area storing the 0 program. Note that when the reset signal is at an idle level, the address generation circuit 17 applies the address generated by the main CPU 11 to the ROM 12 as is.

In this embodiment, the memory control circuit 15 of the main processing unit 10 controls the ROIVI 12 to be in the read mode, regardless of the CPU II signal, during a period in which the reset signal is significant.

The program data for the sub-processing unit 20 read from the ROM 12 is sent via the data bus buffer circuit 33 without passing through the data line connecting both interface circuits 14 and 24. This data bus buffer circuit 33 is connected to the data bus DBM of the main processing section 10 and the data bus DBS of the sub processing section 20, and when the reset signal given from the reset signal generation circuit 32 is significant, both data buses DBM and data bus D
BS is directly connected, and when the reset signal is inactive, both data buses DBM and data bus Dr3S are disconnected.

In this embodiment, as shown in FIG. 2, the RAM 23 in the sub-processing unit 20 includes a storage area A for programs executed by the CPU 21 in addition to a working area AR3.
R4 is allocated, and the program transferred from the main processing unit 10 is stored in this storage area AR4.

The address for storing this program is generated by the address generation circuit 27. Address generation circuit 27
A reset signal is given from the reset generation circuit 32, and during the period when this reset signal is at a significant level, the address of the area where the program is to be stored is sequentially incremented as an address. do.

Note that when the reset signal is at an idle level, the address generation diagram Q27 provides the address generated by the sub CPU 21 to the RAM 23 as is.

In the case of this embodiment, the memory control circuit 25 of the sub-processing section 20, during the period in which the reset signal is significant,
The RAM 23 is controlled to be in write mode.

Here, the reason why the program is transferred during the significant period of the reset signal is that the reset operation is performed before the original processing is executed, and the transfer operation is performed by giving the reset signal to each part. This is because it is easy to synchronize each part of the system.

Further, the program data is transferred via the data bus buffer circuit 33, and the ROM 12 and R
The reason why the address generation circuits 17 and 27 generate the address for the AM 23 is to enable transfer of program data even in a reset state in which the main CPU II and sub CPU 21 cannot perform processing.

In the configuration described below, when the reset switch 31 is pressed, the reset signal generation circuit 32 sends out a significant reset signal for a predetermined period of time. As a result, the address generation circuit 17 generates the address of the area storing the program for the sub-processing section 20, and the memory control circuit 17
5 controls the ROM 12 to read state. Thus,
A program for the sub-processing section 20 is read from the ROM 12 and applied to the data bus DBM. At this time, the data bus buffer circuit 33 is in a state where it can be transferred based on the reset signal, and the program data read from the ROM 12 is transferred to the data bus D of the sub-processing section 20.
Given to B.S.

In the sub-processing section 20, when the reset signal becomes significant, the address generation circuit 27 generates an address signal instructing the program storage area AR4 of the RAM 23, and the memory control circuit 25 gives a write command signal for the RAM 23 to the RAM 23. In this way, the program data given from the main processing section 10 side is sequentially stored in the RAM 23.

The reset signal generating circuit 32 disables the reset signal after a time that sufficiently exceeds the time during which such program data transfer is performed.

As a result, the data bus buffer circuit 33 disconnects both data buses DBM and DBS, and the address generation circuit 1
7 and 27 are in a state where addresses from the CPUs 11 and 21 are given to the ROM 12 and RAM 23 as they are.

Moreover, the CPU II and 21 are also in a state where they can execute processing. As a result, normal processing is executed from then on.

Therefore, according to the embodiment described above, the sub-processing section 10 includes:
Only RAM23 is provided, and C1'U21 is installed in this RAM23.
Since the program data to be executed by the controller is stored, the overall configuration can be made simpler and smaller due to the reduction in memory. In addition, as the time progresses, the CPU of the sub-processing section 20
2] The program to be executed is stored in the ROM of the main processing unit 10.
12 and then transferred to the RAM 23 of the sub-processing section 2o, so the program for the sub-processing section 20 will not be lost.

Note that in the above embodiment, the reset switch 31
Although the program data transfer operation is executed when the button is pressed, the transfer may be performed when the power is turned on or the like.

Further, in the above-described embodiment, the external device controlled by the sub-processing section 20 is the floppy disk drive device 30.
However, other external devices such as a printer device may be used.

[Effects of the Invention] As described above, according to the present invention, it is possible to store a program to be executed by the CPU of the sub-processing section by providing only one memory in the sub-processing section, and the reduction in the number of memories is , the overall configuration can be made smaller and simpler than conventional devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an information processing device according to the present invention, FIG. 2 is a route map showing RAM area allocation on the sub-processing section side, and FIG. 3 is a block diagram showing a conventional device. FIG. 4 is a route map showing area allocation of ROM, R, and AM on the sub-processing section side. 10... Main processing unit, 11... Main CPU, 1
2...ROM, 13.23...RAM, 14.24
...input/output interface circuit, 15.25...memory control circuit, 17.27...address generation circuit, 30...floppy disk drive device, 3
1... Reset switch, 32... Reset signal generation circuit, 33... Data bus buffer circuit. Figure 2 Figure 4

Claims (1)

[Claims] In an information processing device that includes a main central processing unit and a sub central processing unit that controls data exchange with an external device, A second program to be executed by the sub central processing unit is stored in a first storage means for storing a program, and the second program is accessed by the sub central processing unit when the device is started or restarted. An information processing apparatus characterized in that the second program stored in the first storage means is transferred to the means.