JPH0855097A - Data processing system and its memory access method - Google Patents

Abstract

PURPOSE:To provide a data processing system for multi-CPU system which enables each CPU to access a shared ROM with a simple constitution by effectively using the internal memory of the CPU. CONSTITUTION:A flip flop 6 sets a second CPU 1b to the operation stop state at the time or the start or the system, namely, power-on and resets this operation stop state after the end of access to a ROM 3 from a first CPU 1a. A selector circuit 4 selects the address outputted from the first CPU 1a as the address of the ROM 3 at the time of the start of the system. An output switching circuit 5 transfers the program outputted from the ROM 3 to the first CPU 1a. The first CPU 1a loads the program outputted from the ROM 3 to an internal RAM 2a. Meanwhile, the flip flop 6 resets the operation stop state of the second CPU 1b when the load processing of the first CPU 1a is terminated. The second CPU 1b outputs the address to access the program from the ROM 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-CPU data processing system in which a plurality of CPUs access a shared ROM.

[0002]

2. Description of the Related Art In recent years, for example, some hard disk devices such as control devices employ a multi-CPU data processing system using a plurality of microprocessors (CPUs).

In such a system, a plurality of ROMs (read only) usually associated with two CPUs are used.
memory) to program (microprogram)
To perform various control operations based on this program. As the ROM, a rewritable EEPROM (electrically erasable PROM) or the like is used so that the content of the program can be changed according to an instruction from the outside. A method using the built-in mask ROM of each CPU is also conceivable, but it is not desirable because the CPU must be replaced when the program is changed.

By the way, a plurality of ROs are provided corresponding to each CPU.
In the method of providing M, reduction of the number of ROMs and management man-hours of programs prepared in each ROM is a problem. By solving this problem, it is possible to reduce the cost of the system.

Conventionally, in the multi-CPU system, a technique has been developed in which each CPU shares and accesses one ROM. However, when each CPU accesses a required program from a shared ROM, a complicated control operation is required, and there is a drawback that the entire configuration becomes complicated.

[0006]

In the multi-CPU data processing system, the cost of the system can be reduced by sharing the ROM storing the program of each CPU. However, one R
The conventional method in which each CPU shares the OM has a drawback that complicated control operation is required and the entire configuration becomes complicated.

It is an object of the present invention to provide a multi-CPU data processing system in which each CPU can access a shared ROM with a simple structure by effectively utilizing the internal memory of the CPU.

[0008]

According to the present invention, in a multi-CPU data processing system having first and second CPUs that independently execute data processing, each CPU accesses a shared ROM, It is configured to access each program. The system of the present invention sets the second CPU in an operation stop state when the system is activated and resets the operation stop state according to the control of the first CPU, and the access operation of the first CPU. It has a first access control means to be executed and a second access control means to execute the access operation of the second CPU.

[0009]

According to the present invention, the reset control means sets the second CPU in the operation stop state at the time of system startup when the power is turned on, and after the first CPU finishes the access to the ROM, the second CPU Reset the operation stop state of. The first access control means causes the first CPU to access the ROM when the system is activated, and loads the program output from the ROM into the internal RAM of the first CPU. The second access control means is
The access operation of the second CPU to the ROM is executed to transfer the program output from the ROM to the second CPU. With such a configuration, the reset control means that effectively uses the internal RAM of the first CPU and puts the second CPU into the operation stop state at the time of system startup,
Each CPU is alternately ROM without complicated control
Can be accessed to get each program.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a basic configuration of a data processing system according to the first embodiment, FIG. 2 is a block diagram showing a concrete configuration of a data processing system of the same embodiment, and FIG. 3 is an operation of the same embodiment. FIG. 4 is a flow chart for explaining, FIG. 4 is a block diagram showing a main part of the data processing system according to the second embodiment, and FIG. 5 is a timing chart for explaining the operation of the same embodiment. (Basic configuration of the first embodiment) This system is a multi-CPU system having two first CPUs 1a and 1b as shown in FIG. Each CPU 1
Each of a and 1b has an internal RAM, and loads and executes a program (microprogram) accessed from the ROM 3.

The ROM 3 is a shared memory of the CPUs 1a and 1b, and stores each program required for each operation. In the same embodiment, the ROM 3 divides the address space into two for convenience, and stores a program corresponding to the CPU 1a in a lower address space (referred to as lower area) 3a and an upper address space (referred to as upper area) 3 for example.
A program corresponding to the CPU 1b is stored in b.

Further, the present system includes a selector circuit 4,
It has an output switching circuit 5 and a flip-flop 6. The selector circuit 4 uses the address bus 7 of each CPU 1a, 1b.
a, 7b, and selects and outputs one of the addresses A0-AN output from each CPU 1a, 1b.
The output switching circuit 5 transfers the data (program in this embodiment) D0-DN output from the ROM 3 to each CPU 1a,
It is a selection circuit for outputting to one of the data buses 8a and 8b connected to 1b.

The flip-flop 6 is a reset control means for controlling the operating state of the second CPU 1b, and the flip-flop 6 receives the power ON signal PW input to the set terminal S to output the second C signal.
PU1b is set to the operation stop state. Further, the flip-flop 6 resets the second CPU 1b in the operation stop state by the reset signal RE input to the reset terminal R. The reset signal RE is a kind of control signal output from the output port of the CPU 1a. (Specific Configuration of First Embodiment) Specifically, as shown in FIG. 2, the present system includes a lower address (for example, A of the addresses A0-AN output from the CPUs 1a and 1b).
Latch circuits 10a and 10b for latching 0-A7) and three-state buffer circuits 11a and 11b for controlling the output of a higher address (for example, A8-AN) are provided.

The latch circuits 10a and 10b are provided for each CPU 1
It is connected to the data buses 8a and 8b of a and 1b and outputs the latched lower address to the selector circuit 4. The selector circuit 4 sets one of the lower addresses output from the CPUs 1a and 1b as the lower address of the ROM 3. The three-state buffer circuits 11a and 11b are controlled by the output signal of the flip-flop 6 and
One of the upper addresses output from 1a and 1b is a ROM
It is set as the upper address of 3.

The output switching circuit 5 transfers the program (data D0-DN) output from the ROM 3 to each CPU 1a,
One of the data buses 8a and 8b connected to 1b is selected and transferred. (Operation of First Embodiment) The operation of the first embodiment will be described with reference to the flowchart of FIG. First, when the power is turned on and the system is activated, the flip-flop 6 is set by the power ON signal PW (step S1). The power ON signal PW is output from, for example, a power controller provided in the system.

By setting the flip-flop 6, the second
The CPU 1b is set to the operation stop state (step S
2). That is, when the power is turned on, the first CPU 1a and the second CPU 1a
Both CPUs 1b are activated, but the second CPU 1b is temporarily stopped by the output signal of the flip-flop 6.

The first CPU 1a outputs addresses A0-AN for accessing the ROM3. Selector 4
Is the address A0-AN output from the first CPU 1a.
Is selected and output as an address for accessing the ROM 3 (step S3).

Specifically, as shown in FIG. 2, the first CPU
Of the addresses A0-AN output from 1a, the lower address is latched by the latch circuit 10a. Also,
The upper address is output to the 3-state buffer circuit 11a. The selector circuit 4 receives the first signal latched by the latch circuit 10 a according to the output signal of the flip-flop 6.
The lower address is output from the CPU 1a. On the other hand, the 3-state buffer circuit 11a is controlled by the output signal of the flip-flop 6 and outputs the upper address from the first CPU 1a. At this time, the second CPU 1b is in the operation stopped state, and the 3-state buffer circuit 11b is in the output stopped state (high impedance state).

The ROM 3 receives the address A0-AN and the address control signal AL output from the first CPU 1a.
The program stored in the lower area 3a is accessed and output (step S4). The output switching circuit 5 outputs the program output from the ROM 3 to the data bus 8a according to the output signal of the flip-flop 6. 1st C
The PU 1a loads the program input through the data bus 8a into the internal RAM 2a (step S5). After that, the first CPU 1a executes the program loaded in the internal RAM 2a, and executes various control operations, for example. Here, specifically, the first CPU 1a
Executes the process of accessing the ROM 3 to execute the initial program stored in advance in the lower area 3a, and accessing this to access the main program stored in the lower area 3a to load it into the internal RAM 2a.

When the loading of the program into the internal RAM 2a is completed, the first CPU 1a outputs a reset signal RE for resetting the flip-flop 6 from the output port (YES in step S6). This reset signal R
The flip-flop 6 is reset by E, and the second CPU
1b is reset and started up (step S7).

Therefore, the second CPU 1b uses the first CP
Like U1a, ROM3 is accessed to access upper area 3
For example, the operation of loading the program stored in b into the internal RAM 2b is executed.

Specifically, as shown in FIG. 2, by resetting the flip-flop 6, the selector circuit 4 selects and outputs the lower address latched by the latch circuit 10b. The lower address output from the second CPU 1b is latched in the latch circuit 10b. Further, the 3-state buffer circuit 11a is in the output stopped state (high impedance state). On the other hand, the 3-state buffer circuit 11b outputs the upper address from the second CPU 1b. Therefore, the addresses A0-AN output from the second CPU 1b are output as addresses for accessing the ROM 3 (step S8).

As a result, the second CPU 1b will access the program stored in the upper area 3b of the ROM 3 (step S9). That is, the ROM 3 is the second
The program stored in the upper area 3b is accessed and output by the address A0-AN and the address control signal AH output from the CPU 1b. Output switching circuit 5
The ROM 3 according to the reset of the flip-flop 6.
The program output from is output to the data bus 8b. The second CPU 1b loads the program input through the data bus 8b into the internal RAM 2b. The second CPU 1b does not necessarily load the program accessed from the ROM 3 into the internal RAM 2b.

In this way, the first CPU 1a accesses the necessary program from the shared ROM 3 and loads it into the internal RAM 2a. By executing the loaded program, the first CPU 1a executes various control operations which are normal operations (step S10). On the other hand, the second CPU 1b is in the operation stop state at the time of startup until the access operation of the first CPU 1a is completed. 1st CP
When the operation stopped state is reset under the control of U1a, the second CPU 1b will access the necessary program from the ROM 3. By executing this program, the second CPU 1b also executes various control operations that are normal operations (step S10). (Second Embodiment) In the second embodiment, as shown in FIG.
The second CPU 1b is connected to the ROM 3 by the data bus 8b and the address bus 7b as usual, and the first CPU 1a
Is connected to the second CPU 1b. First CPU1
The data bus 8a, the address bus 7a, and the control signal line of a are connected to the general-purpose input / output port of the second CPU 1b, and execute data transfer with the second CPU 1b.

The feature of the second embodiment is that the first CPU 1a
Accesses the ROM 3 indirectly via the second CPU 1b. Further, the first CPU 1a is supplied with the clock pulse CP from the second CPU 1b, and the operating speed is controlled by changing the frequency of the clock pulse CP.

Next, the operation of the second embodiment will be described with reference to the timing chart of FIG. First, when the power is turned on, the second CPU 1b operates as usual in the address A0.
-Output AN to access ROM3. That is, by the address A0-AN and the address control signal AH, the ROM
The second CPU 1b executes the program by accessing the program stored in the upper area 3b of No. 3. At this time, the second CPU 1b transfers the accessed program to the internal R
You may load in AM2b.

The first CPU 1a is in a stopped state until the clock pulse CP is supplied from the second CPU 1b. That is, when the power is turned on, the operation of the first CPU 1a is stopped. When the second CPU 1b finishes the predetermined processing, the second CPU 1b supplies the clock pulse CP to the first CPU 1a to activate the first CPU 1a and execute the program loading processing. At this time, as shown in FIG. 5, the second CPU 1b supplies the clock pulse CP2 obtained by dividing the basic clock pulse CP1 to operate the first CPU 1a at a relatively low speed.

When the first CPU 1a is activated, it outputs the address latch enable signal ALE, and outputs the addresses A0-AN to the address bus 7a in response to this signal. The second CPU 1b receives the signal ALE and inputs the signal ALE.
Address A0-A of the address bus 7a at the falling edge of
Recognize N.

The second CPU 1b accesses the ROM 3 by the address A0-AN output from the first CPU 1a and reads the program stored in the lower area 3a here. As shown in FIG. 5, when the first CPU 1a outputs a read signal RD having a significant logic level "L", the second CPU 1b outputs the data (program) read from the ROM 3 to the data bus 8a. Second CPU1
b monitors the output of the read signal RD and stops the data output when the output is stopped. The second CPU 1b is
By outputting the ready signal RDY, the first CPU 1
It is possible to delay the operation of a.

In this way, the first CPU 1a
Under the control of the CPU 1b, the second CPU 1
The program accessed from the ROM 3 is input via b and loaded into the internal RAM 2a. When the first CPU 1a finishes loading the program, the second CPU 1b changes the division ratio of the clock pulse CP and supplies, for example, the basic clock pulse CP1. That is, the first CPU 1a is shifted to the constant speed operation state. Thereby, the first CPU 1a
Will execute the program loaded in the internal RAM 2a at a constant speed.

[0031]

As described in detail above, according to the present invention, in a multi-CPU data processing system, when a program or the like is accessed from a shared memory, the operation of one CPU is stopped and the other one is stopped. By the method of effectively utilizing the internal memory of the CPU, an efficient access process by each CPU can be realized without requiring a particularly complicated configuration. Therefore, if one ROM is applied to a system shared by the CPUs, the cost of the system can be reduced and an efficient program loading process can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a data processing system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of the data processing system according to the first embodiment.

FIG. 3 is a flowchart for explaining the operation of the first embodiment.

FIG. 4 is a block diagram showing a main part of a data processing system according to a second embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of the second embodiment.

[Explanation of symbols]

1a, 1b ... CPU, 2a, 2b ... Internal RAM, 3 ... R
OM, 4 ... Selector circuit, 5 ... Output switching circuit, 6 ... Flip-flop.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location 7230-5B G06F 9/06 420 K

Claims (6)

[Claims] 1. A first data processing device and a second data processing device which independently perform data processing, memory means accessed by each of the first and second data processing devices, and the first data processing device when the system is started. Reset control means for setting the second data processing device to an operation stop state and resetting the operation stop state of the second data processing device according to the control of the first data processing device; A first operation for executing an access operation of the first data processing device to the memory means
Access control means, and second access control means for executing the access operation of the second data processing device to the memory means after the operation stop state is reset by the reset control means. And data processing system. 2. A first data processing device and a second data processing device, which independently execute data processing, and respective devices corresponding to the respective data processing devices accessed by each of the first and second data processing devices. The memory means storing the program and the second data processing device are set to the operation stop state at the time of system startup, and the second data processing device is set to the second data processing device after the access to the memory means is completed. Reset control means for resetting an operation stop state of the data processing device; and an access operation of the first data processing device to the memory means at the time of starting the system to execute the program output from the memory means. The first
First access control means to be loaded into the internal memory means of the data processing device, and after the operation stop state is reset by the reset control means, the access operation of the second data processing device to the memory means is executed. And a second access control means for transferring the program output from the memory means to the second data processing device. 3. A first data processing device and a second data processing device that independently perform data processing, and respective devices corresponding to the respective data processing devices accessed by each of the first and second data processing devices. The memory means storing the program and the second data processing device are set to the operation stop state at the time of system startup, and the second data processing device is set to the second data processing device after the access to the memory means is completed. Reset control means for resetting an operation stop state of the data processing device; address selection means for selecting an address output from one of the first and second data processing devices when the memory means is accessed; and the memory means. Control for transferring the program output from the memory means to one of the first and second data processing devices at the time of access And an output control of the program output from the memory means by selecting an address output from the first data processing device by the address selection means at the time of starting the system to access the memory means. First access control means for transferring to the first data processing device by the means and loading it into the internal memory means, and after the operation stop state is reset by the reset control means, the second address control means Second access control for selecting an address output from the data processing device to access the memory means, and transferring the program output from the memory means to the second data processing device by the output control means And a data processing system. 4. Data having a configuration in which first and second data processing devices for independently performing data processing are provided, and the operation of the second data processing device is controlled by the first data processing device. In the processing system, the first data processing device is accessed to access the first data processing device.
And memory means for storing each program corresponding to each of the second data processing devices, and the second data processing device when the second data processing device is activated under the control of the first data processing device. Access control means for outputting the program accessed by the first data processing device from the memory means to the second data processing device in response to an access request from the data processing device. Processing system. 5. Data having a configuration including first and second data processing devices that independently perform data processing, and the operation of the second data processing device is controlled by the first data processing device. In the processing system, clock supply means for outputting an operation clock having a frequency set by the first data processing device to an operation clock terminal of the second data processing device; and accessing the first data processing device. , The first
And memory means storing each program corresponding to each second data processing device, and exchange of addresses and data between the second data processing device through an input / output port of the first data processing device. And a data transfer unit that executes the data transfer when the second data processing device is activated in response to the operation clock supplied from the clock supply unit under the control of the first data processing device. Means for accessing the first data processing device from the memory means according to an address supplied from the second data processing device through the means, and accessing the accessed program to the second data processing device through the data transfer means. A data processing system, comprising: an access control unit for outputting. 6. A program corresponding to each of the data processing devices, accessed by each of the first and second data processing devices and the first and second data processing devices that independently execute data processing. In a data processing system comprising memory means for storing the data, the step of setting the second data processing device in a non-operational state when the system is activated, and the first data processing device performing an access operation. hand,
Loading the program output from the memory means into the internal memory means of the first data processing device; and the second data processing after the first data processing device has finished accessing the memory means. Resetting the operation-stopped state of the device; and, after resetting the operation-stopped state, the second data processing device executes an access operation to execute the program output from the memory means to the second data. And a step of transferring to a processing device.