JP3839068B2 - Semiconductor integrated circuit device - Google Patents

Description

始めに、ＣＰＵ２に受信完了割込ＲＸＩが要求され、割込ルーチンに分岐する。まず、汎用レジスタＲ０をスタックに退避する（１）。そして、ＳＣＩの受信データレジスタＲＤＲの内容を汎用レジスタＲ０の下位８ビットＲ０Ｌにリードする（２）。
【０１０８】
また、内蔵ＲＡＭ２上に配置した作業用アドレスＳＵＭの内容を汎用レジスタＲ０の上位８ビットＲ０Ｈにリードする（３）。そして、Ｒ０ＨとＲ０Ｌの内容を加算する（４）。この加算結果をアドレスＳＵＭにライトする（５）。
【０１０９】
さらに、内蔵ＲＡＭ２上に配置した作業用アドレスＣＮＴの内容を汎用レジスタＲ０Ｈにリードする（６）。そして、Ｒ０Ｈの内容をデクリメント（−１）する（７）。このデクリメント結果をアドレスＣＮＴにライトする（８）。
【０１１０】
この内容が“０”であれば、Ｌ１に分岐し（９）、割込選択レジスタＩＲＱＳＥＬの受信完了割込ＲＸＩに対応するビットを反転する（１２）。このとき、割込要求フラグＲＤＲＦが“１”にセットされたままなので、ＣＰＵ１に受信完了割込ＲＸＩが要求される。そして、割込ルーチンから復帰する（１３）。
【０１１１】
また、前記アドレスＣＮＴにライトされた内容が“０”でなければ（９）、割込要求フラグＲＤＲＦを“０”にクリアする（１０）。そして、分岐命令を実行した（１１）後、割込ルーチンから復帰する（１３）。
【０１１２】
また、以下のプログラム例により、マルチプロセッサ受信のアドレス判定を行うことができる。なお、この場合にはアドレス判定の結果、受信したアドレスが自身のアドレスに一致していれば、受信完了割込の要求先をＣＰＵ１に変更するものとする。
【０１１３】

始めに、ＣＰＵ２に受信完了割込ＲＸＩが要求され、割込ルーチンに分岐する。まず、汎用レジスタＲ０をスタックに退避する（１）。そして、ＳＣＩの受信データレジスタＲＤＲの内容を汎用レジスタＲ０の下位８ビットＲ０Ｌにリードする（２）。
【０１１４】
この内容を、マルチプロセッサ受信の自分のＩＤと比較する（３）。この結果、一致していれば、Ｌ１に分岐し（４）、割込選択レジスタＩＲＱＳＥＬの受信完了割込ＲＸＩに対応するビットを反転する（７）。このとき、割込要求フラグＲＤＲＦが“１”にセットされたままなので、ＣＰＵ１に受信完了割込ＲＸＩが要求される。そして、割込ルーチンから復帰する（８）。
【０１１５】
また、自分のＩＤと比較した結果が一致していなければ（４）、割込要求フラグを“０”にクリアする（５）。そして、分岐命令を実行した（６）後、割込ルーチンから復帰する（８）。
【０１１６】
なお、この場合に１本の割込で複数の転送を行うことができる。たとえば、ステッピングモータを駆動して、かつこの加速／減速を行うことができる。また、タイマのコンペアマッチ割込ＯＣＭＩ毎に、ポートから出力するデータを更新してモータを駆動する。さらに、コンペアレジスタの内容を更新して、データ出力の周期を変更して加速／減速を行うことができる。
【０１１７】
この状態の表示に、内蔵ＲＡＭ２上に配置した作業用アドレスＵＰＤＷの内容を用いる。このビット６が“０”にクリアされているときに定速動作であり、“１”にセットされているときは加速または減速、すなわちビット７が“０”にクリアされているときは減速、“１”にセットされているときには加速動作である。なお、初期値はビット６、７ともに“１”にセットしておく。
【０１１８】
また、パルス出力回路のネクストデータレジスタＮＤＲに次の出力パルスを格納するものとし、タイマの定数レジスタＯＣＲにパルス出力周期を設定するものとする。タイマカウンタが定数レジスタの値に一致すると、図示はされないコンペアマッチ信号が発生し、ＮＤＲの内容がＩＯＰ８と兼用の端子から出力される。同時にタイマカウンタの値は０にクリアされる。このＮＤＲは４ビットとする。
【０１１９】
このようなパルス出力については、特願平４−１１７９６９号と同様とする。
【０１２０】
ＰＵＳＨ Ｒ０ （１）
ＭＯＶ．Ｂ ＠ＮＤＲ，Ｒ０Ｌ （２）
ＲＯＴＬ．Ｂ Ｒ０Ｌ （３）
ＢＬＤ ＃４、Ｒ０Ｌ （４）
ＢＳＴ ＃０，Ｒ０Ｌ （５）
ＭＯＶ．Ｂ Ｒ０Ｌ，＠ＮＤＲ （６）
始めに、ＣＰＵ２にコンペアマッチ割込ＯＣＭＩが要求され、割込ルーチンに分岐する。まず、汎用レジスタＲ０をスタックに退避する（１）。そして、ネクストデータレジスタＮＤＲの内容を汎用レジスタＲ０の下位８ビットＲ０Ｌにリードする（２）。
【０１２１】
この内容を回転する（３）。ここでは、４ビット単位の回転とするために、回転後のビット４をキャリフラグに格納し（４）、このキャリフラグをビット０に格納する（５）。この４ビット単位の回転が終了した結果をＮＤＲに書き込む（６）。この内容が次のコンペアマッチで端子から出力される。
【０１２２】

続いて、アドレスＵＰＤＷのビット６の内容を検査し（７）、この内容が“０”（定速動作）であれば、Ｌ３に分岐し（８）、定数レジスタＯＣＲの内容は保持される。また、“０”でなければ、定数データレジスタＯＣＲの内容を汎用レジスタＲ０にリードする（９）。
【０１２３】
さらに、アドレスＵＰＤＷのビット７の内容を検査し（１０）、この内容が“０”（減速動作）であれば、Ｌ１に分岐し（１１）、“０”でなければ（加速動作）、定数値ＣＮＳＴを汎用レジスタＲ０から減算し（１２）、Ｌ２に分岐する（１３）。このＬ１では定数値ＣＮＳＴを汎用レジスタＲ０に加算し（１４）、Ｌ３では汎用レジスタＲ０の内容を定数レジスタＯＣＲに書き込む（１５）。
【０１２４】

続いて、アドレスＣＮＴの内容を汎用レジスタＲ０Ｈにリードする（１６）。この内容Ｒ０Ｈの内容をデクリメント（−１）する（１７）。この内容が“０”でなければ、Ｌ５に分岐し（１８）、“０”であれば、アドレスＵＰＤＷのビット６の内容を検査する（１９）。
【０１２５】
さらに、この内容が“０”（定速動作）であれば、Ｌ６に分岐し（２０）、“０”でなければ、ビット７の内容を検査し（２１）、さらにこの内容が“０”（減速動作）であれば、Ｌ６に分岐し（２２）、“０”でなければ（加速動作）、アドレスＵＰＤＷのビット６を“０”にクリアして、定速動作に遷移し（２３）、低速動作の回転数ＣＮＴ１をＲ０Ｈに設定する（２４）。そして、Ｌ５に分岐する（２５）。
【０１２６】
Ｌ４では、減速動作に遷移するため、アドレスＵＰＤＷのビット６を“１”にセット（２６）し、ビット７を“０”にクリアする（２７）。また、減速動作の回転数ＣＮＴ２をＲ０Ｈに設定する（２８）。
【０１２７】
さらに、Ｌ５では、汎用レジスタＲ０Ｈの内容をアドレスＣＮＴにライトする（２９）。そして、分岐命令を実行（３０）した後、割込ルーチンから復帰する（３２）。
【０１２８】
そして、減速動作の終了後、Ｌ６では割込選択レジスタＩＲＱＳＥＬのにコンペアマッチ割込ＯＣＭＩに対応するビットを反転する（３１）。このとき、割込要求フラグＯＣＭＦが“１”にセットされたままなので、ＣＰＵ１に受信完了割込ＲＸＩが要求される。そして、割込ルーチンから復帰する（３２）。
【０１２９】
また、起動は、前記割込要求レジスタを用いて、ＣＰＵ１からＣＰＵ２に割込を要求して、たとえばＲＡＭＰ上の所定のアドレスにコマンドを配置して指示をすればよい。
【０１３０】
以上により、たとえば特願平４−１３７９５４号または特願平４−１１７９６９号に記載の方法に比べて、ＲＡＭにデータを展開しておく必要がなく、ＲＡＭの使用量を節約できる。
【０１３１】
また、ＣＰＵ２を、割込に対応したデータ処理に主として使用すれば、ＣＰＵ２は常に処理すべきプログラムがあるとは限らない。そこで、１つの割込によるデータ処理が終了した時点で、処理すべきプログラムがなければ、ＣＰＵ２は低消費電力状態、いわゆるスリープ状態にするのがよい。
【０１３２】
このスリープ状態では、専用のＳＬＥＥＰ命令を実行することにより遷移する。そして、ＣＰＵ２に供給されるクロックが停止される。また、割込が要求されると、スリープ状態は解除される。
【０１３３】
次に、図７により低消費電力状態制御回路を詳細に説明する。
【０１３４】
なお、この低消費電力状態制御回路は、たとえばクロック発振器内に構成され、この低消費電力状態は３個のフリップフロップＳＬＰＦ１、ＳＬＰＦ２、ＳＳＢＹＦで制御される。
【０１３５】
フリップフロップＳＬＰＦ１は、ＣＰＵ１がＳＬＥＥＰ命令を実行すると、セット状態となる。このとき、ＣＰＵ１はスリープ状態となる。また、ＣＰＵ１に対する割込要求が発生するとクリア状態となる。
【０１３６】
フリップフロップＳＬＰＦ２は、ＣＰＵ２がＳＬＥＥＰ命令を実行すると、セット状態となる。このとき、ＣＰＵ２はスリープ状態となる。また、ＣＰＵ２に対する割込要求が発生するとクリア状態となる。
【０１３７】
フリップフロップＳＳＢＹＦは、図示はされない制御ビットＳＳＢＹを“１”にセットした状態で、一方のＣＰＵがスリープ状態で、他方のＣＰＵがＳＬＥＥＰ命令を実行するとセット状態となる。このソフトウェアスタンバイ状態では、クロック発振器を始め、全ての機能の動作が停止する。内部はリセット状態となる。
【０１３８】
ただし、規定の電圧が与えられている限り、ＲＡＭ１、ＲＡＭ２、ＲＡＭＰの内容は保持される。また、入出力ポートの状態も保持される。そして、ＮＭＩ割込要求が発生するとクリア状態となる。なお、内部はリセット状態となるためにＮＭＩ以外の割込要求は発生しない。
【０１３９】
このソフトウェアスタンバイ状態に遷移するためには、一方のＣＰＵがＳＳＢＹビットを“１”にセットし、ＳＬＥＥＰ命令を実行すればよい。他方のＣＰＵの状態に応じて、直ちにソフトウェアスタンバイ状態に遷移するか、一旦スリープ状態に遷移した後、他方のＣＰＵがＳＬＥＥＰ命令を実行した後にソフトウェアスタンバイ状態に遷移するかが自動的に選択される。このため、プログラムを作成する場合に、相互の動作状態を確認する必要がなく、プログラムの作成効率を向上することができる。
【０１４０】
また、割込処理を開始したとき、直前が動作中であったか、スリープ状態であったかを示すビットを設けるとよい。この動作中に割込を受け付けた場合には、ＣＰＵの内部のレジスタの内容を退避しなければならないが、スリープ中に割込を受け付ければ、ＣＰＵの内部のレジスタには作業中のデータはないので退避する必要がない。この退避動作および処理終了時の復帰動作を行わなければ、高速化を行うことができる。
【０１４１】
さらに、入出力ポートは、いずれのＣＰＵからライト可能にするか選択可能にする。
【０１４２】
次に、図８により入出力ポートのレジスタを詳細に説明する。
【０１４３】
この入出力ポートのレジスタは、データディレクションレジスタ（ＤＤＲ）、データレジスタ（ＤＲ）、ポート制御レジスタ（ＰＳＥＬ）からなる。
【０１４４】
ＤＤＲは、ライト専用レジスタであり、“０”にクリアされているときに入力、“１”にセットされているときには出力となる。
【０１４５】
ＤＲは、出力データを格納する。このＤＤＲを“１”にセットすると、ＤＲの内容が出力される。リード時にはＤＲの内容または端子の状態が読み出される。すなわち、ＤＤＲが“０”にクリアされているときは端子の状態、“１”にセットされているときにはＤＲの内容が読み出される。
【０１４６】
ＰＳＥＬが、各入出力端子の制御をいずれのＣＰＵで行うかを選択する。このポート制御レジスタ（ＰＳＥＬ）の制御ビットは、データレジスタ（ＤＲ）とデータディレクションレジスタ（ＤＤＲ）のビットを共通に制御する。ＰＳＥＬが“０”にクリアされているときはＣＰＵ１によって、“１”にセットされているときにはＣＰＵ２によってライトが行われる。
【０１４７】
なお、ポートにプルアップＭＯＳを内蔵したり、２重出力バッファとしたりする場合、これらの制御を行うレジスタも、ＰＳＥＬで共通に制御すればよい。このようなレジスタの例は、前記平成５年３月、（株）日立製作所発行『Ｈ８／３００３ ハードウェアマニュアル』Ｐ２６３〜Ｐ３０６、Ｐ４１９〜Ｐ４４５に記載されている。
【０１４８】
次に、図９により入出力ポートを詳細に説明する。
【０１４９】
本実施例の入出力ポートにおいては、データディレクションレジスタ（ＤＤＲ）、データレジスタ（ＤＲ）、ポート制御レジスタ（ＰＳＥＬ）はフリップフロップで構成される。いずれも、内部データバスの所定のビットをデータ入力（Ｄ）とし、リセット信号（ＲＥＳＥＴ）をクリア入力（ＣＬＲ）としている。
【０１５０】
ＤＤＲの入力クロック（Ｃ）は、論理積回路ＡＮＤ１の出力である。この出力（Ｑ）は、出力バッファＯＢＵＦの制御信号およびセレクタＳＥＬ１の選択信号とされる。
【０１５１】
ＤＲの入力クロック（Ｃ）は、論理積回路ＡＮＤ２の出力である。この出力（Ｑ）は出力バッファＯＢＵＦのデータ入力およびセレクタ１のデータ入力とされる。
【０１５２】
ＰＳＥＬの入力クロック（Ｃ）は、ＰＳＥＬリード信号ＷＲＰＳＥＬである。この出力（Ｑ）はセレクタＳＥＬ２の選択信号とされる。
【０１５３】
出力バッファＯＢＵＦは、制御信号としてＤＤＲ出力、データ入力はＤＲ出力とされ、出力信号は端子Ｐに接続される。
【０１５４】
入力バッファＩＢＵＦは、入力信号が端子Ｐに接続され、出力信号がセレクタＳＥＬ１のデータ入力とされる。
【０１５５】
セレクタＳＥＬ１は、ＤＤＲ出力を選択信号、ＤＲ出力および入力バッファＩＢＵＦ出力をデータ入力とする。このＤＤＲ出力が“０”のときは入力バッファＩＢＵＦ出力が選択され、ＤＤＲ出力が“１”のときにはＤＲ出力が選択される。このセレクタＳＥＬ１の出力はＤＲリードバッファの入力とされる。
【０１５６】
セレクタＳＥＬ２は、ＰＳＥＬ出力を選択信号、ＣＰＵ１／２バス権信号をデータ入力とする。この出力はライト許可信号となる。ＰＳＥＬが“０”のときはＣＰＵ１バス権で、ＣＰＵ１がライト許可状態となる。ＰＳＥＬが“１”のときにはＣＰＵ２バス権で、ＣＰＵ２がライト許可状態となる。
【０１５７】
ＤＲリードバッファＤＲＢＵＦは、セレクタＳＥＬ１の出力を入力し、ＤＲリード信号ＲＤＤＲをクロックとし、出力信号は内部データバスの所定のビットに接続される。このＲＤＤＲが活性状態のとき、セレクタＳＥＬ１の出力を内部データバスに出力する。
【０１５８】
ＰＳＥＬリードバッファＰＳＢＵＦは、ＰＳＥＬフリップフロップの出力を入力し、ＰＳＥＬリード信号ＲＤＰＳＥＬをクロックとし、出力信号は内部データバスの所定のビットに接続される。このＲＤＰＳＥＬが活性状態のとき、ＰＳＥＬフリップフロップの出力を内部データバスに出力する。
【０１５９】
論理積回路ＡＮＤ１は、ライト許可信号とＤＤＲライト信号ＷＲＤＤＲを入力とし、出力信号はＤＤＲの入力クロックとなる。
【０１６０】
論理積回路ＡＮＤ２は、ライト許可信号とＤＲライト信号ＷＲＤＲを入力とし、出力信号はＤＲの入力クロックとなる。
【０１６１】
ＲＯＭ１およびＲＯＭ２をＰＲＯＭとすることができ、このＰＲＯＭを外部からプログラムするとき、２つのＲＯＭを外部から連続したアドレスとするようにするとよい。
【０１６２】
次に、図１０によりＰＲＯＭのアドレスマップを説明する。
【０１６３】
たとえば、ＰＲＯＭ１は６４ｋバイト、ＰＲＯＭ２は３２ｋバイトとする。ＭＣＵモードでは、ＰＲＯＭ１はＨ’００００００００〜Ｈ’００００ＦＦＦＦに、ＰＲＯＭ２はＨ’００００〜Ｈ’７ＦＦＦに配置される。
【０１６４】
また、ＰＲＯＭモードでは、ＰＲＯＭ１はＨ’０００００〜Ｈ’０ＦＦＦＦに、ＰＲＯＭ２はＨ’１００００〜Ｈ’１７ＦＦＦに配置される。
【０１６５】
次に、図１１によりＰＲＯＭモードを詳細に説明する。
【０１６６】
このＰＲＯＭモードは、モード端子ＭＤ１、ＭＤ０、およびＳＴＢＹ端子をいずれもロウレベルとすることによって設定される。このとき、図示はされないモード設定回路によって、内部信号ＥＰＭが活性状態（ハイレベル）とされる。このＰＲＯＭモードのときには、ＣＰＵ１／２はＢＵＦＣ１／２によって、アドレスバス、データバスから切り離される。
【０１６７】
図１１において、ＣＳ制御回路、バッファＢＵＦＣ１／２などはバスコントローラに含まれてなる。
【０１６８】
ＰＲＯＭは、図１におけるＲＯＭ１およびＲＯＭ２とし、メモリアレイ、アドレスデコーダ、入出力回路、制御回路からなる。このアドレスデコーダにはアドレスが入力され、入出力回路はデータの入出力を行い、また制御回路は制御信号を入力し、入出力回路を制御してデータの書込み／読み出しなどを行う。また、メモリアレイは不揮発記憶素子が配列されている。
【０１６９】
制御回路には、ＥＰＭ、ＣＳ−１／２＃、ＯＥ＃、ＰＧＭ＃、およびＭＳ−１／２＃、リード信号が入力される。このＥＰＭが活性状態のとき、ＰＲＯＭとしての書込み／読み出し動作が、ＣＳ−１／２＃、ＯＥ＃、ＰＧＭ＃に基づいて行われる。また、ＥＰＭが非活性状態のときには、ＣＰＵのアドレス空間上でのＲＯＭとしての読み出し動作が、ＭＳ−１／２＃、リード信号に基づいて行われる。
【０１７０】
ＰＲＯＭモードのとき、ＶＰＰ、ＣＳ＃、ＯＥ＃、ＰＧＭ＃で制御される。このような制御は、たとえば１９９３年３月、（株）日立製作所発行『ＨＩＴＡＣＨＩ ＩＣ Ｍｅｍｏｒｙ Ｄａｔａ Ｂｏｏｋ Ｎｏ．２（１０ｔｈ Ｅｄｉｔｉｏｎ）』Ｐ５１０〜Ｐ５２４に記載されるＰＲＯＭと同様である。
【０１７１】
ＶＰＰ端子はＲＥＳ端子と、ＣＳ＃、ＯＥ＃、ＰＧＭ＃はＰ６１、Ｐ６２、Ｐ６３端子と、アドレスＡ０−１５はＰ００−０７、Ｐ１０−１７端子と、Ａ１６はＰ６０端子と、データＤ７−０はＰ４０−Ｐ４７端子と兼用にされている。なお、ＶＰＰは図示はされないが、ＰＲＯＭ１／２に与えられる。
【０１７２】
内部信号としては、ＯＥ＃、ＰＧＭ＃がバッファ回路を介して入力され、ＰＲＯＭ１、ＰＲＯＭ２に供給される。ＣＳ−１＃は、アドレス上位信号Ａ１６の反転信号との論理積信号、ＣＳ−２＃は、アドレス上位信号Ａ１５の反転信号、およびＡ１６との論理積信号で生成される。このＣＳ−１＃、ＣＳ−２＃が、それぞれＰＲＯＭ１、ＰＲＯＭ２に与えられる。
【０１７３】
ＰＲＯＭモードのとき、ＩＤＢ１とＩＤＢ２がバッファを介して接続される。ＰＲＯＭ２のデータはＩＤＢ２、ＩＤＢ１およびＩＯＰ３を介して入出力される。すなわち、ＣＳ−２＃が活性状態で読み出し動作のとき、ＰＲＯＭ２から読み出したＩＤＢ２の内容がＩＤＢ１に出力される。さらに、読み出し動作のとき、ＩＤＢ１の内容がＩＯＰ３を介して外部に出力される。
【０１７４】
また、書込み動作のとき、外部の内容がＩＯＰ３を介してＩＤＢ１に入力される。ＣＳ−２＃が活性状態で書込み動作のとき、ＩＤＢ１の内容がＩＤＢ２に出力され、ＰＲＯＭ２に与えられる。さらに、ＩＤＢ１の内容がＩＯＰ３を介して外部に出力される。
【０１７５】
ＰＲＯＭモードのとき、ＩＡＢ１とＩＡＢ２がバッファを介して接続される。すなわち、ＩＯＰ１、２を介して入力されたＩＡＢ１のアドレスが、ＩＡＢ２に入力され、ＰＲＯＭ２に与えられる。なお、ＰＲＯＭ１／２の最大容量が６４ｋバイトであるので、それぞれのＰＲＯＭに与えられるアドレスは１６ビットである。
【０１７６】
たとえば、読み出し動作はＣＳ−１／２＃、ＯＥ＃が活性状態、ＰＧＭ＃が非活性状態のときに行われ、書込み動作はＣＳ−１／２＃、ＰＧＭ＃が活性状態、ＯＥ＃が非活性状態のときに行われる。
【０１７７】
その他、ベリファイやページ書込みなどが可能とされるが、本発明には直接の関係はないので、詳細な説明は省略する。
【０１７８】
１つのＰＲＯＭモードで、ＰＲＯＭ１、ＰＲＯＭ２を、外面的には１つのＰＲＯＭとして一括して書込むことができる。これによって、書込みを効率的に行うことができる。
【０１７９】
次に、図１２によりテストモードを詳細に説明する。
【０１８０】
このテストモードは、モード端子ＭＤ１、ＭＤ０をいずれもロウレベル、およびＳＴＢＹ端子をハイレベルとすることによって設定される。このとき、図示はされないモード設定回路によって、内部信号ＴＭが活性状態（ハイレベル）とされる。
【０１８１】
図１２において、制御回路１／２、バス権調停回路、選択回路、バッファＢＳＢＵＦ、バッファＢＵＦＣ１／２はバスコントローラに含まれてなる。
【０１８２】
バス権調停回路は、ＣＰＵ１／２のいずれが、ＰＡＢ／ＰＤＢを使用するかを選択して制御信号ＰＡＫを出力する。このＰＡＫがハイレベルのときはＣＰＵ１、ＰＡＫがロウレベルのときにはＣＰＵ２がＰＡＢ／ＰＤＢを使用する。テストモードの場合は、Ｐ６２端子から与えられる選択信号によってＰＡＫ信号は制御される。
【０１８３】
テストモードのとき、ＣＰＵ１／２はＢＵＦＣ１／２によって、アドレスバス、データバス、リード信号／ライト信号から切り離される。
【０１８４】
アドレスはＩＯＰ３〜ＩＯＰ０から、バッファＢＵＦＰを介してＩＡＢ１に入力され、さらにＢＳＢＵＦを介してＩＡＢ２およびＰＡＢに入力される。なお、ＩＡＢ１は４Ｇバイトのアドレス空間に対応して３２本のアドレスを有するが、ＩＡＢ２は６４ｋバイトのアドレス空間に対応して１６本、ＰＡＢはＲＡＭＰ、Ｉ／Ｏのアドレスに対応して１０本のアドレスを有する。従って、外部からアドレスを与えるためにはＩＡＢ１を利用するのがよい。
【０１８５】
データバスは、ＩＯＰ４によって、バッファＢＵＦＰを介してＩＤＢ１と入出力される。リード／ライト動作およびアドレスに対応して、ＩＤＢ２またはＰＤＢの内容がＢＳＢＵＦを介してＩＤＢ１と入出力される。
【０１８６】
リード信号、ライト信号は、Ｐ６０端子、Ｐ６１端子からＢＵＦＰを介して入力される。ＲＤ１／２、ＷＲ１／２として、ＲＯＭ１、ＲＡＭ１／ＲＯＭ２、ＲＡＭ２に供給される。また、バス権信号ＰＡＫによって選択されてＲＤＰ、ＷＲＰとなって、ＲＡＭＰ、Ｉ／Ｏに供給される。テストモードにおいては、ＰＡＫ信号によらず、ＲＤ１／２／Ｐは常に同様の動作となり、ＷＲ１／２／Ｐも常に同様の動作となる。
【０１８７】
制御回路１／２は、ＩＡＢ１／２のアドレスに基づいて、選択信号ＭＳＲＯＭ１／２、ＭＳＲＡＭ１／２、ＭＳＲＡＭＰ、ＭＳＩＯを出力する。ＭＳＲＡＭＰ、ＭＳＩＯは共通信号であるので、ＰＡＫ信号に基づいて、一方が出力、他方はハイインピーダンスとなる。たとえば、ＰＡＫ信号がハイレベルのときは制御回路１が出力し、制御回路２はハイインピーダンスとなる。
【０１８８】
また、テストモード時には、ＭＳＲＯＭ１／２、ＭＳＲＡＭ１／２はＰＡＫ信号に基づいて一方が禁止される。これは外部から与えるアドレスに基づいて、１つの機能ブロックが選択されるようにするためである。たとえば、ＰＡＫ信号がハイレベルのときはＭＳＲＯＭ１、ＭＳＲＡＭ１はＩＡＢ１に基づいた出力、ＭＳＲＯＭ２、ＭＳＲＡＭ２は非活性状態とされる。
【０１８９】
ＲＯＭ１／ＲＡＭ１をテストする場合には、Ｐ６２端子をハイレベルにして、ＰＡＫ信号をハイレベルにした状態で、アドレス、リード信号／ライト信号を与えることによってリード／ライトを行うことができる。
【０１９０】
また、ＲＯＭ２／ＲＡＭ２をテストする場合には、Ｐ６２端子をロウレベルにして、ＰＡＫ信号をロウレベルにした状態で、アドレス、リード信号／ライト信号を与えることによってリード／ライトを行うことができる。このアドレスは下位１６ビットのみが有効になる。
【０１９１】
さらに、ＲＡＭＰ／Ｉ／Ｏをテストする場合には、Ｐ６２端子をハイレベルにして、ＰＡＫ信号をハイレベルにした状態で、アドレス、リード信号／ライト信号を与えることによってリード／ライトを行うことができる。
【０１９２】
上記によって、ＣＰＵによってアドレスが与えられ、かつデータの入出力が行われるべき内部バスに、内蔵の機能ブロックを外部からリード／ライトするためのアドレスデータなどを外部から供給可能にして、この機能ブロックに必要なデータのリード／ライトを外部から直接行うことができるようにし、このシングルチップマイクロコンピュータに内蔵される機能ブロックのテストの容易化、ならびにテスティング効率の向上を実現できる。
【０１９３】
また、内蔵ＲＡＭをテストする場合、データのテストは独立して行い、アドレスデコーダのテストは並行して行うようにするとよい。このアドレスデコーダのテストを行うには、ＲＡＭ１／２／Ｐを同時に選択可能にすることによって同時にテストを行うことができる。
【０１９４】
この場合に、図１２に対してＲＡＭテストモードを設ければよい。テストモードにした状態で、Ｐ６３端子をロウレベルとすると前記同様のテストモード、Ｐ６３端子をハイレベルにするとＲＡＭテストモードとなる。
【０１９５】
このＲＡＭテストモードでは、ＲＡＭ１／２／Ｐの選択信号ＭＳＲＡＭ１、ＭＳＲＡＭ２、ＭＳＲＡＭＰを同時に活性状態にすることができる。ただし、リードするデータはそれぞれ、ビット０〜１、ビット２〜３、ビット４〜７とする。
【０１９６】
ＣＰＵ１とＣＰＵ２は、実質的に同一のＣＰＵであるか、またはＣＰＵ１がＣＰＵ２を包含するようにし、ソフトウェアの開発環境を共有できるようにするのがよい。このようなＣＰＵには、たとえば特願平４ー２２６４４７号がある。
【０１９７】
以上のようなシングルチップマイクロコンピュータを評価するエミュレータは、使用者が外部からブレーク条件を設定するとき、いずれのＣＰＵにブレークを設定するかを指定可能にするとよい。また、２つのＣＰＵの条件が両方成立したときにブレークするように指定可能にするとよい。
【０１９８】
次に、図１３によりエミュレーション用プロセッサの構成を説明する。
【０１９９】
エミュレーション用プロセッサは、ＣＰＵ１、ＣＰＵ２を含むマイクロコンピュータ部分、および図示はされないバッファ回路などを含むエミュレーション用プロセッサ専用ブロックから構成され、公知の半導体製造技術によって１つの半導体基板上に形成されている。
【０２００】
このエミュレーション用プロセッサは、応用システムと信号の送受信を行うユーザインタフェース、およびマイクロコンピュータ開発装置と信号の送受信を行うエミュレーションインタフェースを有している。
【０２０１】
エミュレーション用バスとしては、ＩＡＢ１およびＩＤＢ１、ＩＡＢ２およびＩＤＢ２をエミュレーションインタフェースを介して入出力する。また、ＰＡＢおよびＰＤＢのいずれのＣＰＵが使用しているかを示すバス権表示信号を出力している。これは図１３のＰＡＫ信号に相当するものとされる。また、バス権調停によって、ＣＰＵが待機状態とされていることを示す信号を出力している。
【０２０２】
ＰＡＢ、ＰＤＢのアクセス状態は明示的には表示されないが、バス権表示信号とＩＡＢ１およびＩＤＢ１、ＩＡＢ２およびＩＤＢ２によるエミュレーション用バスの内容によって判断することができる。このＰＡＢ、ＰＤＢによるエミュレーション用バスを出力しないことによって、エミュレーション用プロセッサの端子数を削減でき、これによってパッケージサイズを小さくして、ひいてはエミュレータのサイズを縮小できる。
【０２０３】
ブレーク要求端子は、ＢＲＫ１＃、ＢＲＫ２＃の２本がエミュレーションインタフェースに含まれてなる。これに基づいてＢＲＫ１、ＢＲＫ２信号によって、それぞれＣＰＵ１、ＣＰＵ２にブレーク割込を要求する。これらは対応するＣＰＵ選択ビットを持たず、優先順位判定回路を経て、割込要求信号と並列したＣＰＵへのブレーク要求信号を活性状態にする。また、ベクタ番号信号は一般の割込要求と兼用される。
【０２０４】
ＣＰＵ１、ＣＰＵ２が、ブレーク割込を受け付けると、それぞれブレークアクノリッジ信号ＢＲＫＡＫ１、ＢＲＫＡＫ２が活性状態になる。たとえば、ＣＰＵ２が、前記のようなＳＣＩの受信処理、パルス出力処理を行っている場合、ＣＰＵ１をブレーク割込によって停止しても、ＣＰＵ２はユーザの処理を実行するためにＳＣＩの受信を中断してしまい、いわゆるオーバランエラーが発生したり、パルス出力を中断してしまい、たとえばユーザシステムのモータ駆動ができなくなってしまうようなことを回避できる。
【０２０５】
次に、図１４により、エミュレーション用プロセッサを搭載したエミュレータの構成を説明する。
【０２０６】
コネクタ部がシングルチップマイクロコンピュータの代わりに応用システム（ユーザシステム）に装着される。エミュレーション用プロセッサは、このコネクタ部とインタフェースケーブルを介し、ターゲットシステムインタフェースを用いて応用システムと信号の入出力を行う。
【０２０７】
また、エミュレーション用プロセッサはエミュレーションインタフェースを用いてエミュレーションバス１／２に接続される。このエミュレーションバス１がＩＡＢ１／ＩＤＢ１に対応し、エミュレーションバス２がＩＡＢ２／ＩＤＢ２に対応する。これらのエミュレーションバスには、図示はされない状態信号、制御信号などを含む。
【０２０８】
このエミュレーションバスを用いて、エミュレーション用プロセッサから、応用システムとエミュレーション用プロセッサの内部状態に応じた情報などが出力され、またエミュレーション用プロセッサに対し、エミュレーションのための各種制御信号が入力される。そして、エミュレーション用プロセッサの、図示はされないエミュレートモード端子が電源レベルに固定され、エミュレーション用プロセッサ内部ではエミュレートモードが設定される。
【０２０９】
また、エミュレーションバスには、特に制限はされないものの、応用システムまたはターゲットマイクロコンピュータ内蔵のメモリを代行するためのＲＡＭでなるようなエミュレーションメモリと、エミュレーション用プロセッサの制御状態やエミュレーションバスの状態を監視して、その状態が予め設定された状態に達した時に、エミュレータ専用割込を入力して、ＣＰＵによるユーザプログラムの実行を停止させ、エミュレーション用プログラム実行状態に遷移させる（ブレーク）ためのブレーク制御回路が接続される。
【０２１０】
さらに、このエミュレーションバスには、ＣＰＵのリード動作またはライト動作を示す信号、命令リード動作を示す信号などに基づき、エミュレーションバスに与えられるアドレスやデータさらには制御情報を逐次蓄えるリアルタイムトレース回路などが接続される。本実施例においては、エミュレーションバス１／２がエミュレーションメモリ、ブレーク制御回路、リアルタイムトレース回路などにそれぞれ接続される。
【０２１１】
従って、エミュレーションメモリは、ＩＡＢ１／ＩＤＢ１およびＩＡＢ２／ＩＤＢ２のデータを独立して並立的に入出力する。また、ブレーク制御回路は、ＩＡＢ１／ＩＤＢ１およびＩＡＢ２／ＩＤＢ２のアドレス／データ、その他の情報を独立に判定する。このＩＡＢ１／ＩＤＢ１側の条件が成立した後、ＩＡＢ２／ＩＤＢ２側の条件が成立したときにブレークを要求することが可能にされる。前記の通り、ブレーク割込はＣＰＵ１およびＣＰＵ２の両方に同時に要求することもできるし、一方のＣＰＵのみに要求することもできる。
【０２１２】
また、リアルタイムトレース回路は、ＩＡＢ１／ＩＤＢ１およびＩＡＢ２／ＩＤＢ２のアドレス／データ、その他の情報を独立に蓄積し、一方のＣＰＵがブレークしたときには、他方のＣＰＵのアドレス／データ、その他の情報のみを蓄積する。また、一方のＣＰＵのみのアドレス／データ、その他の情報を選択的に蓄積することもできる。
【０２１３】
このエミュレーションメモリ、ブレーク制御回路、リアルタイムトレース回路はコントロールバスに接続され、コントロールバスを介してコントロールプロセッサの制御を受けるようになっている。このコントロールバスは、エミュレーション用プロセッサ制御回路に接続されるとともに、インタフェース回路を介して、特に制限はされないものの、パーソナルコンピュータなどのシステム開発装置に接続される。
【０２１４】
たとえば、システム開発装置から入力されたプログラムをエミュレーションメモリに転送し、内蔵ＲＯＭ上に配置されるべきこのプログラムをＣＰＵがリードすると、エミュレーションメモリ上のプログラムがリードされる。また、ブレーク条件や、リアルタイムトレース条件などもシステム開発装置から与えることができる。
【０２１５】
このブレーク条件としては、少なくとも、ＣＰＵ１とＣＰＵ２の条件が独立して設定できるようにされる。また、リアルタイムトレース条件としては、少なくとも、ＣＰＵ１とＣＰＵ２のアドレス／データ、その他の情報を同時に蓄積するか、選択的に一方のＣＰＵのアドレス／データ、その他の情報のみを蓄積するかを選択できるようにする。
【０２１６】
従って、本実施例のシングルチップマイクロコンピュータによれば、データ処理装置としてのＣＰＵ１，ＣＰＵ２、バス制御手段としてのバスコントローラ、読み出し可能な記憶手段としてのＲＯＭ１，ＲＯＭ２、データ入出力手段としてのＩＯＰ０〜ＩＯＰ１１を主要な構成とすることにより、以下の作用効果を得ることができる。
【０２１７】
(1).ＣＰＵ１とＲＯＭ１を接続するＩＡＢ１，ＩＤＢ１と、ＣＰＵ２とＲＯＭ２を接続するＩＡＢ２，ＩＤＢ２とを独立に設け、ＲＯＭ１にＣＰＵ１のプログラムを、ＲＯＭ２にＣＰＵ２のプログラムを格納することにより、ＣＰＵ１とＣＰＵ２が並列動作することを可能にし、またＲＡＭＰとＩＯＰ０〜ＩＯＰ１１などによる入出力回路を共通のＰＡＢ，ＰＤＢに接続し、ＣＰＵ１およびＣＰＵ２が利用可能とすることにより、ＣＰＵ１とＣＰＵ２の制御すべきデータを任意に配分して利用することができる。これによって、シングルチップマイクロコンピュータの処理速度を向上し、資源利用効率を向上できる。
【０２１８】
(2).１つのシングルチップマイクロコンピュータで２つの処理を同時に行うことにより、従来の複数の半導体集積回路装置を利用していたシステムを代替して、小型化を実現することができる。
【０２１９】
(3).ＣＰＵ１およびＣＰＵ２が、相互に割込を要求することを可能にすることにより、容易にＣＰＵ１，２の相互の同期を実現することができる。
【０２２０】
(4).ＣＰＵ１およびＣＰＵ２の動作によって、ソフトウェアスタンバイのようなシングルチップマイクロコンピュータの全体を停止状態とする場合、ＳＳＢＹビットを“１”にセットした状態で、一方のＣＰＵがＳＬＥＥＰ命令を実行したときに、他方のＣＰＵの状態に応じて、直ちにソフトウェアスタンバイ状態に遷移するか、一旦スリープ状態に遷移した後、他方のＣＰＵがＳＬＥＥＰ命令を実行した後にソフトウェアスタンバイ状態に遷移するかが自動的に選択することによって、プログラムを作成する場合に、相互の動作状態を確認する必要がなく、プログラムの作成効率を向上することができる。
【０２２１】
(5).ＩＯＰ０〜ＩＯＰ１１をビット単位で、いずれのＣＰＵ１，２が利用するかを指定するレジスタＤＲを設けることにより、１本の入出力ポートを２つのＣＰＵ１，２で利用することができ、資源の利用効率をより向上することができる。
【０２２２】
(6).割込を、いずれのＣＰＵ１，２に要求するかを指定するレジスタを割込許可回路に設けることにより、入出力回路を２つのＣＰＵ１，２で任意に配分して利用することができ、資源の利用効率をより向上することができる。
【０２２３】
(7).一方のＣＰＵを、主に割込によるデータ転送を行うことに使用することにより、割込時の種々の処理を容易に行うことができる。
【０２２４】
(8).ＲＯＭ１，２をＰＲＯＭで構成した場合、ＰＲＯＭモード時にはＲＯＭ１とＲＯＭ２を連続したアドレスに配置することにより、ＲＯＭ１とＲＯＭ２を１つのＰＲＯＭと互換性を持たせ、ＰＲＯＭ書込みを効率化することができる。
【０２２５】
(9).１つの物理的アドレスに対応して、ＣＰＵ１，２毎に異なる論理的アドレスを有する場合、または異なるＣＰＵ１，２の１つの論理的アドレスに対応して、異なる物理的アドレスを有する場合に、いずれの論理アドレスを使用するかを選択する制御信号を与えることによって、ＣＰＵ１，２によってアドレスが与えられ、かつデータの入出力が行われるべき複数の内部バスに、外部から内蔵の機能ブロックをリード／ライトするためのアドレスデータなどを前記内部バスより少ないバッファ回路を介して供給可能にして、この機能ブロックに必要なデータのリード／ライトを外部から直接行うことができるようにし、このシングルチップマイクロコンピュータに内蔵される機能ブロックのテストの容易化、ならびにテスティング効率の向上を実現できる。
【０２２６】
(10). ＣＰＵ１とＣＰＵ２の互換性を持たせることにより、開発効率を向上することができ、またサポートツールを共通化することを可能にし、開発装置の開発効率を向上することができる。これにより、使用者が必要とする開発装置の数を低減し、開発装置に必要な費用を低減することができる。
【０２２７】
(11). このシングルチップマイクロコンピュータのエミュレータにおいては、２つのＣＰＵ１，２を独立に停止する割込を有することにより、デバック効率を向上することができる。
【０２２８】
また、本実施例においては、図１５に示すように、図１のシングルチップマイクロコンピュータに対して、ダイレクトメモリアクセスコントローラ（ＤＭＡＣ）がＣＰＵ１と同様にＩＡＢ１，ＩＤＢ１に接続されて追加されることにより、ＣＰＵ１とＤＭＡＣを、バスコントローラのバス権調停に基づいて互いに排他的に動作させることができる。
【０２２９】
すなわち、ＤＭＡＣは、起動要因として、ＣＰＵ１が所定の制御ビットを“１”にセットすることによって、データ転送を行うオートリクエストや、ＤＭＡ要求端子に所定の信号が与えられたときに、データ転送を行う外部リクエスト機能を持ち、また転送モードとして、オートリクエストのとき、ＣＰＵ１を停止してバスを専有してデータ転送を行うバーストモードや、１回の転送毎にバス権を解放してＣＰＵ１と交互に動作しつつ、データ転送を行うサイクルスチールモードを持つことにより可能となる。
【０２３０】
また、割込要求信号を起動要求信号として、データ転送を行うことができ、ＣＰＵ２が割込でデータ転送を行うより高速のデータ転送が可能である。
【０２３１】
さらに、バス調停は、リード／ライトの競合時に行うほか、時分割で動作するようにしてもよい。たとえば、８ステート毎にＣＰＵ１およびＣＰＵ２にバス権を与える。また、８ステート間にバスが終了しなかった場合には、終了するまで動作する。たとえば、ＣＰＵ１には４ステート、ＣＰＵ２には１２ステートずつバス権を与えてもよい。
【０２３２】
（実施例２）
図１６は本発明の他の実施例であるシングルチップマイクロコンピュータを示すブロック図、図１７は本実施例のシングルチップマイクロコンピュータにおけるバスの動作タイミング図である。
【０２３３】
本実施例のシングルチップマイクロコンピュータは、実施例１に対して、ＩＡＢ１とＩＡＢ２、ＩＤＢ１とＩＤＢ２が共通化されてＩＡＢ／ＩＤＢとされ、データバス幅を３２ビットとし、同様にＲＯＭ１とＲＯＭ２、ＲＡＭ１とＲＡＭ２が共通化されてリードオンリメモリ（ＲＯＭ：読み出し可能な記憶手段）／ランダムアクセスメモリ（ＲＡＭ）とされ、これらは３２ビット同時にリード／ライト可能にしている。
【０２３４】
また、ＣＰＵ１（第１のデータ処理装置）およびＣＰＵ２（第２のデータ処理装置）は時分割で、内部アドレスバス（ＩＡＢ）／内部データバス（ＩＤＢ）を利用して、ＲＯＭ／ＲＡＭをリード／ライトする。前記の通り、これらのＣＰＵ１／２の命令は１６ビット単位であり、最小命令を１ステートで実行する。
【０２３５】
すなわち、１つのＣＰＵ１／２に対して、命令については１６ビットを１ステートでリードして、命令リード量と命令実行量が同等となる。３２ビットで命令をリードすれば、命令リードの回数を半分にして、ＩＡＢ／ＩＤＢおよびＲＯＭ／ＲＡＭの使用頻度を１／２とすることができる。従って、ＣＰＵ１およびＣＰＵ２が交互にＩＡＢ／ＩＤＢを利用してＲＯＭから命令を読み出すことができ、並列に実行可能とすることができる。
【０２３６】
実際には、分岐命令などのように３２ビットで命令をリードしても、１６ビットが無駄になってしまったり、データアクセスのときには使用頻度を減らせなっかたりして完全な並列動作はできないが、前記の通り命令のリード回数が多く、本実施例によっても、実施例１に対して処理速度をそれほど低下させることがない。また、ＲＯＭ／ＲＡＭを共通化することによって、物理的規模を低下させたり、ＣＰＵ１／２の使用するメモリ容量を任意に設定したりすることができる。
【０２３７】
次に、図１７により内部バスの動作タイミングの一例を説明する。
【０２３８】
なお、ＣＰＵ１／２のプログラムは図６と同様であり、バスの使用権は、前回バスを使用していたＣＰＵ１／２が非優先とされ、そのほかの場合にはＣＰＵ２を優先するものとする。
【０２３９】
たとえば、ＩＡＢ１／２は、φ＃に同期して出力され、またＣＰＵ１／２のＲＯＭおよびＲＡＭに対するリードは、３２ビット一括して１ステートで行われる。ただし、これは４の倍数番地から始まる３２ビットデータに限定される。
【０２４０】
まず、ＩＡＢ１／２はφ＃に同期して、１ステート出力され、特に制限はされないものの、ＲＯＭおよびＲＡＭの中でφに同期してラッチされる。これに対応するリードデータはφ＃に同期して出力され、φ＃が活性状態の期間にＣＰＵ１／２に取り込まれる。
【０２４１】
また、前記同様に、ＲＡＭＰに対するリード／ライトは２ステート、Ｉ／Ｏに対するリード／ライトは３ステートで行われる。φ＃に同期したＩＡＢ１／２は、バスコントローラでφに同期化される。この場合に、先頭命令の存在するアドレスｍ、ｎは４の倍数番地とされる。
【０２４２】
Ｔ１では、ＣＰＵ１／２のＲＯＭからの命令フェッチが要求されるが、ＣＰＵ２の命令フェッチが優先され、ＩＡＢにアドレスｍが出力される。
【０２４３】
Ｔ２では、ＲＯＭからＩＤＢに読み出された命令コード（ＢＣＬＲ命令の第１、第２ワード）をＣＰＵ２が取り込むとともに、ＣＰＵ１の命令フェッチのアドレスｎがＩＡＢに出力される。
【０２４４】
Ｔ３では、ＲＯＭからＩＤＢに読み出された命令コード（ＣＭＰ、ＢＥＱ命令）をＣＰＵ１が取り込むとともに、ＣＰＵ２はアドレスＳＳＲをＩＡＢに出力する。自動的に、ＣＰＵ２のＰＡＢ／ＰＤＢの使用が許可される。この場合に、ＳＣＩのリードが３ステート必要であるため、ＣＰＵ２待機信号がハイレベルになる。
【０２４５】
Ｔ４では、ＩＡＢの内容がＰＡＢに出力されて、ＳＣＩのレジスタＳＳＲの内容がリードされる。このリードデータはＴ６で得られる。一方、ＣＰＵ１が命令フェッチを要求するが、ＣＰＵ２がバスを使用中であるので、保留とされ、ＣＰＵ１待機信号がハイレベルになる。
【０２４６】
Ｔ５では、ＣＰＵ１／２ともに待機状態とされる。
【０２４７】
Ｔ６では、ＳＣＩのレジスタＳＳＲから読み出されたデータをＰＤＢ、ＩＤＢを介してＣＰＵ２が取り込む。また、ＣＰＵ２は次の命令フェッチを要求するが、ＣＰＵ１の命令フェッチが優先され、ＣＰＵ１待機信号がロウレベルとなり、ＣＰＵ２待機信号ハイレベルのままである。この場合に、ＣＰＵ１の命令フェッチのアドレスｎ＋４をＩＡＢに出力する。
【０２４８】
Ｔ７では、ＲＯＭからＩＤＢに読み出された命令コード（ＢＴＳＴ命令の第１ワード）をＣＰＵ１が取り込む。この場合に、ＣＰＵ１は分岐先命令のフェッチを要求するが、ＣＰＵ２の命令フェッチが優先され、ＣＰＵ２待機信号がロウレベルとなり、ＣＰＵ１待機信号ハイレベルになる。
【０２４９】
Ｔ８では、ＲＯＭからＩＤＢに読み出された次の命令コードをＣＰＵ２が取り込む。この場合に、ＣＰＵ１待機信号がロウレベルとなり、ＣＰＵ１の命令フェッチのアドレスＮ１をＩＡＢに出力する。
【０２５０】
Ｔ９では、ＲＯＭからＩＤＢに読み出された命令コードをＣＰＵ１が取り込むが、これは分岐条件が不成立で実行されない。先にフェッチ済みのＢＴＳＴ命令の第１ワードが有効になる。この場合に、ＣＰＵ１は次の命令フェッチを要求するが、ＣＰＵ２が優先され、ＣＰＵ１待機信号ハイレベルになる。
【０２５１】
一方、ＣＰＵ２はアドレスＳＳＲをＩＡＢに出力する。自動的に、ＣＰＵ２のＰＡＢ／ＰＤＢの使用が許可される。ここで、ＳＣＩのリードが３ステート必要であるため、ＣＰＵ２待機信号がハイレベルになる。
【０２５２】
Ｔ１０では、ＩＡＢの内容がＰＡＢに出力され、ＣＰＵ２はアドレスＳＳＲにライトすべきデータをＩＤＢ経由ＰＤＢに出力する。ここで、ＣＰＵ１は待機状態とされる。
【０２５３】
Ｔ１１では、ＣＰＵ２待機信号がロウレベルになる。
【０２５４】
Ｔ１２では、ＣＰＵ１待機信号がロウレベルとなり、ＣＰＵ１の命令フェッチのアドレスｎ＋６をＩＡＢに出力する。
【０２５５】
Ｔ１３では、ＲＯＭからＩＤＢに読み出された命令コード（ＢＴＳＴ命令の第２ワード）をＣＰＵ１が取り込む。この場合に、ＣＰＵ１はアドレスＰＯＲＴのリードを要求し、ＣＰＵ２はＲＯＭからの命令フェッチを要求するが、ＣＰＵ２が優先され、ＣＰＵ１待機信号ハイレベルになる。ここで、ＩＡＢにＣＰＵ２の命令フェッチのアドレスｍ＋８が出力される。
【０２５６】
Ｔ１４では、ＲＯＭからＩＤＢに読み出された次の命令コードをＣＰＵ２が取り込む。この場合に、ＣＰＵ１はアドレスＰＯＲＴをＩＡＢに出力する。ここで、入出力ポートのリードが３ステート必要であるため、ＣＰＵ１待機信号が再度ハイレベルとなる。
【０２５７】
Ｔ１５では、ＩＡＢの内容がＰＡＢに出力されて、入出力ポートのレジスタＰＯＲＴの内容がリードされる。このリードデータはＴ１７で得られる。一方、ＣＰＵ２が命令フェッチを要求するが、ＣＰＵ１がバスを使用中であるので、保留とされ、ＣＰＵ２待機信号がハイレベルになる。
【０２５８】
以上のように、本実施例においては、図６の実施例１に比較して、実行時間が長くなっているが、少なくとも１つのＣＰＵ１／２で実現する場合よりも短くできる。
【０２５９】
まず、割込やサブルーチン分岐などでＣＰＵ１／２の内部状態を退避したり、復帰したりする作業を除くことができる。また、２つのＣＰＵ１／２を単純に交互に動作するよりも短くできる。これは、ＲＯＭからＣＰＵ１／２が単位時間に実行できるより大きい量の命令を単位時間にリード可能にし、バスを使用しないでよい時間を作り、これを他方のＣＰＵ１／２が利用可能としているためである。
【０２６０】
これは、内蔵のＲＯＭにプログラムを配置する場合に特に有効であり、ＣＰＵがリード／ライトする大部分が命令のリードであることと、内部のメモリは外部のメモリに対して読み出し速度を向上しやすいこと、バスの幅を容易に広げられるためである。
【０２６１】
このとき、ＣＰＵ２は、前記ＤＭＡＣやＤＴＣのようなデータ処理装置またはデータ転送装置であっても、同様にＣＰＵ１の処理速度を低下することを最小限として、データ転送を行うことができる。特に、データ転送に先立って転送情報をＲＡＭから読み出す必要がある前記ＤＴＣに特に有効である。
【０２６２】
従って、本実施例のシングルチップマイクロコンピュータによれば、データ処理装置としてのＣＰＵ１，ＣＰＵ２、読み出し可能な記憶手段としてのＲＯＭを主要な構成とし、ＩＡＢ／ＩＤＢ、ＲＯＭ／ＲＡＭを共通化することにより、実施例１に加えて以下の作用効果を得ることができる。
【０２６３】
すなわち、ＣＰＵ１／２が単位時間に実行できる命令のバイト数より、大きなバイト数を単位時間でリード可能なＩＡＢ／ＩＤＢに、複数のＣＰＵ１／２を接続することにより、複数のＣＰＵ１／２が時分割的にＩＡＢ／ＩＤＢを利用して実質的に並立動作を可能にし、また共通のＲＯＭ／ＲＡＭを任意に配分して利用し、シングルチップマイクロコンピュータの処理速度を向上し、資源利用効率を向上することができる。
【０２６４】
以上、本発明者によってなされた発明を実施例１および２に基づき具体的に説明したが、本発明は前記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
【０２６５】
たとえば、バスの具体的な回路構成についても種々変更可能であり、ＩＡＢ１、ＩＤＢ１とＰＡＢ、ＰＤＢを直結してもよい。この場合には、ＣＰＵ１とＣＰＵ２が並立的にプログラムを読み出して実行できるようにすればよく、これによって相互に動作を制約する頻度が高くなるが、物理的規模を縮小できる場合がある。
【０２６６】
また、ＲＡＭ１、ＲＡＭ２、ＲＡＭＰを１つの機能ブロックとしてもよい。
【０２６７】
さらに、ＣＰＵの数も３個以上にすることができ、この場合には複数のＣＰＵを第１のバスに接続して、バスを時分割で利用し、さらに別の単数または複数のＣＰＵを第２のバスに接続してもよい。
【０２６８】
また、内蔵のＲＯＭはマスクＲＯＭ、ＰＲＯＭの他、ＥＥＰＲＯＭ、フラッシュメモリなどのＣＰＵが実行すべきプログラムを格納するメモリであればよい。このＲＯＭ１とＲＯＭ２が異なっていてもよい。
【０２６９】
さらに、タイマ、ＳＣＩなどの割込を要求する機能ブロックあるいはパルス出力回路などの割込処理の対象となる機能ブロックの種類、機能、数などには何等制約されない。
【０２７０】
以上の説明では、主として本発明者によってなされた発明をその利用分野であるシングルチップマイクロコンピュータに適用した場合について説明したが、これに限定されるものではなく、その他の半導体集積回路装置にも適用可能であり、本発明は、少なくとも複数のデータ処理装置を内蔵した半導体集積回路装置に適用することができる。
【０２７１】
【発明の効果】
本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下のとおりである。
【０２７２】
(1).２つのデータ処理装置に並立したバスによって独立した２つの読み出し可能な記憶手段に格納した命令をリード可能にしたり、バスの幅を拡張してデータ処理装置が単位時間に実行可能な命令数以上の命令をリード可能にして、２つのデータ処理装置を並立的に動作可能な命令を供給する機能を内蔵するシングルチップマイクロコンピュータまたは半導体集積回路装置において、複数の記憶手段を同時に選択可能とし、複数の記憶手段の同時書込みまたは同時読み出しを行うことによって割込によるデータ処理のチャネル数の制約をなくし、さらにデータ処理内容を任意とすることができるので、任意の転送処理の実現、物理的規模の縮小、転送チャネル数の制約解除、あるいはシングルチップマイクロコンピュータまたは半導体集積回路装置の製造費用の削減が可能となる。
【０２７３】
(2).前記(1) により、第１、第２のデータ処理装置を同時に動作させることができるので、シングルチップマイクロコンピュータまたは半導体集積回路装置の処理速度の向上が可能となる。
【０２７４】
(3).前記シングルチップマイクロコンピュータまたは半導体集積回路装置のエミュレーション用プロセッサ、さらにエミュレータによれば、２つのデータ処理装置を独立に停止させることができるので、デバック効率の向上を図ることが可能となる。
【図面の簡単な説明】
【図１】本発明の実施例１であるシングルチップマイクロコンピュータを示すブロック図である。
【図２】実施例１のシングルチップマイクロコンピュータにおける全体のアドレスマップの説明図である。
【図３】実施例１におけるシングルチップマイクロコンピュータのバスの接続状態のブロック図である。
【図４】実施例１における割込コントローラの概略ブロック図である。
【図５】実施例１における割込要求ビットおよび割込許可回路の概略ブロック図である。
【図６】実施例１におけるバスの動作タイミング図である。
【図７】実施例１における低消費電力状態制御回路の概略ブロック図である。
【図８】実施例１における入出力ポートを制御するレジスタ構成の説明図である。
【図９】実施例１における入出力ポートの概略ブロック図である。
【図１０】実施例１におけるＰＲＯＭのアドレスマップである。
【図１１】実施例１におけるＰＲＯＭモードの主要部のブロック図である。
【図１２】実施例１におけるテストモードの主要部のブロック図である。
【図１３】実施例１におけるエミュレーション用プロセッサの概略ブロック図である。
【図１４】実施例１におけるエミュレータの概略ブロック図である。
【図１５】実施例１におけるシングルチップマイクロコンピュータの変形例を示すブロック図である。
【図１６】本発明の実施例２であるシングルチップマイクロコンピュータを示すブロック図である。
【図１７】実施例２のシングルチップマイクロコンピュータにおけるバスの動作タイミング図である。
【符号の説明】
ＣＰＵ１ 中央処理装置（第１のデータ処理装置）
ＣＰＵ２ 中央処理装置（第２のデータ処理装置）
ＲＯＭ１ リードオンリメモリ（第１の読み出し可能な記憶手段）
ＲＯＭ２ リードオンリメモリ（第２の読み出し可能な記憶手段）
ＲＡＭ１，ＲＡＭ２，ＲＡＭＰ ランダムアクセスメモリ
ＳＣＩ シリアルコミュニケーションインタフェース
Ａ／Ｄ Ａ／Ｄ変換器
ＩＯＰ０〜ＩＯＰ１１ 入出力ポート（データ入出力手段）
ＩＡＢ１ 内部アドレスバス（第１のバス）
ＩＡＢ２ 内部アドレスバス（第２のバス）
ＰＡＢ 内部アドレスバス（第３のバス）
ＩＤＢ１ 内部データバス（第１のバス）
ＩＤＢ２ 内部データバス（第２のバス）
ＰＤＢ 内部データバス（第３のバス）
ＤＭＡＣ ダイレクトメモリアクセスコントローラ
ＲＯＭ リードオンリメモリ（読み出し可能な記憶手段）
ＲＡＭ ランダムアクセスメモリ
ＩＡＢ 内部アドレスバス
ＩＤＢ 内部データバス[0001]
[Industrial application fields]
The present invention relates to a semiconductor integrated circuit device. For example, data transfer by a large number of interrupts in a single chip microcomputer and unique processing for each user can be performed, and the processing efficiency can be improved. The present invention relates to a semiconductor integrated circuit device capable of improving the debugging efficiency of a computer, and a technology effective when applied to an emulation processor and an emulator thereof.
[0002]
[Prior art]
For example, as described in “LSI Handbook” P540 and P541 issued by Ohm Co., Ltd. on November 30, 1984, a single-chip microcomputer is a ROM for holding a program centering on a central processing unit (CPU). Functional blocks such as a read only memory (RAM), a data holding RAM (random access memory), and an input / output circuit for inputting and outputting data are formed on one semiconductor substrate.
[0003]
Such a single-chip microcomputer has a built-in direct memory access controller (DMAC) and a built-in data transfer independent of the CPU. Wear manual "or Japanese Patent Application No. 4-137554. This DMAC can be activated by an interrupt request, can perform a repeat mode, a block transfer mode, and the like, and is suitable for control of a stepping motor and printer print data. For example, transfer of up to 8 channels can be performed.
[0004]
Further, since the DMAC transfer is independent of the CPU, it is only necessary to stop the CPU for the number of cycles necessary for the data transfer, and the CPU can continue the processing being executed. For example, when transferring byte data and incrementing a transfer source / destination address, in the above example, there are 6 data transfer states including 1 dead cycle state.
[0005]
[Problems to be solved by the invention]
However, since the DMAC as described above has a transfer source address, a transfer destination address, a transfer counter, and a control register in each channel, if a plurality of channels are to be transferred, a large number of registers must be provided. In other words, the logical and physical scales of the DMAC, and thus the entire semiconductor integrated circuit device, are increased. Furthermore, the increase in scale increases manufacturing costs. That is, it is difficult to transfer all of the interrupt factors or the majority of data.
[0006]
On the other hand, such a register is disposed on a general-purpose RAM having a high storage density, and a data transfer device that prevents an increase in logical / physical scale, that is, a so-called data transfer controller (DTC) is built in Showa 63 December, "H8 / 532 Hardware Manual" published by Hitachi, Ltd. In this DTC, data transfer can be performed by substantially all interrupt factors.
[0007]
However, since the register holding the transfer information is arranged on the general-purpose RAM, prior to data transfer, this register is read into the DTC, data transfer is performed according to the read contents, and the register information updated by the data transfer is further updated. It is necessary to save to RAM. During this period, the CPU must be stopped, and much time is spent reading and saving registers compared to data transfer.
[0008]
For this reason, the processing efficiency of the entire single-chip microcomputer or semiconductor integrated circuit device is lowered. For example, when transferring byte data and incrementing the transfer source / destination address, in the above example, 30 states are required for register reading / saving for 5 data transfer states, and the CPU is stopped for a total of 35 states. Will do.
[0009]
The control of the DMAC or DTC operation is specified by the contents of the control bit of the control register, and only the transfer mode and the activation factor can be selected. If the number of control bits is increased, transfer data addition (checksum), parity calculation, and the like can be performed, but it is difficult to perform specific processing for each user. If various processes are to be realized, the logical and physical scales of the circuits that control the processes will increase.
[0010]
Of course, the CPU can be used to perform a unique process for each user associated with data transfer. For example, when an interrupt occurs, the main process is interrupted and a desired process is performed. However, the main processing to be performed by the CPU must be interrupted, and the internal state of the CPU must be saved and restored, resulting in overhead and improving the processing performance of the entire single-chip microcomputer. You will not be able to.
[0011]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a single chip microcomputer or a semiconductor integrated circuit device which can perform data transfer by a large number of interrupts and unique processing for each user and can improve processing efficiency. is there.
[0012]
It is another object of the present invention to provide an emulation processor and emulator for a semiconductor integrated circuit device capable of improving the debugging efficiency of the single chip microcomputer.
[0013]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0014]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
[0015]
That is, the semiconductor integrated circuit device of the present invention is provided with the second data processing device, and the first bus used by the first data processing device can be separated from the second bus used by the second data processing device. The bus use of the first data processing device and the bus use of the second data processing device can be performed at the same time, and further necessary for the operations of the first data processing device and the second data processing device, respectively. Functional blocks or modules connected by respective first or second buses, and in particular, a first readable storage means capable of storing a program to be executed by the first data processing device and the second data processing device. A second readable storage means is provided, and the first data processing apparatus is programmed from the first readable storage means, and the second data processing apparatus is programmed from the second readable storage means. It is obtained so as to operate by reading the beam.
[0016]
In addition, the first and second data processing devices and the readable storage means common to them are connected to each other by a bus, and the first data processing device has a larger number of instructions than the instructions that can be executed in unit time. Is read from the storage means using the bus, and the second data processing apparatus instructs the second data processing apparatus to minimize the decrease in the instruction execution speed of the first data processing apparatus without continuously reading the storage means using the bus. Is read from the storage means.
[0017]
In this case, among the interrupt factors, the first factor can be requested to the first data processing device, and the second factor can be requested to the second data processing device. The address space may include the address space of the second data processing device, and the input / output means is readable / writable from the first data processing device and the second data processing device. Is provided with a function for adjusting the operation.
[0018]
The emulation processor for evaluating the semiconductor integrated circuit device outputs a signal indicating which data processing device is using the bus on which the first and second data processing devices operate exclusively. , First and second break interrupt input terminals for stopping the first and second data processing devices.
[0019]
Furthermore, an emulator equipped with this processor determines whether the operation information of the first and second data processing devices is stored in the storage means at the same time, or whether the operation information of one data processing device is selectively stored in the storage means. Means for selecting based on designation from system development device, or means for independently setting conditions for requesting break interrupt to first and second data processing devices based on designation from system development device It is what has.
[0020]
[Action]
According to the semiconductor integrated circuit device described above, the data processing device can be read by making it possible to read instructions stored in two independent readable storage means by buses juxtaposed to the two data processing devices, or by expanding the bus width. By making it possible to read more instructions than the number of instructions that can be executed per unit time, or by incorporating a function that supplies instructions that can operate two data processing devices in parallel, a plurality of storage means can be selected simultaneously. By simultaneously writing or simultaneously reading a plurality of storage means, the restriction on the number of channels of data processing due to interrupts can be eliminated, and the data processing contents can be made arbitrary.
[0021]
In addition, since the first and second data processing devices operate simultaneously, the processing speed of the single chip microcomputer or the semiconductor integrated circuit device can be improved.
[0022]
Furthermore, according to the emulation processor and the emulator equipped with the emulation processor, the first data processing device can be stopped by the first break interrupt, and the second data processing device can be stopped by the second break interrupt. Thus, debugging efficiency can be improved by having an interrupt for independently stopping the two data processing devices.
[0023]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0024]
Example 1
FIG. 1 is a block diagram showing a single chip microcomputer according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of an entire address map in the single chip microcomputer of the present embodiment, and FIG. 3 is a bus diagram of the single chip microcomputer. FIG. 4 is a schematic block diagram of the interrupt controller, FIG. 5 is a schematic block diagram of the interrupt request bit and interrupt permission circuit, FIG. 6 is a bus operation timing diagram, and FIG. 7 is a low power consumption state. 8 is a schematic block diagram of the control circuit, FIG. 8 is an explanatory diagram of a register configuration for controlling the input / output port, FIG. 9 is a schematic block diagram of the input / output port, FIG. 10 is an address map of the PROM, and FIG. FIG. 12 is a block diagram of the main part of the test mode, and FIG. 13 is a schematic block of the emulation processor. 14 shows a schematic block diagram of the emulator, FIG. 15 is a block diagram showing a modification of the single-chip microcomputer according to the present embodiment.
[0025]
First, the configuration of the single chip microcomputer of this embodiment will be described with reference to FIG.
[0026]
The single-chip microcomputer of this embodiment includes a central processing unit (CPU1: first data processing device, CPU2: second data processing device), read-only memory (ROM1: first readable storage means, ROM2: Second readable storage means), random access memory (RAM1, RAM2, RAMP), timer, pulse output circuit, serial communication interface (SCI), A / D converter (A / D), input / output port (IOP0) ~ IOP11: data input / output means), interrupt controller (interrupt control means), bus controller (bus control means), and clock oscillator functional block (or module), formed on one semiconductor substrate .
[0027]
These functional blocks are connected to each other by an internal bus. The internal bus includes a read signal and a write signal in addition to an address bus and a data bus, and may further include a bus size signal or a system clock. The internal address bus includes IAB1 (first bus), IAB2 (second bus), and PAB (third bus), and the internal data bus includes IDB1 (first bus) and IDB2 ( A second bus) and a PDB (third bus). The internal data buses IDB1, IDB2, and PDB have a 16-bit configuration. The instructions of CPU1 and CPU2 are in units of 16 bits.
[0028]
CPU1, ROM1, and RAM1 are connected to IAB1 and IDB1, and CPU2, ROM2, and RAM2 are connected to IAB2 and IDB2. RAMP is connected to PAB and PDB. These IAB1, IAB2, and PAB are interfaced by a bus controller, and similarly, IDB1, IDB2, and PDB are interfaced by a bus controller.
[0029]
PAB and PDB are connected to a bus controller, RAMP, timer, pulse output circuit, SCI, A / D converter, interrupt controller, and IOP0 to IOP11. Either one of CPU1 and CPU2 can read / write these using PAB and PDB. The interrupt controller inputs an interrupt signal output from the timer, SCI, and input / output port, and outputs an interrupt request signal and a vector number to the CPU 1 or CPU 2.
[0030]
The input / output port is also used as an external bus signal and an input / output signal of the input / output circuit. IOP0-3 are used as address bus outputs, IOP4, 5 are used as data bus input / output, and IOP6 is also used as bus control signal input / output signal. The external address and the external data are connected to IAB1 and IDB1 via buffer circuits included in these input / output ports, respectively. PAB and PDB are used to read / write the registers of the input / output ports, and are not directly related to the external bus.
[0031]
The bus control signal output includes an address strobe, a high / low data strobe, a read strobe, a write strobe, and a bus acknowledge signal. The bus control input signal includes a wait signal and a bus request signal. These input / output signals are not shown. The expansion of the external bus is selected by an operation mode or the like, and the functions of these input / output ports are also selected.
[0032]
Also, IOP7 is a timer input / output, IOP8 is a pulse output, IOP9 is an SCI input / output, IOP10 is an analog input, and IOP11 is also used as an external interrupt request (IRQ) input. The input / output signals of the timer, SCI, A / D converter and IOP7, IOP9, IOP10 are not shown.
[0033]
In addition, there are input terminals such as power supply terminals Vcc, Vss, analog power supply terminals AVcc, AVss, reset input RES, standby input STBY, interrupt input NMI, clock input EXTAL, XTAL, operation mode inputs MD0, MD1, MD2.
[0034]
The pulse output circuit outputs the content held in a register (NDR) (not shown) from a terminal also serving as IOP8 in accordance with a trigger signal given from the timer.
[0035]
Next, an address map of the single chip microcomputer will be described with reference to FIG.
[0036]
For example, CPU 1 has a 4 Gbyte address space, and CPU 2 has a 64 kbyte address space. ROM1 and RAM1 exist only in the address space of CPU1, and ROM2 and RAM2 exist only in the address space of CPU2. The RAMP indicated by the hatched portion, the address of each functional block of the timer, pulse output circuit, SCI, A / D converter, IOP0 to 11, and interrupt controller, that is, the internal register, for each physical address, Have a unique logical address on the address space of the CPU.
[0037]
These addresses are associated with each other, and specifically, an address obtained by adding H′FFFF above the address of CPU 2 becomes the address of CPU 1. For example, the start address of RAMP is H′FFFFFB80 for CPU1 and H′FB80 for CPU2.
[0038]
That is, the CPU 1 can read / write ROM1, RAM1, RAMP, and internal registers, and the CPU2 can read / write ROM2, RAM2, RAMP, and internal registers.
[0039]
Next, the connection state of the address bus and data bus of this single chip microcomputer will be described with reference to FIG.
[0040]
In FIG. 3, I / O includes the functional blocks of the timer, pulse output circuit, SCI, A / D converter, IOP 0 to 11, and interrupt controller of FIG. Since the clock oscillator is not connected to the bus, it is omitted.
[0041]
As the address bus and data bus, there are CPU1, ROM1, RAM1, IAB1 connecting the outside, IAB2 connecting CPU2, ROM2, RAM2, and PAB connecting RAMP, I / O. Such an address bus and data bus are interfaced by a bus controller (BSC).
[0042]
For example, when the CPU 1 reads a program from the ROM 1 or reads / writes data from / to the RAM 1, the operation is performed using the IAB1 and IDB1. The CPU 1 does not use PAB and PDB.
[0043]
On the other hand, when the CPU 2 reads a program from the ROM 2 or reads / writes data from / to the RAM 2, the operation is performed using the IAB2 and IDB2. The CPU 2 does not use PAB and PDB. At this time, the CPU 1 and the CPU 2 operate using mutually independent buses and can operate in parallel.
[0044]
When either one of the CPU 1 and the CPU 2 reads / writes data to / from the RAMP or the I / O, the bus right arbitration is performed. In this case, the bus right request by the CPU 2 has priority over the bus right request by the CPU 1. This bus arbitration is performed by the bus controller based on the address indicated by IAB1 / IAB2 and the command signal output by the CPU1 / 2. The command signal includes a read request, a write request, a size signal, and the like.
[0045]
If one side reads / writes data to / from RAMP or I / O and the other side attempts to read / write data to / from RAMP or I / O, the latter continues until the former read / write is completed. Is given a standby signal to enter a standby state. For example, the CPU 1 can read / write the ROM 1 and RAM 1 while the CPU 2 is reading / writing data with RAMP or I / O.
[0046]
Furthermore, if CPU 1 and CPU 2 try to read / write data to / from RAMP or I / O at the same time, one CPU will be in a stopped state, but the program will not be placed in RAMP or I / O. As a result, data read / write with RAMP or I / O can be limited to data only, and the frequency can be reduced.
[0047]
In this case, since data read / write is performed based on the read instruction, the ratio of the number of instruction read and data read / write does not become 1/2 or more. Further, since all programs are not configured by data read / write instructions, the ratio can be further reduced. Generally, it is considered to be about 1/4 to 1/5. The same is shown by the program described in this embodiment. Therefore, the parallel operability of CPU1 and CPU2 can be improved.
[0048]
In order to effectively use such parallel operation, the CPU 1 performs overall settings and main program processing using the ROM 1, RAM 1 or an external device, and the CPU 2 performs sequential control of I / O. It is good to do so. In addition, CPU instructions may be arranged in the ROM 1 or the ROM 2 and the work area may be arranged in the RAM 1 or the RAM 2.
[0049]
Next, the interrupt controller will be described in detail with reference to FIG.
[0050]
For example, there are two types of interrupt factors, internal interrupts and external interrupts, each having an interrupt factor flag. This internal interrupt factor flag is set to “1” when the timer, SCI, and A / D converter input / output circuits are in a predetermined state, and the external interrupt factor flag is external interrupt. Set to “1” when the input terminal reaches a predetermined level or when a predetermined signal change occurs. This interrupt factor flag is cleared to “0” by the write operation of the CPU 1/2.
[0051]
The output of each bit of the interrupt factor flag is input to the interrupt permission circuit, and the content of the interrupt permission register, that is, the interrupt permission bit is further input to this interrupt permission circuit. This interrupt permission register is a register that can be read / written by the CPU 1/2, and selects whether to permit or prohibit the corresponding interrupt.
[0052]
For example, if the interrupt factor flag is set to “1” and the interrupt permission bit is set to “1”, an interrupt is requested. That is, the interrupt permission circuit is configured by a logical product circuit having the corresponding interrupt factor flag and the interrupt permission bit as inputs.
[0053]
The output of the interrupt permission circuit is input to the CPU selection circuit, and the contents of the interrupt selection register IRQSEL are further input to this CPU selection circuit. This interrupt selection register selects whether the CPU 1 or the CPU 2 is permitted to interrupt when an interrupt is requested.
[0054]
For example, if the bit of the interrupt selection register is set to “1”, the CPU 2 is requested to interrupt. When the bit of the interrupt selection register is cleared to “0”, the CPU 1 is requested to interrupt. That is, the CPU selection circuit includes a logical product circuit of the corresponding interrupt signal and the interrupt selection bit, and a logical product circuit of the interrupt signal and the inverted signal of the interrupt selection bit. The output of the former AND circuit is a CPU2 interrupt request signal, and the output of the latter AND circuit is a CPU1 interrupt request signal.
[0055]
As for the output of the CPU selection circuit, the CPU1 interrupt request and the CPU2 interrupt request are independently input to the priority determination circuit, and the output of the priority register is further input to this priority determination circuit. This priority register sets, for example, two levels of priority for each group of interrupt factors.
[0056]
In this case, the priority order is determined for each CPU1 / 2 interrupt request. As a result of this determination, the highest priority is selected, a vector number is generated, and each vector number of the CPU1 / 2 interrupt request is output.
[0057]
The CPU1 / 2 interrupt request signal and vector number are input to the mask level determination circuit, and the corresponding CPU1 / 2 interrupt mask bits are input to the mask level determination circuit. Here, if the requested interrupt is below the interrupt mask level of the CPU, it is suspended. Then, an interrupt request signal and a vector number are output to each of CPU 1/2. CPU 1 has 2 mask bits, but CPU 2 has 1 mask bit.
[0058]
Furthermore, when the interrupt request signal for each CPU becomes active, this CPU starts interrupt exception processing at the end of the instruction being executed, extracts the branch destination address from the vector address corresponding to the vector number, and interrupts. Branch to the load processing routine.
[0059]
Since such priority determination and interrupt mask level are known in March 1993, published by Hitachi, Ltd. “H8 / 3003 Hardware Manual” or Japanese Patent Application No. 4-137955, etc. Detailed description is omitted.
[0060]
Further, the vector number is constant regardless of whether the CPU 1 or the CPU 2 is required. However, corresponding to the size of the address space, the vector address is in units of 4 bytes in CPU 1 and in units of 2 bytes in CPU 2.
[0061]
The non-maskable interrupt NMI is input from one terminal NMI, but can request interrupts from two CPUs simultaneously. This does not have a corresponding interrupt enable bit. This NMI interrupt is used to forcibly stop the processing of the CPU when the single-chip microcomputer or the semiconductor integrated circuit is out of control because of its non-maskable characteristics. It is convenient to request NMI interrupts to both CPUs 2. Compared to using at least two terminals, one terminal can be saved and used effectively as an input / output port or the like.
[0062]
The interrupt factor flag has an interrupt request bit that can be written by the CPU 2. When this interrupt permission bit is set to “1”, the CPU 1 can be requested to interrupt. The interrupt request bit can be set to “1” from the CPU 2 and can be cleared to “0” from the CPU 1. When the CPU 1 clears to “0”, it is necessary to read “1” in advance and then write “0”.
[0063]
Next, the interrupt request bit and the interrupt permission circuit in the interrupt controller will be described in detail with reference to FIG.
[0064]
For example, two flip-flops FF1 and FF2 are included. The FF1 constitutes an interrupt request bit, and a reset signal RESET is input as the clear signal CLR. The output of the AND circuit AND1 is input to the set signal S, the output of the AND circuit AND3A is input to the reset signal R, and the output Q is output as an interrupt request via the AND circuit AND4. In addition, it is input to the AND circuit AND2 and the output buffer.
[0065]
The AND circuit AND1 receives the bus right signal of the CPU 2, the register write signal, and predetermined bits of the internal data bus. The register read / register write signal is a signal generated by a logical product of the read signal / write signal and a signal indicating that the register is selected by decoding the address. For example, the register write signal becomes active “1” when CPU 2 or CPU 1 writes to the address of this interrupt request bit.
[0066]
The FF2 controls the interrupt request bit, and the reset signal RESET is input as the clear signal CLR. Further, the output of the AND circuit AND2 is input to the set signal S, the output of the AND circuit AND3A is input to the reset signal R, and the output Q is input to the AND circuit AND3A.
[0067]
The output of FF1, the bus right signal of CPU1, and the register read signal are input to the AND circuit AND2.
[0068]
The AND circuit AND3A receives the output of FF2, the inversion of a predetermined bit of the internal data bus, and the output of AND3B. The bus right signal and register write signal of the CPU 1 are input to the AND 3B.
[0069]
The AND circuit AND4 receives an output of the FF1 and an interrupt permission signal which is an output of a predetermined bit of an interrupt permission register (not shown), and the output is an interrupt request signal. Note that the selection bit is not provided, and it is always necessary to request the CPU 1 for an interrupt.
[0070]
The output buffer inputs the output of FF1 as data, and inputs the register read signal as a clock signal. This output is coupled to a predetermined bit of the internal data bus.
[0071]
Therefore, when the CPU 2 writes “1” to the address of the interrupt request bit, the output of the AND1 becomes “1” and the FF1 is set to “1”. As described above, when the predetermined bit of the interrupt permission register is set to “1”, the CPU 1 is requested to interrupt.
[0072]
Further, when the CPU 1 reads the address of the interrupt request bit in this state, the contents of the interrupt request bit are output to the data bus via the output buffer, and the output of the AND2 becomes “1”, so that the FF2 becomes “ Set to 1 ″.
[0073]
Subsequently, when the CPU 1 writes “0” to the interrupt request bit, the output of the AND3A becomes “1”, and FF1 and FF2 are cleared to “0”. Similarly, the CPU 1 has an interrupt request bit that can be written, and this interrupt permission bit can be written only from the CPU 2 and can request the CPU 2 to interrupt.
[0074]
In the so-called read modify write instruction, it is preferable not to release the bus between read and write. For example, the bit set instruction fetches data at a specified address into the CPU in byte size, sets 1 bit specified in the CPU to “1”, and writes the data in byte size.
[0075]
The PAB and PDB are not released to the other CPU between this read and write. The signal prohibiting the release of the bus can be included in the command signal output from the CPU 1/2 to the bus controller.
[0076]
Next, an example of the operation timing of the internal bus will be described with reference to FIG.
[0077]
The single-chip microcomputer of this embodiment operates in synchronization with, for example, the system clock φ, IAB1 / 2 is output in synchronization with φ # which is an inverted signal of φ, and ROM1 / 2 and RAM1 of CPU1 / 2. Reading for / 2 is performed in one state.
[0078]
First, IAB1 / 2 is output in one state in synchronization with φ #, and is not particularly limited, but is latched in ROM1 / 2 and RAM1 / 2 in synchronization with φ. Read data corresponding to this is output in synchronization with φ #, and φ # is taken into the CPU during the active period. For example, the data corresponding to the address output to IAB1 / 2 in synchronization with φ # of T1 is taken into CPU 1/2 during the period in which φ # of T2 is active.
[0079]
On the other hand, read / write with respect to RAMP is performed in two states, and read / write with respect to I / O is performed in three states. The IAB1 / 2 synchronized with φ # is synchronized with φ by the bus controller.
[0080]
In this case, the program of the CPU 1 is as follows. The instruction notation is the same as that of the CPU described in “H8 / 300 Series Programming Manual” issued by Hitachi, Ltd. in July 1989.
[0081]
CMP. B #CODE, R0L
BEQ N1
BTST # 0, @PORT
BNE N2
For example, the CMP, BEQ, and BNE instructions are 2 bytes long, and the TST instruction is 4 bytes long.
[0082]
First, a CMP instruction is read from address n. When the execution of the CMP instruction is started, the BEQ instruction is first read from the address n + 2, and the immediate data CODE and the contents of the general-purpose register R0L are internally compared and reflected in the condition code.
[0083]
Further, when the execution of the BEQ instruction is started, first, the BTST instruction is read from the address n + 4. Next, an instruction is read from the branch destination address N1, and it is determined whether the comparison results match. If they do not match, the instruction at address N1 is ignored and the already read BTST instruction is executed.
[0084]
Subsequently, the second word of the BTST instruction is read. When this BTST instruction is executed, data is read in byte size from the I / O specified by the absolute address PORT using PAB / PDB. Next, a BNE instruction is prefetched from address n + 6.
[0085]
The program of the CPU 2 is as follows.
[0086]
BCLR #RDRF, @SSR
For example, the BCLR instruction is 4 bytes long.
[0087]
First, a BCLR instruction is read from address m and address m + 2. When the execution of the BCLR instruction is started, data is first read in byte size using PAB / PDB from the I / O specified by the absolute address SSR.
[0088]
Subsequently, the next instruction is prefetched from the address m + 4, and the bit designated by the immediate data RDRF of the read data is cleared to “0”. This data is written to the I / O specified by the absolute address SSR using PAB / PDB. The execution of the next instruction is started, and the next instruction is prefetched from the address m + 6.
[0089]
At T1, instruction fetch from ROM1 / 2 of CPU1 / 2 is performed, and an address is output to IAB1 / 2.
[0090]
At T2, the instruction codes (CMP instruction, first word of the BCLR instruction) read from ROM 1/2 to IDB 1/2 are fetched by CPU 1/2, and the next instruction fetch address is output to IAB 1/2. The
[0091]
At T3, the CPU 1/2 fetches the instruction code (the BEQ instruction and the second word of the BCLR instruction) read from the ROM 1/2 to the IDB 1/2, the CPU 1 receives the next instruction fetch address, and the CPU 2 addresses Each SSR is output to IAB1 / 2.
[0092]
In this case, since only the CPU 2 uses the PAB / PDB, the use of the PAB / PDB of the CPU 2 is permitted. Here, since the SCI read requires three states, the CPU2 standby signal becomes high level.
[0093]
At T4, the bus right signal goes low, indicating the use of PAB / PDB of CPU2. The contents of IAB2 are output to PAB, and the contents of SCI register SSR are read. This read data is obtained at T6.
[0094]
In this case, the CPU 1 fetches the instruction code read from the ROM 1 to the IDB 1 (first word of the BTST instruction), and the CPU 1 outputs the branch destination address N1 to the IAB 1 (second word of the BTST instruction).
[0095]
At T5, the CPU 1 fetches the instruction code read from the ROM 1 to the IDB 1, but this is not executed because the branch condition is not satisfied. The first word of the previously fetched BTST instruction becomes valid. In this case, the CPU 1 outputs the next instruction fetch address to the IAB 1.
[0096]
At T6, the CPU 2 fetches the data read from the SCI register SSR via the PDB and IDB2. Further, the CPU2 standby signal becomes low level, and the next instruction fetch address is output to IAB2.
[0097]
In this case, the CPU 1 outputs the address PORT to the IAB 1, and since the use of the PAB / PDB of the CPU 2 is finished, the use of the PAB / PDB of the CPU 1 is permitted. Here, since the PORT read requires three states, the CPU1 standby signal becomes high level.
[0098]
At T7, the bus right signal goes high, indicating the use of PAB / PDB of CPU1. The contents of IAB1 are output to PAB, and the contents of register PORT of the input / output port are read. This read data is obtained at T9.
[0099]
In this case, the CPU1 standby signal becomes low level, the next instruction fetch address is output to IAB1, and CPU2 outputs the address SSR to IAB2. Here, since the CPU 1 is using PAB / PDB, the operation of the CPU 2 is suspended, and the CPU 2 standby signal becomes high level.
[0100]
At T8, the CPU 2 outputs data to be written to the address SSR to the IDB2.
[0101]
At T9, the CPU 1 takes in data read from the register PORT of the input / output port via the PDB and IDB2. The CPU 1 outputs the next instruction fetch address to the IAB 1. In this case, the CPU1 standby signal goes low, and the next instruction fetch address is output to IAB1.
[0102]
At T10, the CPU 1 captures the instruction code (BNE instruction) read from the ROM 1 to the IDB 1. The address of the next instruction fetch is output to IAB1. In this case, the bus right signal becomes low level, and the use of the PAB / PDB of the CPU 2 is displayed. The contents of IAB2 are output to PAB, and the contents of IDB2 are written to SCI register SSR.
[0103]
A write operation is performed at T11 and T12. In this case, the CPU2 standby signal becomes low level at T12, and the address of the next instruction fetch is output to IAB2. The CPU 1 repeats the same operation as described above.
[0104]
Note that the CPU 1 can be an external CPU, and an external CPU can read / write the common part as a peripheral function. Further, when the CPU 2 reads / writes the common part, the wait signal is activated in the external CPU and waits. At this time, the single chip microcomputer outputs an interrupt signal to the external CPU.
[0105]
Next, a data transfer program example is shown below. Here, the checksum of the SCI received data is performed, and the result is stored in the work address SUM arranged on the built-in RAM 2. Further, it is assumed that the number of received data is stored in the work address SUM arranged on the built-in RAM 2.
[0106]
In addition, the work address CNT for storing the number of transfers, the SCI reception data register RDR, the status register SSR, and the interrupt controller's interrupt selection register IRQSEL are used.
[0107]

First, the CPU 2 requests the reception completion interrupt RXI, and branches to an interrupt routine. First, the general-purpose register R0 is saved on the stack (1). Then, the contents of the SCI reception data register RDR are read into the lower 8 bits R0L of the general-purpose register R0 (2).
[0108]
Further, the contents of the work address SUM arranged on the built-in RAM 2 are read into the upper 8 bits R0H of the general-purpose register R0 (3). Then, the contents of R0H and R0L are added (4). The addition result is written to the address SUM (5).
[0109]
Further, the contents of the work address CNT arranged on the built-in RAM 2 are read into the general-purpose register R0H (6). Then, the contents of R0H are decremented (-1) (7). The decrement result is written to the address CNT (8).
[0110]
If this content is "0", the process branches to L1 (9), and the bit corresponding to the reception completion interrupt RXI of the interrupt selection register IRQSEL is inverted (12). At this time, since the interrupt request flag RDRF remains set to “1”, the reception completion interrupt RXI is requested to the CPU 1. Then, the process returns from the interrupt routine (13).
[0111]
If the content written in the address CNT is not “0” (9), the interrupt request flag RDRF is cleared to “0” (10). Then, after executing the branch instruction (11), the process returns from the interrupt routine (13).
[0112]
Also, the address determination for multiprocessor reception can be performed by the following program example. In this case, if the received address matches its own address as a result of the address determination, the request destination of the reception completion interrupt is changed to the CPU 1.
[0113]

First, the CPU 2 requests the reception completion interrupt RXI, and branches to an interrupt routine. First, the general-purpose register R0 is saved on the stack (1). Then, the contents of the SCI reception data register RDR are read into the lower 8 bits R0L of the general-purpose register R0 (2).
[0114]
This content is compared with the ID of the multiprocessor reception (3). As a result, if they match, the process branches to L1 (4), and the bit corresponding to the reception completion interrupt RXI of the interrupt selection register IRQSEL is inverted (7). At this time, since the interrupt request flag RDRF remains set to “1”, the reception completion interrupt RXI is requested to the CPU 1. Then, the process returns from the interrupt routine (8).
[0115]
If the result of comparison with its own ID does not match (4), the interrupt request flag is cleared to “0” (5). Then, after executing the branch instruction (6), the process returns from the interrupt routine (8).
[0116]
In this case, a plurality of transfers can be performed with one interrupt. For example, a stepping motor can be driven and this acceleration / deceleration can be performed. In addition, for each compare match interrupt OCMI of the timer, the data output from the port is updated to drive the motor. Further, the contents of the compare register can be updated to change the data output cycle to perform acceleration / deceleration.
[0117]
For the display of this state, the contents of the work address UPDW arranged on the built-in RAM 2 are used. When this bit 6 is cleared to “0”, the operation is constant speed. When it is set to “1”, acceleration or deceleration is performed. That is, when bit 7 is cleared to “0”, deceleration is performed. When it is set to “1”, the acceleration operation is performed. The initial value is set to “1” for both bits 6 and 7.
[0118]
The next output pulse is stored in the next data register NDR of the pulse output circuit, and the pulse output cycle is set in the constant register OCR of the timer. When the timer counter matches the value of the constant register, a compare match signal (not shown) is generated, and the contents of NDR are output from a terminal shared with IOP8. At the same time, the value of the timer counter is cleared to zero. This NDR is 4 bits.
[0119]
Such pulse output is the same as that of Japanese Patent Application No. 4-117969.
[0120]
PUSH R0 (1)
MOV. B @NDR, R0L (2)
ROTL. B R0L (3)
BLD # 4, R0L (4)
BST # 0, R0L (5)
MOV. BR0L, @NDR (6)
First, the CPU 2 requests the compare match interrupt OCMI, and branches to an interrupt routine. First, the general-purpose register R0 is saved on the stack (1). Then, the contents of the next data register NDR are read into the lower 8 bits R0L of the general register R0 (2).
[0121]
This content is rotated (3). Here, in order to perform rotation in units of 4 bits, the rotated bit 4 is stored in the carry flag (4), and this carry flag is stored in bit 0 (5). The result of completion of this 4-bit unit rotation is written to the NDR (6). This content is output from the terminal at the next compare match.
[0122]

Subsequently, the content of bit 6 of the address UPDW is inspected (7). If this content is "0" (constant speed operation), the process branches to L3 (8), and the content of the constant register OCR is held. If not "0", the contents of the constant data register OCR are read into the general-purpose register R0 (9).
[0123]
Further, the content of bit 7 of the address UPDW is inspected (10). If this content is “0” (deceleration operation), the process branches to L1 (11), and if not “0” (acceleration operation), The numerical value CNST is subtracted from the general-purpose register R0 (12) and branched to L2 (13). In L1, the constant value CNST is added to the general register R0 (14), and in L3, the contents of the general register R0 are written to the constant register OCR (15).
[0124]

Subsequently, the contents of the address CNT are read into the general-purpose register R0H (16). The content R0H is decremented (-1) (17). If this content is not "0", the process branches to L5 (18), and if "0", the content of bit 6 of the address UPDW is inspected (19).
[0125]
Further, if this content is “0” (constant speed operation), the process branches to L6 (20). If not “0”, the content of bit 7 is inspected (21), and further this content is “0”. If (deceleration operation), branch to L6 (22), if not "0" (acceleration operation), clear bit 6 of address UPDW to "0" and transition to constant speed operation (23) Then, the rotational speed CNT1 of the low speed operation is set to R0H (24). And it branches to L5 (25).
[0126]
In L4, in order to shift to a deceleration operation, bit 6 of address UPDW is set to “1” (26), and bit 7 is cleared to “0” (27). Further, the rotational speed CNT2 of the deceleration operation is set to R0H (28).
[0127]
Further, in L5, the contents of the general-purpose register R0H are written to the address CNT (29). Then, after executing the branch instruction (30), the process returns from the interrupt routine (32).
[0128]
After the deceleration operation is completed, the bit corresponding to the compare match interrupt OCMI is inverted in the interrupt selection register IRQSEL at L6 (31). At this time, since the interrupt request flag OCMF remains set to “1”, the reception completion interrupt RXI is requested to the CPU 1. Then, the process returns from the interrupt routine (32).
[0129]
The activation may be instructed by requesting an interrupt from the CPU 1 to the CPU 2 using the interrupt request register and arranging a command at a predetermined address on the RAMP, for example.
[0130]
As described above, for example, compared with the method described in Japanese Patent Application No. 4-137854 or Japanese Patent Application No. 4-117969, it is not necessary to develop data in the RAM, and the amount of RAM used can be saved.
[0131]
Further, if the CPU 2 is mainly used for data processing corresponding to an interrupt, the CPU 2 does not always have a program to be processed. Therefore, when there is no program to be processed when data processing by one interrupt is completed, the CPU 2 should be in a low power consumption state, so-called sleep state.
[0132]
In this sleep state, a transition is made by executing a dedicated SLEEP instruction. Then, the clock supplied to the CPU 2 is stopped. When an interrupt is requested, the sleep state is canceled.
[0133]
Next, the low power consumption state control circuit will be described in detail with reference to FIG.
[0134]
The low power consumption state control circuit is configured in, for example, a clock oscillator, and the low power consumption state is controlled by three flip-flops SLPF1, SLPF2, and SSBYF.
[0135]
The flip-flop SLPF1 is set when the CPU1 executes the SLEEP instruction. At this time, the CPU 1 enters a sleep state. Further, when an interrupt request to the CPU 1 is generated, a clear state is entered.
[0136]
The flip-flop SLPF2 is set when the CPU2 executes the SLEEP instruction. At this time, the CPU 2 enters a sleep state. When an interrupt request for the CPU 2 is generated, the CPU 2 is cleared.
[0137]
The flip-flop SSBYF enters a set state when one CPU is in a sleep state and the other CPU executes a SLEEP instruction with a control bit SSBY (not shown) set to “1”. In this software standby state, the operation of all functions including the clock oscillator is stopped. The inside is reset.
[0138]
However, as long as a prescribed voltage is applied, the contents of RAM1, RAM2, and RAMP are retained. In addition, the state of the input / output port is also maintained. When an NMI interrupt request is generated, a clear state is entered. Since the inside is in a reset state, no interrupt request other than NMI is generated.
[0139]
In order to transition to this software standby state, one CPU may set the SSBY bit to “1” and execute the SLEEP instruction. Depending on the state of the other CPU, whether to immediately transition to the software standby state or to transition to the software standby state after the other CPU executes the SLEEP instruction after the transition to the sleep state is automatically selected. . For this reason, when creating a program, it is not necessary to confirm the mutual operation state, and the efficiency of program creation can be improved.
[0140]
Also, when the interrupt process is started, it is preferable to provide a bit indicating whether the previous operation was in operation or the sleep state. If an interrupt is accepted during this operation, the contents of the CPU's internal registers must be saved, but if an interrupt is accepted during sleep, the CPU's internal registers will not have the data being worked on. There is no need to evacuate. If the save operation and the return operation at the end of the process are not performed, the speed can be increased.
[0141]
Further, the input / output port allows selection from which CPU writing is possible.
[0142]
Next, the register of the input / output port will be described in detail with reference to FIG.
[0143]
The register of the input / output port includes a data direction register (DDR), a data register (DR), and a port control register (PSEL).
[0144]
DDR is a write-only register, and is input when it is cleared to “0” and output when it is set to “1”.
[0145]
The DR stores output data. When this DDR is set to “1”, the contents of DR are output. At the time of reading, the contents of DR or the state of terminals are read out. That is, when the DDR is cleared to “0”, the terminal state is read. When the DDR is set to “1”, the contents of the DR are read.
[0146]
The PSEL selects which CPU controls each input / output terminal. The control bit of the port control register (PSEL) controls the bits of the data register (DR) and the data direction register (DDR) in common. When PSEL is cleared to “0”, writing is performed by CPU 1, and when it is set to “1”, writing is performed by CPU 2.
[0147]
When a pull-up MOS is incorporated in the port or a double output buffer is used, the registers for performing these controls may be controlled in common by PSEL. Examples of such registers are described in “H8 / 3003 Hardware Manual” P263 to P306, P419 to P445 issued by Hitachi, Ltd. in March 1993.
[0148]
Next, the input / output ports will be described in detail with reference to FIG.
[0149]
In the input / output port of this embodiment, the data direction register (DDR), the data register (DR), and the port control register (PSEL) are configured by flip-flops. In either case, a predetermined bit of the internal data bus is used as a data input (D), and a reset signal (RESET) is used as a clear input (CLR).
[0150]
The DDR input clock (C) is the output of the AND circuit AND1. This output (Q) is used as a control signal for the output buffer OBUF and a selection signal for the selector SEL1.
[0151]
The DR input clock (C) is the output of the AND circuit AND2. This output (Q) is used as the data input of the output buffer OBUF and the data input of the selector 1.
[0152]
The PSEL input clock (C) is a PSEL read signal WRPSEL. This output (Q) is used as a selection signal for the selector SEL2.
[0153]
The output buffer OBUF is a DDR output as a control signal, a data input is a DR output, and an output signal is connected to a terminal P.
[0154]
The input buffer IBUF has an input signal connected to the terminal P and an output signal as a data input of the selector SEL1.
[0155]
The selector SEL1 uses the DDR output as a selection signal and the DR output and the input buffer IBUF output as data inputs. When the DDR output is “0”, the input buffer IBUF output is selected, and when the DDR output is “1”, the DR output is selected. The output of the selector SEL1 is input to the DR read buffer.
[0156]
The selector SEL2 uses the PSEL output as a selection signal and the CPU1 / 2 bus right signal as a data input. This output is a write permission signal. When PSEL is “0”, the CPU1 is in a write-permitted state with the CPU1 bus right. When PSEL is “1”, the CPU 2 is in a write-permitted state with the CPU 2 bus right.
[0157]
The DR read buffer DRBUF receives the output of the selector SEL1, uses the DR read signal RDDR as a clock, and the output signal is connected to a predetermined bit of the internal data bus. When this RDDR is active, the output of the selector SEL1 is output to the internal data bus.
[0158]
The PSEL read buffer PSBUF receives the output of the PSEL flip-flop, uses the PSEL read signal RDPSEL as a clock, and the output signal is connected to a predetermined bit of the internal data bus. When this RDPSEL is active, the output of the PSEL flip-flop is output to the internal data bus.
[0159]
The AND circuit AND1 receives the write permission signal and the DDR write signal WRDDR, and the output signal is the DDR input clock.
[0160]
The AND circuit AND2 receives the write permission signal and the DR write signal WRDR, and the output signal is the DR input clock.
[0161]
ROM1 and ROM2 can be PROMs, and when this PROM is programmed from the outside, it is preferable that the two ROMs have consecutive addresses from the outside.
[0162]
Next, the address map of the PROM will be described with reference to FIG.
[0163]
For example, PROM1 is 64 kbytes and PROM2 is 32 kbytes. In the MCU mode, PROM1 is arranged in H'00000000 to H'0000FFFF, and PROM2 is arranged in H'0000 to H'7FFF.
[0164]
In the PROM mode, PROM1 is arranged at H'0000-H'0FFFF, and PROM2 is arranged at H'10000-H'17FFF.
[0165]
Next, the PROM mode will be described in detail with reference to FIG.
[0166]
This PROM mode is set by setting mode terminals MD1, MD0, and STBY terminals to a low level. At this time, the internal signal EPM is activated (high level) by a mode setting circuit (not shown). In the PROM mode, the CPU 1/2 is disconnected from the address bus and data bus by BUFC 1/2.
[0167]
In FIG. 11, the CS control circuit, the buffer BUFC1 / 2, etc. are included in the bus controller.
[0168]
The PROM is the ROM 1 and the ROM 2 in FIG. 1, and includes a memory array, an address decoder, an input / output circuit, and a control circuit. An address is input to the address decoder, the input / output circuit inputs / outputs data, and the control circuit inputs a control signal, and controls the input / output circuit to write / read data. In addition, the memory array is arranged with non-volatile storage elements.
[0169]
An EPM, CS-1 / 2 #, OE #, PGM #, MS-1 / 2 #, and read signal are input to the control circuit. When this EPM is in an active state, a write / read operation as a PROM is performed based on CS-1 / 2 #, OE #, and PGM #. When the EPM is inactive, a read operation as a ROM in the CPU address space is performed based on the MS-1 / 2 #, read signal.
[0170]
In the PROM mode, it is controlled by VPP, CS #, OE #, and PGM #. Such control is performed by, for example, “HITACHI IC Memory Data Book No.” issued by Hitachi, Ltd. in March 1993. 2 (10th Edition) "PROM described in P510 to P524.
[0171]
The VPP terminal is the RES terminal, the CS #, OE #, and PGM # are the P61, P62, and P63 terminals, the address A0-15 is the P00-07, the P10-17 terminal, the A16 is the P60 terminal, and the data D7-0 is Also used as P40-P47 terminals. Although VPP is not shown, it is given to PROM1 / 2.
[0172]
As internal signals, OE # and PGM # are input via a buffer circuit and supplied to PROM1 and PROM2. CS-1 # is generated by a logical product signal with an inverted signal of the address upper signal A16, and CS-2 # is generated by an inverted signal of the address upper signal A15 and a logical product signal with A16. These CS-1 # and CS-2 # are given to PROM1 and PROM2, respectively.
[0173]
In the PROM mode, IDB1 and IDB2 are connected via a buffer. The data in PROM2 is input / output via IDB2, IDB1 and IOP3. That is, when the read operation is performed when CS-2 # is in the active state, the contents of IDB2 read from PROM2 are output to IDB1. Furthermore, during the read operation, the contents of IDB1 are output to the outside via IOP3.
[0174]
Also, during the write operation, external contents are input to IDB1 via IOP3. When CS-2 # is in the active state and the write operation is performed, the contents of IDB1 are output to IDB2 and given to PROM2. Further, the contents of IDB1 are output to the outside via IOP3.
[0175]
In the PROM mode, IAB1 and IAB2 are connected via a buffer. That is, the address of IAB1 input via IOP1 and 2 is input to IAB2 and given to PROM2. Since the maximum capacity of PROM1 / 2 is 64 kbytes, the address given to each PROM is 16 bits.
[0176]
For example, a read operation is performed when CS-1 / 2 #, OE # is active, and PGM # is inactive, and a write operation is CS-1 / 2 #, PGM # is active, and OE # is non-active. Performed when active.
[0177]
In addition, verification, page writing, and the like are possible. However, since there is no direct relationship with the present invention, detailed description is omitted.
[0178]
In one PROM mode, PROM1 and PROM2 can be collectively written as one PROM externally. Thereby, writing can be performed efficiently.
[0179]
Next, the test mode will be described in detail with reference to FIG.
[0180]
This test mode is set by setting the mode terminals MD1 and MD0 to low level and the STBY terminal to high level. At this time, the internal signal TM is activated (high level) by a mode setting circuit (not shown).
[0181]
In FIG. 12, a control circuit 1/2, a bus arbitration circuit, a selection circuit, a buffer BSBUF, and a buffer BUFC1 / 2 are included in the bus controller.
[0182]
The bus arbitration circuit selects which of the CPUs 1/2 uses PAB / PDB and outputs a control signal PAK. When the PAK is high, the CPU 1 uses the PAB / PDB. When the PAK is low, the CPU 2 uses the PAB / PDB. In the test mode, the PAK signal is controlled by the selection signal supplied from the P62 terminal.
[0183]
In the test mode, CPU 1/2 is disconnected from the address bus, data bus, and read / write signal by BUFC 1/2.
[0184]
Addresses are input from IOP3 to IOP0 to IAB1 via buffer BUFP, and further input to IAB2 and PAB via BSBUF. IAB1 has 32 addresses corresponding to the 4 Gbyte address space, IAB2 has 16 addresses corresponding to the 64 kbyte address space, and PAB has 10 addresses corresponding to the RAMP and I / O addresses. Address. Therefore, IAB1 is preferably used to give an address from the outside.
[0185]
The data bus is input / output from / to IDB1 by the IOP4 via the buffer BUFP. Corresponding to the read / write operation and the address, the contents of IDB2 or PDB are input / output from / to IDB1 via BSBUF.
[0186]
The read signal and the write signal are input from the P60 terminal and the P61 terminal via BUFP. RD1 / 2 and WR1 / 2 are supplied to ROM1, RAM1 / ROM2, and RAM2. Further, it is selected by the bus right signal PAK, becomes RDP, WRP, and is supplied to the RAMP, I / O. In the test mode, regardless of the PAK signal, RD1 / 2 / P always operates in the same manner, and WR1 / 2 / P always operates in the same manner.
[0187]
The control circuit 1/2 outputs selection signals MSROM1 / 2, MSRAM1 / 2, MSRAMP, and MSIO based on the address of IAB1 / 2. Since MSRAMP and MSIO are common signals, one is output and the other is high impedance based on the PAK signal. For example, when the PAK signal is at a high level, the control circuit 1 outputs and the control circuit 2 becomes high impedance.
[0188]
In the test mode, one of MSROM1 / 2 and MSRAM1 / 2 is prohibited based on the PAK signal. This is because one functional block is selected based on an address given from the outside. For example, when the PAK signal is at high level, MSROM1 and MSRAM1 are output based on IAB1, and MSROM2 and MSRAM2 are inactivated.
[0189]
When testing the ROM1 / RAM1, read / write can be performed by giving an address and a read / write signal with the P62 terminal at a high level and the PAK signal at a high level.
[0190]
When testing ROM2 / RAM2, read / write can be performed by giving an address and a read / write signal with the P62 terminal set to low level and the PAK signal set to low level. Only the lower 16 bits of this address are valid.
[0191]
Further, when testing RAMP / I / O, read / write can be performed by giving an address and a read signal / write signal with the P62 terminal at a high level and the PAK signal at a high level. it can.
[0192]
As described above, address data for externally reading / writing internal function blocks can be supplied from the outside to the internal bus to which data is input / output by the CPU, and this function block. It is possible to directly read / write data necessary for the operation from the outside, facilitating the test of the functional blocks built in the single-chip microcomputer and improving the testing efficiency.
[0193]
When testing the built-in RAM, the data test is preferably performed independently, and the address decoder test is preferably performed in parallel. In order to test the address decoder, the RAM 1/2 / P can be selected at the same time so that the test can be performed simultaneously.
[0194]
In this case, a RAM test mode may be provided for FIG. In the test mode, when the P63 terminal is set to the low level, the test mode is the same as described above, and when the P63 terminal is set to the high level, the RAM test mode is set.
[0195]
In the RAM test mode, the RAM1 / 2 / P selection signals MSRAM1, MSRAM2, and MSRAMP can be simultaneously activated. However, the data to be read is bit 0 to 1, bit 2 to 3, and bit 4 to 7, respectively.
[0196]
The CPU 1 and the CPU 2 may be substantially the same CPU, or the CPU 1 may include the CPU 2 so that the software development environment can be shared. An example of such a CPU is Japanese Patent Application No. 4-226447.
[0197]
The emulator that evaluates the single-chip microcomputer as described above is preferably configured so that when the user sets a break condition from the outside, it can be specified which CPU the break is set to. In addition, it is preferable that it is possible to designate a break when both of the two CPU conditions are satisfied.
[0198]
Next, the configuration of the emulation processor will be described with reference to FIG.
[0199]
The emulation processor includes a microcomputer portion including CPU1 and CPU2, and a block dedicated to the emulation processor including a buffer circuit (not shown) and the like, and is formed on one semiconductor substrate by a known semiconductor manufacturing technique.
[0200]
This emulation processor has a user interface for transmitting and receiving signals to and from the application system, and an emulation interface for transmitting and receiving signals to and from the microcomputer development apparatus.
[0201]
As the emulation bus, IAB1 and IDB1, IAB2 and IDB2 are input / output via the emulation interface. In addition, a bus right display signal indicating which CPU of PAB or PDB is using is output. This corresponds to the PAK signal in FIG. In addition, a signal indicating that the CPU is in a standby state is output by bus right arbitration.
[0202]
The access status of PAB and PDB is not explicitly displayed, but can be determined by the bus right display signal and the contents of the emulation bus by IAB1, IDB1, IAB2, and IDB2. By not outputting the PAB and PDB emulation buses, the number of terminals of the emulation processor can be reduced, thereby reducing the package size and thus the emulator size.
[0203]
Two break request terminals, BRK1 # and BRK2 #, are included in the emulation interface. Based on this, a break interrupt is requested to CPU1 and CPU2 by BRK1 and BRK2 signals, respectively. These do not have a corresponding CPU selection bit, and activate the break request signal to the CPU in parallel with the interrupt request signal via the priority determination circuit. The vector number signal is also used as a general interrupt request.
[0204]
When CPU1 and CPU2 accept a break interrupt, break acknowledge signals BRKAK1 and BRKAK2 are activated. For example, when the CPU 2 performs the SCI reception processing and pulse output processing as described above, even if the CPU 1 is stopped by a break interrupt, the CPU 2 interrupts the SCI reception to execute the user processing. Thus, it is possible to avoid the occurrence of a so-called overrun error or interruption of the pulse output, for example, the motor drive of the user system cannot be performed.
[0205]
Next, the configuration of an emulator equipped with an emulation processor will be described with reference to FIG.
[0206]
The connector portion is attached to the application system (user system) instead of the single chip microcomputer. The emulation processor performs input / output of signals to / from the application system using the target system interface via the connector portion and the interface cable.
[0207]
The emulation processor is connected to the emulation bus 1/2 using an emulation interface. The emulation bus 1 corresponds to IAB1 / IDB1, and the emulation bus 2 corresponds to IAB2 / IDB2. These emulation buses include state signals, control signals, and the like not shown.
[0208]
Using this emulation bus, information corresponding to the internal state of the application system and the emulation processor is output from the emulation processor, and various control signals for emulation are input to the emulation processor. An emulation mode terminal (not shown) of the emulation processor is fixed to the power supply level, and the emulation mode is set inside the emulation processor.
[0209]
Although the emulation bus is not particularly limited, it monitors the control status of the emulation processor, the emulation processor, and the status of the emulation bus. When the state reaches a preset state, a break control circuit for inputting an emulator-dedicated interrupt, stopping execution of the user program by the CPU, and transitioning to the emulation program execution state (break) Is connected.
[0210]
In addition, the emulation bus is connected to a real-time trace circuit that sequentially stores addresses, data, and control information given to the emulation bus based on signals indicating CPU read or write operations and signals indicating instruction read operations. Is done. In this embodiment, the emulation buses 1/2 are connected to an emulation memory, a break control circuit, a real-time trace circuit, and the like.
[0211]
Therefore, the emulation memory inputs / outputs IAB1 / IDB1 and IAB2 / IDB2 data independently and in parallel. The break control circuit independently determines the address / data of IAB1 / IDB1 and IAB2 / IDB2, and other information. After the condition on the IAB1 / IDB1 side is established, a break can be requested when the condition on the IAB2 / IDB2 side is established. As described above, the break interrupt can be requested to both the CPU 1 and the CPU 2 simultaneously, or can be requested to only one CPU.
[0212]
The real-time trace circuit stores IAB1 / IDB1 and IAB2 / IDB2 addresses / data and other information independently. When one CPU breaks, only the other CPU's address / data and other information are stored. To do. It is also possible to selectively store the address / data of only one CPU and other information.
[0213]
The emulation memory, break control circuit, and real-time trace circuit are connected to the control bus and are controlled by the control processor via the control bus. The control bus is connected to an emulation processor control circuit and is connected to a system development device such as a personal computer through an interface circuit, although not particularly limited.
[0214]
For example, when the program input from the system development apparatus is transferred to the emulation memory and the CPU reads this program to be placed on the built-in ROM, the program on the emulation memory is read. In addition, break conditions and real-time trace conditions can be given from the system development device.
[0215]
As this break condition, at least the conditions of CPU1 and CPU2 can be set independently. As the real-time trace condition, at least the address / data of CPU 1 and CPU 2 and other information can be stored at the same time, or the address / data and other information of only one CPU can be selectively stored. To.
[0216]
Therefore, according to the single chip microcomputer of this embodiment, the CPU 1 and CPU 2 as data processing devices, the bus controller as bus control means, the ROM 1 and ROM 2 as readable storage means, and the IOP 0 as data input / output means. By using the IOP 11 as a main configuration, the following operational effects can be obtained.
[0217]
(1) IAB1 and IDB1 that connect CPU1 and ROM1 and IAB2 and IDB2 that connect CPU2 and ROM2 are provided independently. By storing the program of CPU1 in ROM1 and the program of CPU2 in ROM2, Data that should be controlled by CPU1 and CPU2 is made possible by allowing CPU2 to operate in parallel and connecting input / output circuits such as RAMP and IOP0 to IOP11 to a common PAB and PDB so that CPU1 and CPU2 can use them. Can be allocated and used arbitrarily. As a result, the processing speed of the single chip microcomputer can be improved and the resource utilization efficiency can be improved.
[0218]
(2) By performing two processes simultaneously with one single-chip microcomputer, it is possible to replace the system that used a plurality of conventional semiconductor integrated circuit devices and to achieve miniaturization.
[0219]
(3) By allowing the CPU 1 and the CPU 2 to request mutual interrupts, the CPUs 1 and 2 can be easily synchronized with each other.
[0220]
(4) When the entire single-chip microcomputer such as software standby is stopped by the operation of CPU 1 and CPU 2, one CPU executes the SLEEP instruction with the SSBY bit set to “1”. Sometimes, depending on the state of the other CPU, whether it immediately transitions to the software standby state or temporarily transitions to the sleep state and then transitions to the software standby state after the other CPU executes the SLEEP instruction. By selecting, when creating a program, it is not necessary to confirm the mutual operation state, and the creation efficiency of the program can be improved.
[0221]
(5) By providing a register DR that designates which CPUs 1 and 2 use IOP0 to IOP11 in bit units, one input / output port can be used by two CPUs 1 and 2, Resource utilization efficiency can be further improved.
[0222]
(6) By providing a register for designating which CPU 1 or 2 the interrupt is requested to the interrupt permission circuit, the two CPUs 1 and 2 can arbitrarily allocate and use the input / output circuit. It is possible to improve the resource utilization efficiency.
[0223]
(7) By using one of the CPUs mainly for data transfer by interruption, various processes at the time of interruption can be easily performed.
[0224]
(8) When ROM1 and ROM2 are composed of PROM, ROM1 and ROM2 are arranged at consecutive addresses in the PROM mode, so that ROM1 and ROM2 are compatible with one PROM, and PROM writing is made efficient. be able to.
[0225]
(9) When the CPUs 1 and 2 have different logical addresses corresponding to one physical address, or when the CPUs 1 and 2 have different physical addresses corresponding to one logical address By providing a control signal for selecting which logical address to be used, an internal function block is externally provided to a plurality of internal buses to which addresses are given by the CPUs 1 and 2 and data is to be input / output Address data for reading / writing data can be supplied via a buffer circuit smaller than the internal bus so that data necessary for this functional block can be directly read / written from the outside. Easier testing of functional blocks built in chip microcomputers and improved testing efficiency Can be realized.
[0226]
(10). By making the CPU 1 and the CPU 2 compatible, the development efficiency can be improved, the support tool can be shared, and the development efficiency of the development apparatus can be improved. As a result, the number of development devices required by the user can be reduced, and the cost required for the development devices can be reduced.
[0227]
(11). In this single-chip microcomputer emulator, the debugging efficiency can be improved by having an interrupt that stops the two CPUs 1 and 2 independently.
[0228]
Further, in this embodiment, as shown in FIG. 15, a direct memory access controller (DMAC) is connected to IAB1 and IDB1 in the same manner as CPU 1 and added to the single chip microcomputer of FIG. The CPU 1 and the DMAC can be operated exclusively with each other based on the bus right arbitration of the bus controller.
[0229]
That is, the DMAC performs data transfer when the CPU 1 sets a predetermined control bit as “1” as an activation factor, and when a predetermined signal is given to the DMA request terminal or the DMA request terminal. It has an external request function to perform, and the transfer mode is the auto request, in the burst mode in which the CPU 1 is stopped and the bus is exclusively used for data transfer, or the bus right is released for each transfer and alternated with the CPU 1 This is possible by having a cycle steal mode in which data is transferred while operating in the same manner.
[0230]
Further, data transfer can be performed using the interrupt request signal as an activation request signal, and higher speed data transfer is possible than the CPU 2 performs data transfer by interrupt.
[0231]
Further, the bus arbitration may be performed in a time division manner in addition to the read / write conflict. For example, a bus right is given to CPU 1 and CPU 2 every 8 states. If the bus does not end during 8 states, the operation continues until it ends. For example, the bus right may be given to CPU 1 by 4 states and CPU 2 by 12 states.
[0232]
(Example 2)
FIG. 16 is a block diagram showing a single chip microcomputer according to another embodiment of the present invention, and FIG. 17 is an operation timing chart of a bus in the single chip microcomputer according to this embodiment.
[0233]
The single-chip microcomputer of this embodiment is different from that of the first embodiment in that IAB1 and IAB2, IDB1 and IDB2 are shared to form IAB / IDB, and the data bus width is 32 bits. Similarly, ROM1, ROM2, and RAM1 And RAM 2 are used in common as a read-only memory (ROM: readable storage means) / random access memory (RAM), which can simultaneously read / write 32 bits.
[0234]
CPU 1 (first data processing device) and CPU 2 (second data processing device) read / write ROM / RAM using the internal address bus (IAB) / internal data bus (IDB) in a time-sharing manner. Write. As described above, these CPU1 / 2 instructions are 16-bit units, and the minimum instruction is executed in one state.
[0235]
In other words, 16 bits are read in one state for one CPU 1/2, and the instruction read amount and the instruction execution amount are equal. If an instruction is read with 32 bits, the number of instruction reads can be halved and the frequency of use of IAB / IDB and ROM / RAM can be halved. Therefore, the CPU 1 and the CPU 2 can alternately read instructions from the ROM by using IAB / IDB, and can be executed in parallel.
[0236]
Actually, even if an instruction is read with 32 bits, such as a branch instruction, 16 bits are wasted, and the frequency of use cannot be reduced during data access, but complete parallel operation cannot be performed. As described above, the number of times the instruction is read is large, and the processing speed is not reduced so much as in the first embodiment. Further, by sharing the ROM / RAM, the physical scale can be reduced, or the memory capacity used by the CPU 1/2 can be arbitrarily set.
[0237]
Next, an example of the operation timing of the internal bus will be described with reference to FIG.
[0238]
The CPU 1/2 program is the same as that shown in FIG. 6, and the right to use the bus is that CPU 1/2 that used the previous bus has no priority, and in other cases, the CPU 2 has priority.
[0239]
For example, IAB1 / 2 is output in synchronism with φ #, and the read of the CPU1 / 2 with respect to the ROM and RAM is performed in one state in a batch of 32 bits. However, this is limited to 32-bit data starting from a multiple of 4.
[0240]
First, IAB1 / 2 is output in one state in synchronization with φ #, and is not particularly limited, but is latched in synchronization with φ in ROM and RAM. The corresponding read data is output in synchronization with φ #, and is fetched by the CPU 1/2 during the period in which φ # is in the active state.
[0241]
Similarly to the above, read / write with respect to RAMP is performed in two states, and read / write with respect to I / O is performed in three states. IAB1 / 2 synchronized with φ # is synchronized with φ by the bus controller. In this case, the addresses m and n where the head instruction exists are set to a multiple of 4.
[0242]
At T1, instruction fetch from the ROM of CPU1 / 2 is requested, but instruction fetch of CPU2 is prioritized and address m is output to IAB.
[0243]
At T2, the instruction code (first and second words of the BCLR instruction) read from the ROM to the IDB is fetched by the CPU 2, and the instruction fetch address n of the CPU 1 is output to the IAB.
[0244]
At T3, the CPU 1 fetches an instruction code (CMP, BEQ instruction) read from the ROM to the IDB, and the CPU 2 outputs an address SSR to the IAB. The use of the PAB / PDB of the CPU 2 is automatically permitted. In this case, since three SCI reads are required, the CPU2 standby signal goes high.
[0245]
At T4, the contents of IAB are output to PAB, and the contents of SCI register SSR are read. This read data is obtained at T6. On the other hand, the CPU 1 requests an instruction fetch, but since the CPU 2 is using the bus, it is put on hold and the CPU 1 standby signal becomes high level.
[0246]
At T5, both CPU 1/2 are set in a standby state.
[0247]
At T6, the CPU 2 fetches the data read from the SCI register SSR via the PDB and IDB. The CPU 2 requests the next instruction fetch, but the instruction fetch of the CPU 1 is prioritized, the CPU 1 standby signal becomes low level, and the CPU 2 standby signal remains at high level. In this case, the instruction fetch address n + 4 of the CPU 1 is output to the IAB.
[0248]
At T7, the CPU 1 captures the instruction code (first word of the BTST instruction) read from the ROM to the IDB. In this case, the CPU 1 requests to fetch the branch destination instruction. However, the instruction fetch of the CPU 2 is prioritized, the CPU 2 standby signal becomes low level, and the CPU 1 standby signal becomes high level.
[0249]
At T8, the CPU 2 fetches the next instruction code read from the ROM to the IDB. In this case, the CPU1 standby signal becomes a low level, and the instruction fetch address N1 of the CPU1 is output to the IAB.
[0250]
At T9, the CPU 1 fetches the instruction code read from the ROM to the IDB, but this is not executed because the branch condition is not satisfied. The first word of the previously fetched BTST instruction becomes valid. In this case, the CPU 1 requests the next instruction fetch, but the CPU 2 has priority, and the CPU 1 standby signal becomes high level.
[0251]
On the other hand, the CPU 2 outputs the address SSR to the IAB. The use of the PAB / PDB of the CPU 2 is automatically permitted. Here, since the SCI read requires three states, the CPU2 standby signal becomes high level.
[0252]
At T10, the contents of IAB are output to PAB, and CPU 2 outputs data to be written to address SSR to PDB via IDB. Here, the CPU 1 is in a standby state.
[0253]
At T11, the CPU2 standby signal becomes low level.
[0254]
At T12, the CPU1 standby signal goes low, and the instruction fetch address n + 6 of CPU1 is output to the IAB.
[0255]
At T13, the CPU 1 captures the instruction code (second word of the BTST instruction) read from the ROM to the IDB. In this case, the CPU 1 requests to read the address PORT, and the CPU 2 requests to fetch an instruction from the ROM. However, the CPU 2 has priority, and the CPU 1 standby signal becomes high level. Here, the instruction fetch address m + 8 of the CPU 2 is output to the IAB.
[0256]
At T14, the CPU 2 fetches the next instruction code read from the ROM to the IDB. In this case, the CPU 1 outputs the address PORT to the IAB. Here, since three states are required for reading the input / output port, the CPU1 standby signal becomes high level again.
[0257]
At T15, the contents of IAB are output to PAB, and the contents of register PORT of the input / output port are read. This read data is obtained at T17. On the other hand, the CPU 2 requests an instruction fetch, but since the CPU 1 is using the bus, it is put on hold and the CPU 2 standby signal becomes high level.
[0258]
As described above, in this embodiment, the execution time is longer than that in the first embodiment shown in FIG. 6, but the execution time can be shortened as compared with the case where it is realized by at least one CPU 1/2.
[0259]
First, the operation of saving or restoring the internal state of the CPU 1/2 by interruption or subroutine branching can be excluded. Also, the two CPUs 1/2 can be made shorter than simply operating alternately. This is because a larger amount of instructions that can be executed from the ROM by the CPU1 / 2 in unit time can be read in unit time, and a time that does not require the use of the bus is created, which is available to the other CPU1 / 2. It is.
[0260]
This is particularly effective when the program is arranged in the built-in ROM. Most of the CPU reads / writes are instruction reads, and the internal memory improves the reading speed relative to the external memory. This is because the width of the bus can be easily increased.
[0261]
At this time, even if the CPU 2 is a data processing device or data transfer device such as the DMAC or DTC, the CPU 2 can similarly perform data transfer with a minimum reduction in the processing speed of the CPU 1. This is particularly effective for the DTC in which transfer information needs to be read from the RAM prior to data transfer.
[0262]
Therefore, according to the single chip microcomputer of this embodiment, the CPU 1 and CPU 2 as data processing devices and the ROM as readable storage means are the main components, and the IAB / IDB and ROM / RAM are shared. In addition to the first embodiment, the following effects can be obtained.
[0263]
That is, by connecting a plurality of CPUs 1/2 to an IAB / IDB that can read a larger number of bytes per unit time than the number of instructions that CPU 1/2 can execute per unit time, Uses IAB / IDB in a divided manner to enable substantially parallel operation. Arbitrarily allocates and uses common ROM / RAM to improve the processing speed of single-chip microcomputers and improve resource utilization efficiency. can do.
[0264]
The invention made by the present inventor has been specifically described based on the first and second embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0265]
For example, the specific circuit configuration of the bus can be variously changed, and the IAB1 and IDB1 may be directly connected to the PAB and PDB. In this case, it is only necessary that the CPU 1 and the CPU 2 can read and execute the program in parallel, and this increases the frequency of restricting the operations mutually, but the physical scale may be reduced in some cases.
[0266]
Further, RAM1, RAM2, and RAMP may be a single functional block.
[0267]
Further, the number of CPUs can be three or more. In this case, a plurality of CPUs are connected to the first bus, the bus is used in a time-sharing manner, and another one or more CPUs are connected to the first bus. You may connect to 2 buses.
[0268]
The built-in ROM may be a memory that stores programs to be executed by the CPU, such as an EEPROM and a flash memory, in addition to the mask ROM and PROM. The ROM 1 and the ROM 2 may be different.
[0269]
Furthermore, there are no restrictions on the type, function, number, etc. of functional blocks that require interrupt processing, such as functional blocks that require interrupts such as timers and SCI, or pulse output circuits.
[0270]
In the above description, the case where the invention mainly made by the present inventor is applied to a single chip microcomputer which is a field of use of the invention has been described. However, the present invention is not limited to this and is applicable to other semiconductor integrated circuit devices. The present invention can be applied to a semiconductor integrated circuit device including at least a plurality of data processing devices.
[0271]
【The invention's effect】
Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
[0272]
(1). It is possible to read instructions stored in two readable storage means independent by a bus parallel to two data processing devices, or the bus width can be expanded to allow the data processing device to execute in unit time. Multiple memory means can be selected simultaneously in a single-chip microcomputer or semiconductor integrated circuit device that has the function of supplying instructions capable of operating two data processing devices in parallel by enabling the reading of more instructions than the number of instructions By simultaneously writing to or simultaneously reading from a plurality of storage means, the restriction on the number of data processing channels due to interrupts can be eliminated, and the data processing content can be made arbitrary. Reduction in size, restriction on the number of transfer channels, or single-chip microcomputer or semiconductor integrated circuit The manufacturing cost of the apparatus can be reduced.
[0273]
(2) According to (1), the first and second data processing devices can be operated simultaneously, so that the processing speed of the single chip microcomputer or the semiconductor integrated circuit device can be improved.
[0274]
(3) According to the emulation processor of the single-chip microcomputer or semiconductor integrated circuit device, and further the emulator, the two data processing devices can be stopped independently, so that the debugging efficiency can be improved. Become.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a single-chip microcomputer that is Embodiment 1 of the present invention.
FIG. 2 is an explanatory diagram of an entire address map in the single chip microcomputer according to the first embodiment;
3 is a block diagram of a bus connection state of the single chip microcomputer according to the first embodiment. FIG.
FIG. 4 is a schematic block diagram of an interrupt controller according to the first embodiment.
FIG. 5 is a schematic block diagram of an interrupt request bit and an interrupt permission circuit according to the first embodiment.
FIG. 6 is an operation timing chart of the bus in the first embodiment.
FIG. 7 is a schematic block diagram of a low power consumption state control circuit according to the first embodiment.
8 is an explanatory diagram of a register configuration for controlling input / output ports in Embodiment 1. FIG.
FIG. 9 is a schematic block diagram of an input / output port according to the first embodiment.
10 is an address map of the PROM in Embodiment 1. FIG.
11 is a block diagram of the main part of the PROM mode in Embodiment 1. FIG.
12 is a block diagram of a main part of a test mode in Embodiment 1. FIG.
13 is a schematic block diagram of an emulation processor in Embodiment 1. FIG.
FIG. 14 is a schematic block diagram of an emulator according to the first embodiment.
FIG. 15 is a block diagram showing a modification of the single chip microcomputer in the first embodiment.
FIG. 16 is a block diagram showing a single-chip microcomputer that is Embodiment 2 of the present invention.
17 is an operation timing chart of a bus in the single chip microcomputer of Embodiment 2. FIG.
[Explanation of symbols]
CPU1 Central processing unit (first data processing unit)
CPU2 Central processing unit (second data processing unit)
ROM1 Read-only memory (first readable storage means)
ROM2 Read-only memory (second readable storage means)
RAM1, RAM2, RAMP Random access memory
SCI serial communication interface
A / D A / D converter
IOP0 to IOP11 I / O port (data I / O means)
IAB1 internal address bus (first bus)
IAB2 internal address bus (second bus)
PAB internal address bus (third bus)
IDB1 internal data bus (first bus)
IDB2 internal data bus (second bus)
PDB internal data bus (third bus)
DMAC direct memory access controller
ROM read-only memory (readable storage means)
RAM random access memory
IAB internal address bus
IDB internal data bus

Claims (8)

A semiconductor integrated circuit device having first and second data processing devices, bus control means, first and second readable storage means, and data input / output means,
The first data processing device, the bus control means, and the first readable storage means are interconnected by a first bus,
The second data processing device, the bus control means, and the second readable storage means are interconnected by a second bus;
And the bus control means and the data input / output means are connected to each other by a third bus,
The bus control means selects whether to connect the first bus and the second bus to the third bus, and reads the first data processing device using the first bus. , It is possible to perform reading using the second bus of the second data processing device in parallel,
The semiconductor integrated circuit device is connected to an external bus and outputs data from the first data processing device to the outside via the first bus, or to the first data processing device via the external bus. Allows control to input data ,
The data input / output means includes register means, and at least one register means of the register means included in the data input / output means has a plurality of bits, and the first and second data processing are performed according to the state of another register means. A semiconductor integrated circuit device, which can be selected from which of the devices is writable . The semiconductor integrated circuit device according to claim 1,
The data input / output means can make an interrupt request,
And an interrupt control means for inputting an interrupt signal output from the data input / output means to the interrupt control means. The interrupt control means is connected to each of the first and second data processors. 1. Output the second interrupt request signal.
The interrupt control means has data processing device selection means, first and second interrupt priority order judgment means, and first and second mask control means, and the interrupt signal is activated. In response, it is possible to select which of the first and second interrupt request signals is activated.
The data processing device selection means selects whether the predetermined interrupt signal is requested to the first or second interrupt priority determination means according to a register setting,
The first and second interrupt priority determining means determine the priority of the input interrupt signal, and output the determination results to the first and second mask control means, respectively.
The first and second mask control means request the first and second data processing devices for interrupts in the interrupt mask states of the first and second data processing devices, respectively. The semiconductor integrated circuit device according to claim 1, wherein at least one interrupt is supplied to the first and second interrupt priority determining means without going through the data processing device selecting means. The semiconductor integrated circuit device according to claim 1, wherein:
A semiconductor integrated circuit device characterized in that the second data processing device has writable register means, and that it is possible to request an interrupt from the first data processing device according to the state of the register means. . A semiconductor integrated circuit device according to claim 1, 2 or 3,
It has a terminal requesting an interrupt, and it is possible to request an interrupt to both the first and second data processing devices in response to a predetermined signal change occurring at the terminal. A semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 4 ,
2. A semiconductor integrated circuit device according to claim 1, wherein the register means capable of selecting which of the first data processing device and the second data processing device can be written controls a terminal state. A semiconductor integrated circuit device according to claim 1, 2, 3, 4 or 5 ,
Overall setting for setting an overall stop state for stopping the entire semiconductor integrated circuit device, a first standby state for stopping the first data processing device, and a second standby state for stopping the second data processing device, respectively. A stop unit, a first standby unit, and a second standby unit, wherein the first and second data processing devices are predetermined in the overall stop state, the first standby state, and the second standby state. Transition in response to execution of the transition command, and when the first data processing device executes the transition command for setting the overall stop state, the second data processing device The semiconductor integrated circuit device shifts to the overall stop state if the standby state is 2, and transitions to the first standby state if the second data processing device is not the second standby state. . A semiconductor integrated circuit device according to claim 1, 2, 3, 4, 5 or 6 ,
A test mode setting means; and a buffer means. The buffer means inputs an address, a read signal or a write signal, and an address space selection signal when the test mode setting means sets a test mode, and the read mode Data is input / output according to a signal or a write signal, and the address space selection signal specifies which address space of the first or second data processing device the input address corresponds to. The readable storage means or the data input / output means is selected according to the address space selection signal and the address, and the readable storage means or the data input / output means is selected according to the read signal or write signal. Is characterized in that it can be read or written Integrated circuit device. A semiconductor integrated circuit device according to claim 1, 2, 3, 4, 5, 6 or 7 ,
The first and second readable storage means are first and second electrically writable storage means, each having a write mode setting means and a buffer means. When the write mode setting means sets the write mode, an address, data, and a control signal are input, and writing is performed to the first and second electrically writable storage means according to the control signal. The semiconductor integrated circuit device is characterized in that the first and second electrically writable storage means are arranged at continuously writable addresses.

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