JP5061272B2 - Serial data transmitter / receiver - Google Patents

Description

  The present invention relates to a serial data transmission / reception apparatus that transmits / receives serial data and a related technology.

  Non-Patent Document 1 introduces a computer system including an input / output controller having a serial port.

David A. Patterson / John L. Hennessy, Mitsuaki Narita, “Computer Configuration and Design (2)”, 2nd edition, Nikkei Business Publications, May 17, 1999, p. 639,640

  However, Non-Patent Document 1 does not disclose a specific transmission / reception procedure by the input / output controller.

  Therefore, the present invention can efficiently exchange transmission / reception data with other functional units, can contribute to the reduction of processing of other functional units, and can efficiently use shared resources. It is an object of the present invention to provide a serial data transmission / reception device and related technology.

  According to an aspect of the present invention, a serial data transmission / reception device is a serial data transmission / reception device that transmits / receives serial data, serial / parallel conversion means for converting received serial data into parallel data, and parallel data into serial data. A parallel / serial conversion means for converting and transmitting to a transmission / reception buffer configured on a shared memory provided outside the serial data transmission / reception device and shared by the serial data transmission / reception device and another functional unit A transmission / reception buffer access means for writing the reception data and reading the transmission data from the transmission / reception buffer, wherein the serial / parallel conversion means monitors the reception data and changes the first reception data after setting the reception start The received data from the point as valid received data. Sent to the buffer access means, the parallel / serial conversion means transmits the transmission data received from the transceiver buffer access means after setting the start of the transmission as a valid transmission data.

  According to this configuration, a serial data transmission / reception buffer, that is, a transmission / reception buffer is configured on a shared memory with other functional units, and the serial data transmission / reception device does not pass through other functional units (for example, a CPU). Since it is possible to access the shared memory directly, it is easy to send and receive large sizes, and in order for other functional units to acquire received data or set transmit data, simply access the shared memory. Therefore, it is possible to efficiently exchange transmission / reception data with other functional units (for example, a CPU). When serial data transmission / reception is not performed, the transmission / reception buffer area can be used by another functional unit for other purposes. Furthermore, since reception data is stored in the transmission / reception buffer from the change point of the first reception data after the start of reception is set, useless reception data before the first valid reception data may be stored in the shared memory. Therefore, it is possible to efficiently process received data by other functional units (for example, a CPU).

  In this serial data transmission / reception apparatus, when the serial / parallel conversion means detects the change point of the first reception data after setting the reception start, the transmission / reception buffer as valid reception data including 1 bit before the change is received. Output to access means.

  According to this configuration, since the 1 bit before the change at the change point of the first received data is also stored in the transmission / reception buffer, the detection processing of the start bit of the packet by other functional units (for example, CPU, etc.) is higher. Can be done with precision.

  In this serial data transmission / reception apparatus, the parallel / serial conversion means stops data transmission without receiving an instruction when transmission of a predetermined amount of data is completed.

  According to this configuration, when transmission of a preset amount of data is completed, the transmission is automatically stopped, so that invalid data stored in the transmission / reception buffer is not erroneously transmitted.

  In the serial data transmission / reception device, the start and end addresses of the transmission / reception buffer area are set by the function unit outside the serial data transmission / reception device at the address of the shared memory.

  According to this configuration, since the position and size of the transmission / reception buffer area on the shared memory can be set freely, a necessary and sufficient amount of area is reserved for the transmission / reception buffer, and other functional units use the other areas. By doing so, it becomes possible to efficiently use the shared memory as the entire system.

  In this serial data transmitter / receiver, the start address and the end address of the transmission / reception buffer area can be set to arbitrary values by the external functional unit.

  In this serial data transmission / reception device, the transmission / reception buffer access means includes a pointer indicating a reading position of transmission data from the transmission / reception buffer or a writing position of reception data to the transmission / reception buffer, and the value of the pointer is a value of data transmission Alternatively, it is incremented every time reception is performed, and is reset to the start address when the value of the pointer matches the end address.

  According to this configuration, a part of the shared memory, in this case, the transmission / reception buffer can be used as a ring buffer.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is incorporated. When it is necessary to indicate which bit of the signal, [a: b] or [a] is added after the signal name. [A: b] means the a-th bit to the b-th bit of the signal, and [a] means the a-th bit of the signal. “0b” means a binary number, and “0x” means a hexadecimal number.

  FIG. 1 is a block diagram showing an internal configuration of a multimedia processor 1 according to the embodiment of the present invention. As shown in FIG. 1, this multimedia processor includes an external memory interface 3, a DMAC (direct memory access controller) 4, a central processing unit (hereinafter referred to as “CPU”) 5, a CPU local RAM 7, and a rendering processing unit. (Hereinafter referred to as “RPU”) 9, color palette RAM 11, sound processing unit (hereinafter referred to as “SPU”) 13, SPU local RAM 15, geometry engine (hereinafter referred to as “GE”) 17, Y Sorting unit (hereinafter referred to as “YSU”) 19, external interface block 21, main RAM access arbiter 23, main RAM 25, I / O bus 27, video DAC (digital to analog con) Erter) 29, audio DAC block 31, and A / D converter (hereinafter, referred to as "ADC".) 33 comprises a. When it is not necessary to distinguish between the main RAM 25 and the external memory 50, they are referred to as “memory MEM”.

  The CPU 5 executes programs stored in the memory MEM to perform various calculations and control of the entire system. Further, the CPU 5 can make a program and data transfer request to the DMAC 4, and can directly fetch the program code from the external memory 50 and directly access the external memory 50 without going through the DMAC 4.

  The I / O bus 27 is a bus for system control using the CPU 5 as a bus master, and is a functional unit (external memory interface 3, DMAC 4, RPU 9, SPU 13, GE 17, YSU 19, and external interface block 21) that is a bus slave. It is used to access the control registers and local RAMs 7, 11 and 15. In this way, these functional units are controlled by the CPU 5 through the I / O bus 27.

  The CPU local RAM 7 is a RAM dedicated to the CPU 5, and is used as a stack area for saving data at the time of a subroutine call or interruption, a storage area for variables handled only by the CPU 5, and the like.

  The RPU 9 generates a three-dimensional image composed of polygons and sprites in real time. Specifically, the RPU 9 reads each structure instance of the polygon structure array and each structure instance of the sprite structure array sorted by the YSU 19 from the main RAM 25, executes a predetermined process, and executes a screen ( An image is generated for each horizontal line according to the scanning of the display area. The generated image is converted into a data stream indicating a composite video signal waveform and output to the video DAC 29. Further, the RPU 9 has a function of making a DMA transfer request to the DMAC 4 for taking in texture pattern data of polygons and sprites.

  The texture pattern data is two-dimensional pixel array data that is pasted on a polygon or sprite. Each pixel data is a part of information for designating an entry in the color palette RAM 11. Hereinafter, the pixels of the texture pattern data are referred to as “texels”, and are used separately from “pixels” that indicate the pixels constituting the image displayed on the screen. Therefore, the texture pattern data is a set of texel data.

  The polygon structure array is a structure array for polygons that are polygonal graphic elements, and the sprite structure array is a structure array for sprites that are rectangular graphic elements parallel to the screen. The elements of the polygon structure array are called “polygon structure instances”, and the elements of the sprite structure array are called “sprite structure instances”. However, when it is not necessary to distinguish between the two, they may be simply referred to as “structure instances”.

  Each polygon structure instance stored in the polygon structure array contains display information for each polygon (vertex coordinates on the screen, information on texture patterns in texture mapping mode, and color data in Gouraud shading mode (RGB color components)) In other words, one polygon corresponds to one polygon structure instance. Each sprite structure instance stored in the sprite structure array is display information for each sprite (including information on coordinates and texture patterns on the screen), and one sprite structure instance corresponds to one sprite structure instance. Yes.

  The video DAC 29 is a digital / analog converter for generating an analog video signal. The video DAC 29 converts the data stream input from the RPU 9 into an analog composite video signal, and outputs it from a video signal output terminal (not shown) to a television monitor or the like (not shown).

  In the present embodiment, the color palette RAM 11 is composed of a color palette of 512 colors, that is, 512 entries. The RPU 9 refers to the color palette RAM 11 using the texel data included in the texture pattern data as part of an index for designating the entry of the color palette, and converts the texture pattern data into color data (RGB color components).

  The SPU 13 generates PCM (pulse code modulation) waveform data (hereinafter referred to as “wave data”), amplitude data, and main volume data. Specifically, the SPU 13 generates wave data for a maximum of 64 channels and time-division multiplexes, generates envelope data for a maximum of 64 channels and multiplies the channel volume data, and time-divisions the amplitude data. Multiplex. Then, the SPU 13 outputs main volume data, time-division multiplexed wave data, and time-division multiplexed amplitude data to the audio DAC block 31. Further, the SPU 13 has a function of making a DMA transfer request for taking in wave data and envelope data to the DMAC 4.

  The audio DAC block 31 converts the wave data, amplitude data, and main volume data input from the SPU 13 into analog signals, and multiplies the results to generate analog audio signals. This analog audio signal is output from an audio signal output terminal (not shown) to an audio input terminal (not shown) of a television monitor or the like (not shown).

  The SPU local RAM 15 stores parameters used when the SPU 13 performs wave reproduction and envelope generation (for example, storage addresses and pitch information of wave data and envelope data).

  The GE 17 executes a geometric operation for displaying a three-dimensional image. Specifically, the GE 17 performs operations such as matrix product, vector affine transformation, vector orthogonal transformation, perspective projection transformation, vertex lightness / polygon lightness calculation (vector inner product), and polygon back surface culling processing (vector outer product).

  The YSU 19 sorts each structure instance of the polygon structure array and each structure instance of the sprite structure array stored in the main RAM 25 according to the sorting rules 1 to 4. In this case, the polygon structure array and the sprite structure array are separately sorted.

  Hereinafter, the sorting rules 1 to 4 by the YSU 19 will be described, but before that, the coordinate system will be described. A two-dimensional coordinate system used for actual display on a display device (not shown) such as a television monitor is called a screen coordinate system. In this embodiment, the screen coordinate system is composed of a two-dimensional pixel array of 2048 pixels in the horizontal direction and 1024 pixels in the vertical direction. The coordinate origin is at the upper left, the right direction corresponds to the positive X axis, and the lower direction corresponds to the positive Y axis. However, the area actually displayed is not the entire space of the screen coordinate system but a part of the space. This display area is called a screen.

  Sort rule 1 is to rearrange the polygon structure instances in ascending order of the minimum Y coordinate. The minimum Y coordinate is the smallest Y coordinate among the Y coordinates of all the vertices of the polygon. The Y coordinate is the vertical coordinate of the screen, and the downward direction is the positive direction. Sort rule 2 is to arrange the polygon structure instances in descending order of the depth value for a plurality of polygons having the same minimum Y coordinate.

  However, the YSU 19 regards a plurality of polygons having pixels displayed on the first line of the screen as being the same even if the minimum Y coordinate is different, so that the sorting rule 2 is not the sorting rule 1. According to the above, the polygon structure instances are rearranged. That is, when there are a plurality of polygons having pixels displayed on the top line of the screen, the minimum Y coordinate is regarded as the same, and they are rearranged in descending order of the depth value. This is the sort rule 3.

  Sort rules 1 to 3 are applied even in the case of interlaced scanning. However, in the sorting for displaying the odd field, the minimum Y coordinate of the polygon displayed on the odd line and / or the minimum Y coordinate of the polygon displayed on the even line immediately before the odd line are the same. As a result, the sorting by the sorting rule 2 is performed. However, the first odd line is excluded. This is because there is no previous even line. On the other hand, in the sorting for displaying the even field, the minimum Y coordinate of the polygon displayed on the even line and / or the minimum Y coordinate of the polygon displayed on the odd line immediately before the even line are the same. As a result, the sorting by the sorting rule 2 is performed. This is sort rule 4.

  Sort rules 1 to 4 for sprites are the same as sort rules 1 to 4 for polygons, respectively.

  The external memory interface 3 is responsible for reading data from the external memory 50 and writing data to the external memory 50 via the external bus 51. In this case, the external memory interface 3 arbitrates external bus access request factors (factors requesting access to the external bus 51) from the CPU 5 and the DMAC 4 in accordance with an EBI priority table (not shown), and any one of the external buses Select the access request factor. Then, access to the external bus 51 is permitted for the selected external bus access request factor. The EBI priority table is a table that defines priorities of a plurality of types of external bus access request factors from the CPU 5 and external bus access request factors from the DMAC 4.

  As external bus access request factors, there are a block transfer request by an IPL (initial program loader) (not shown) included in the CPU, a data access request by the CPU 5, an instruction fetch request by the CPU 5, and a DMA request by the DMAC 4.

  The DMAC 4 performs DMA transfer between the main RAM 25 and the external memory 50 connected to the external bus 51. In this case, the DMAC 4 arbitrates DMA transfer request factors (factors that request DMA transfer) from the CPU 5, RPU 9, and SPU 13 according to a DMA priority table (not shown), and selects any one DMA transfer request factor. . Then, a DMA request is made to the external memory interface 3. The DMA priority table is a table that defines the priority of DMA request factors from the CPU 5, RPU 9, and SPU 13.

  The DMA request factors of the SPU 13 include (1) transferring wave data to the wave buffer and (2) transferring envelope data to the envelope buffer. The wave buffer and envelope buffer are temporary storage areas for wave data and envelope data set on the main RAM 25, respectively. The arbitration between the two DMA request factors of the SPU 13 is performed by hardware (not shown) in the SPU 13, and the DMAC 4 is not concerned.

  As a DMA request factor of the RPU 9, there is transferring the texture pattern data to the texture buffer. The texture buffer is a temporary storage area for texture pattern data set on the main RAM 25.

  The DMA request factors of the CPU 5 include (1) page transfer when a page miss occurs in virtual storage management, and (2) data transfer requested by an application program or the like. When a plurality of DMA transfer requests are generated simultaneously in the CPU 5, the arbitration is performed by software executed by the CPU 5, and the DMAC 4 is not concerned.

  The external interface block 21, which is one of the features of the present invention, is an interface with the peripheral device 54 and includes a 24-channel programmable digital input / output port. Hereinafter, these input / output ports are collectively referred to as “PIO”. Moreover, when distinguishing each PIO, each is described as PIO0-PIO23. Each 24-channel PIO has a mouse interface function for 4 channels, a light gun interface function for 4 channels, a general-purpose timer / counter for 2 channels, an asynchronous serial interface function for 1 channel, and a channel for 1 channel. Internally connected to one or more of the general-purpose parallel / serial conversion port functions.

  The ADC 33 is connected to 4-channel analog input ports, and converts the analog signal input from the analog input device 52 into a digital signal via these. For example, an analog input signal such as a microphone sound is sampled and converted into digital data.

  The main RAM access arbiter 23 arbitrates an access request to the main RAM 25 from the functional units (CPU 5, RPU 9, GE 17, YSU 19, DMAC 4, and external interface block 21 (general-purpose parallel / serial conversion port), and has any function. Grant access to the unit.

  The main RAM 25 is used as a work area, a variable storage area, a virtual storage management area, and the like for the CPU 5. Further, the main RAM 25 is a storage area for data that the CPU 5 delivers to other functional units, a storage area for data that the RPU 9 and SPU 13 have acquired from the external memory 50 by DMA, a storage area for input data and output data for the GE 17 and YSU 19, etc. Also used as Further, it is also used as a transmission / reception data storage area of a general-purpose parallel / serial conversion port 91 (described later) in the external interface block, which is a feature of the present invention.

  The external bus 51 is a bus for accessing the external memory 50. It is accessed from the CPU 5 and the DMAC 4 via the external memory interface 3. The address bus of the external bus 51 is composed of 30 bits, and an external memory 50 having a maximum of 1 Gbyte (= 8 Gbit) can be connected thereto. The data bus of the external bus 51 is composed of 16 bits, and can connect an external memory 50 having a data bus width of 8 bits or 16 bits. External memories having different data bus widths can be connected at the same time, and a function of automatically switching the data bus width according to the external memory to be accessed is provided.

  FIG. 2 is a block diagram showing an internal configuration of the external interface block 21 of FIG. Referring to FIG. 2, external interface block 21 includes PIO setting unit 55, mouse interfaces 60 to 63, light gun interfaces 70 to 73, general-purpose timer / counter 80, asynchronous serial interface 90, and general-purpose parallel / serial conversion. Port 91 is included.

  The PIO setting unit 55 is a functional block that performs various settings of PIO 0 to PIO 23 that are ports of input / output signals between the peripheral device 54 and the multimedia processor 1. Specifically, the PIO setting unit 55 sets the use as an input port / use as an output port, the presence / absence of an internal pull-up resistor, and the presence / absence of an internal pull-down resistor for each PIO. The PIO setting unit 55 sets connection / disconnection between each PIO and each function 60 to 63, 70 to 73, 80, 90, and 91. These settings are performed by the CPU 5 rewriting the value of a control register (not shown) in the PIO setting unit 55 through the I / O bus 27.

  Each of the mouse interfaces 60 to 63 is a functional block used for connection with a pointing device such as a mouse or a trackball. Mouse interfaces 60 to 63 for four channels are provided, and a maximum of four devices such as a mouse can be connected.

  Each of the mouse interfaces 60 to 63 is connected to corresponding four PIOs set as input ports, and two of the four PIOs are for the X axis and the other two are for the Y axis. Then, two rotary encoder signals that are 90 degrees out of phase are input to the X-axis and Y-axis, respectively. Each of the mouse interfaces 60 to 63 detects a change in the phase of the rotary encoder signal and increments / decrements the respective counters of the X coordinate and the Y coordinate. The count value of this counter is read by the CPU 5 through the I / O bus 27. Further, the count value of this counter can be rewritten by the CPU 5 through the I / O bus 27.

  Each of the light gun interfaces 70 to 73 is a functional block used for connecting a pointing device to a CRT (CRT) such as a light pen or a light gun. Light gun interfaces 70 to 73 for four channels are provided, and up to four devices such as light guns can be connected.

  Each of the light gun interfaces 70 to 73 is connected to a corresponding one PIO set as an input port. When the light gun interface 70 to 73 detects a rise (transition from low level to high level) in the signal input from the corresponding PIO, the value of the horizontal counter in the RPU 9 is latched, and at the same time, the rise is detected. The light gun interfaces 70 to 73 generate interrupt request signals IRQ0 to IRQ3 for the CPU 5.

  The CPU 5 reads the current value of the vertical counter in the RPU 9 and reads the value of the latched horizontal counter in the interrupt processing requested from the light gun interfaces 70 to 73, so that the input signal rises. The values of the vertical counter and the horizontal counter when detected can be known. That is, the CPU 5 can know which position on the CRT screen is pointed to by a device such as a light gun.

  In this case, the horizontal count can be latched and the interrupt request signals IRQ0 to IRQ3 can be generated not at the rising edge but at the falling edge (transition from the high level to the low level). Setting of rising / falling, enabling / disabling generation of interrupt request signals IRQ0 to IRQ3, and reading of the value of the horizontal counter are controlled by the CPU 5 through the I / O bus 27 in the light gun interfaces 70 to 73. This is done by accessing a register (not shown).

  The general purpose timer / counter 80 includes a programmable two-channel timer / counter that can be used in various applications. Each of the timers / counters functions as a timer when driven by a system clock inside the multimedia processor 1, and functions as a counter when driven by an input signal from a PIO (for example, PIO6) set as an input port.

  Individual settings can be made for each of the two-channel timer / counter. When the count value of the timer / counter reaches a predetermined value, an interrupt request signal IRQ4 for the CPU 5 can be generated.

  The setting as a timer or counter, the setting of a predetermined count value, and the setting of enabling / disabling generation of the interrupt request signal IRQ4 are performed by the CPU 5 via the I / O bus 27 in the control register (see FIG. (Not shown).

  The asynchronous serial interface 90 is a serial interface that performs full-duplex asynchronous serial data communication. “Full duplex” refers to a method capable of simultaneously transmitting and receiving data, and “start-stop synchronization” refers to a start bit and a stop bit without using a clock signal for synchronization. Used to indicate a method for synchronizing received data. The communication method of the asynchronous serial interface 90 is compatible with a UART (Universal Asynchronous Receiver Transmitter) used for a serial input / output port of a personal computer.

  Data to be transmitted to the outside is written into a transmission buffer (not shown) in the asynchronous serial interface 90 by the CPU 5 through the I / O bus 27. The transmission data written in the transmission buffer is converted from parallel data into a serial data string by the asynchronous serial interface 90, and is output bit by bit from the PIO (eg, PIO2) set as the output port.

  On the other hand, externally received data input bit by bit from a PIO set as an input port (for example, PIO1) is converted from a serial data string to parallel data by an asynchronous serial interface 90, and an asynchronous serial interface. The data is written in a reception buffer (not shown) in 90. The reception data written in the reception buffer is read out by the CPU 5 through the I / O bus 27.

  The asynchronous serial interface 90 generates an interrupt request signal IRQ5 to the CPU 5 when transmission of all data stored in the transmission buffer is completed or when reception data is fully stored in the reception buffer. Is possible. Writing data to the transmission buffer, reading data from the reception buffer, setting the communication baud rate, and enabling / disabling the generation of the interrupt request signal IRQ5 are performed by the CPU 5 in an asynchronous manner via the I / O bus. This is done by accessing a control register (not shown) in the serial interface 90. The communication baud rate is represented by the number of data modulations / second, and substantially corresponds to bps (bit per second).

  The general-purpose parallel / serial conversion port 91 is a serial interface that performs half-duplex serial data communication. “Half-duplex” refers to a scheme in which data transmission and reception are not performed simultaneously, and communication is performed while switching between transmission and reception.

  Transmission data read from the transmission / reception buffer SRB configured on the main RAM 25 is converted from parallel data into a serial data string by the general-purpose parallel / serial conversion port 91, and from a PIO (for example, PIO5) set as an output port. One bit is output at a time.

  On the other hand, received data input bit by bit from a PIO set as an input port (for example, PIO4) is converted from a serial data string to parallel data by a general-purpose parallel / serial conversion port 91, and a transmission / reception buffer SRB on the main RAM 25 is converted. Is written to.

  As described above, since the transmission / reception buffer SRB on the main RAM 25 is used for both transmission and reception, transmission / reception cannot be performed simultaneously. Writing of transmission data to the transmission / reception buffer SRB and reading of reception data from the transmission / reception buffer SRB are performed by the CPU 5 directly accessing the main RAM 25.

  The general-purpose parallel / serial conversion port 91 sends an interrupt request signal IRQ6 to the CPU 5 when data transmission of a predetermined number of bytes from the transmission / reception buffer SRB is completed or when reception data of a predetermined number of bytes is stored in the transmission / reception buffer SRB. Can be generated. The transmission / reception setting, transmission / reception buffer SRB area setting, communication baud rate setting, and interrupt request signal IRQ6 generation enable / disable setting are performed by the CPU 5 in the general-purpose parallel / serial conversion port 91 via the I / O bus. This is done by accessing the control register (see FIG. 7 described later).

  As described above, the general-purpose parallel / serial conversion port 91 has a function of accessing the transmission / reception buffer SRB configured on the main RAM 25. When accessing the main RAM 25, the general-purpose parallel / serial conversion port 91 issues an access request to the main RAM access arbiter 23. When access from the main RAM access arbiter 23 to the main RAM 25 is permitted, the general-purpose parallel / serial conversion port 91 actually receives read data from the main RAM 25 or sends write data to the main RAM 25.

  In FIG. 2, input / output signals PIO [23: 0] between the PIO setting unit 55 and the peripheral device 54 are input / output signals via the PIO of the same name.

  FIG. 3 is a block diagram showing an internal configuration of the general-purpose parallel / serial conversion port 91 of FIG. Referring to FIG. 3, general-purpose parallel / serial conversion port 91 includes a controller 900, a transmission / reception shift register 902, and a transmission / reception buffer register 904.

  The controller 900 controls the transmission / reception shift register 902 and the transmission / reception buffer register 904 according to the setting value written from the CPU 5 to the control register (see FIG. 7 described later) through the I / O bus 27, and controls the transmission / reception of data. Specifically, it is as follows.

  The controller 900 stores the data stored in the transmission / reception buffer register 904 in the transmission / reception buffer SRB on the main RAM 25 or stores the data read from the transmission / reception buffer SRB on the main RAM 25 in the transmission / reception buffer register 904. An access request is issued to the RAM access arbiter 23 and access permission is received.

  In addition, when data is transmitted and received, the controller 900 generates a serial data clock SDCK according to a communication baud rate set in a control register (see FIG. 7 described later), and outputs the serial data clock SDCK to the PIO setting unit 55. The PIO setting unit 55 outputs the serial data clock SDCK output from the controller 900 from the PIO (for example, PIO3) to the peripheral device 54.

  Further, the controller 900 has a function of issuing an interrupt request signal IRQ6 to the CPU 5 when transmission of the predetermined number of bytes is completed or when reception of the predetermined number of bytes is completed. However, enabling / disabling of generation of the interrupt request signal IRQ6 is set from the CPU 5 to the control register (see FIG. 7 described later) through the I / O bus 27.

  The transmission / reception buffer register 904 is a register having a 64-bit size, and operates according to control from the controller 900. Specifically, it is as follows.

  At the time of data transmission, the transmission / reception buffer register 904 temporarily stores the 64-bit data received from the main RAM access arbiter 23, and transmits / receives the stored data at the timing when the data transmission from the transmission / reception shift register 902 is completed. Transfer to register 902. Input data to the transmission / reception shift register 902 is parallel data.

  On the other hand, at the time of data reception, the transmission / reception buffer register 904 temporarily stores the 64-bit reception data transferred from the transmission / reception shift register 902 and stores the data stored at the timing when writing to the main RAM 25 is permitted. The data is output to the RAM access arbiter 23. Input data to the transmission / reception buffer register 904 is parallel data.

  The transmission / reception shift register 902 is a shift register having a size of 64 bits and operates according to control from the controller 900. Specifically, it is as follows.

  At the time of data transmission, the transmission / reception shift register 902 outputs 64-bit data received from the transmission / reception buffer register 904 bit by bit in synchronization with the serial data clock SDCK. That is, the transmission / reception shift register 902 converts 64-bit parallel data into a serial data string SDS and outputs it.

  On the other hand, at the time of data reception, the transmission / reception shift register 902 samples the received serial data string SDR in synchronization with the serial data clock SDCK, stores it one bit at a time, and transmits / receives the buffer at the timing when the reception data for 64 bits is prepared. Send to register 904. That is, the transmission / reception shift register 902 converts the received serial data string SDR into 64-bit parallel data and outputs it.

  Transmission data (transmission serial data) SDS is output from the PIO (for example, PIO5) through the PIO setting unit 55, and reception data (reception serial data) SDR is input from the PIO (for example, PIO4) through the PIO setting unit 55.

  FIG. 4 is a timing chart of data reception processing performed by the general-purpose parallel / serial conversion port 91 of FIG. As shown in FIG. 4A, the general-purpose parallel / serial conversion port 91 samples the received serial data SDR in synchronization with the serial data clock SDCK in FIG. The sampled data SDR is not stored in the transmission / reception shift register 902 during a period (before time t0) when reception enable is not set in the control register (see FIG. 7 described later). That is, as shown in FIG. 4C, the reception data SDR before time t0 set to reception enable is not treated as valid reception data VDR.

  However, even if reception enable is set, reception serial data SDR is not always stored in transmission / reception shift register 902 as valid reception data VDR. After receiving enable is set, data input to the transmission / reception shift register 902 is started as valid received data VDR from the time when a signal level change (high level to low level or low level to high level) is detected in the received serial data SDR. Is done.

  In this case, actually, the reception serial data SDR including one bit before the change when the signal level change is detected in the reception serial data SDR is handled as valid reception data VDR. In FIG. 4A, the change in the signal level from the high level to the low level of the received serial data SDR is detected at time t1, but one bit of the high level (that is, “1”) before the change is also effective. Treated as received data VDR.

  The general-purpose parallel / serial conversion port 91 can generate an interrupt request signal IRQ6 to the CPU 5 when reception of valid data VDR of the number of received bytes RB set in a control register (see FIG. 7 described later) is completed. is there. However, since the data reception continues even after the interrupt request signal IRQ6 to the CPU 5 is generated, the CPU 5 needs to read the received data from the transmission / reception buffer SRB before the reception data overflows the transmission / reception buffer SRB of the main RAM 25. Further, since the CPU 5 can read the current number of received bytes through the I / O bus 27, when generation of the interrupt request signal IRQ6 is disabled, the current number of received bytes is monitored. Therefore, it is necessary to read data from the transmission / reception buffer SRB so that buffer overrun due to writing of reception data on the transmission / reception buffer SRB does not occur.

  FIG. 5 is a timing chart of data transmission processing performed in the general-purpose parallel / serial conversion port 91 of FIG. As shown in FIG. 5B, the general-purpose parallel / serial conversion port 91 transmits the transmission serial data SDS in synchronization with the serial data clock SDCK in FIG. Data transmission from a PIO (for example, PIO5) as an output port is not performed during a period (before time t) in which transmission enable is not set in a control register 91 (see FIG. 7 described later). That is, as shown in FIG. 5B, transmission data before time t set to enable transmission holds the same level (value).

  After the time t when transmission is enabled, the value stored in the transmission / reception shift register 902 is output bit by bit from a PIO (eg, PIO5) as an output port. When the output of the set number of transmission bytes SB is completed, data transmission is automatically stopped (without receiving an instruction). When generation of the interrupt request signal IRQ6 to the CPU 5 is set to enable, the interrupt request signal IRQ6 for the CPU 5 is output at the transmission completion timing.

  FIG. 6 is an explanatory diagram of the transmission / reception buffer SRB for the general-purpose parallel / serial conversion port 91 configured on the main RAM 25 of FIG. As shown in FIG. 6, the transmission / reception buffer SRB configured on the main RAM 25 is arranged in the physical address space of the main RAM 25. The start address SAD and the end address EAD of the transmission / reception buffer SRB are set in a control register (see FIG. 7 described later) in the general-purpose parallel / serial conversion port 91. The values of the start address SAD and the end address EAD are indicated by physical addresses of the main RAM 25. The setting is performed by the CPU 5 through the I / O bus 27.

  This transmission / reception buffer SRB is treated as a ring buffer. That is, the value of the read address / write address indicating the current read position / write position is sequentially incremented and reset to the start address SAD when it matches the end address EAD. The CPU 5 can read the current value of the read address / write address indicated by the pointer RWP through the I / O bus 27.

  FIG. 7 is an explanatory diagram of a control register related to the general-purpose parallel / serial conversion port 91 of FIG. The general-purpose parallel / serial conversion port 91 includes a control register shown in FIG. Each control register is arranged at a corresponding I / O bus address in the figure.

  The control register SIOBaudrate in FIG. 7A sets addition data of a counter of a baud rate generator (not shown) for creating a serial data clock SDCK used for transmission / reception by the general-purpose parallel / serial conversion port 91. This corresponds to setting the communication baud rate. The control register SIOInterruptClear in FIG. 7B clears the interrupt factor of the general-purpose parallel / serial conversion port 91 by writing “1” in bit 0. That is, when “1” is written to bit 0 of the control register SIOInterruptClear while the interrupt request signal IRQ6 is asserted, the interrupt request signal IRQ6 is negated.

  The control register SIOInterruptEnable in FIG. 7C sets a bit 0 to “1” to generate a transmission completion interrupt for the general-purpose parallel / serial conversion port 91 or a reception completion interrupt for a predetermined number of bytes for the general-purpose parallel / serial conversion port 91. to approve.

  In the control register SIOSstatus of FIG. 7D, bit 0 indicates whether or not a predetermined number of bytes reception completion interrupt has occurred. When bit 1 is “0”, the general-purpose parallel / serial conversion port 91 performs transmission or reception. When bit 1 is “1”, transmission or reception is being executed. Bit 2 indicates whether data transmission is incomplete or complete.

  In the control register SIOControl of FIG. 7E, bit 0 indicates the direction of data transfer (reception mode / transmission mode), and bit 1 indicates enable / disable of data transmission / reception. The control register SIOBBufferTopAddress in FIG. 7F sets the start address SAD of the transmission / reception buffer SRB for storing transmission / reception data. The control register SIOBbufferEndAddress in FIG. 7G sets the termination address EAD of the transmission / reception buffer SRB for storing transmission / reception data.

  The control register SIOByteCount in FIG. 7 (h) sets the number of bytes of transmission data at the time of transmission, and sets the number of bytes at which an interrupt is generated each time it is received. The control register SIOCurrentBufferAddress in FIG. 7 (i) indicates the read address or write address indicated by the pointer RWP of the current transmission / reception buffer SRB.

  As described above, the serial data transmission / reception buffer, that is, the transmission / reception buffer SRB is configured on the main RAM 25 shared with other functional units such as the CPU 5, and the general-purpose parallel / serial conversion port 91 configures the CPU 5. Since it is possible to directly access the main RAM 25 without intervention, it is easy to transmit and receive a large size, and the CPU 5 simply accesses the main RAM 25 in order to acquire reception data or set transmission data. Therefore, the transmission / reception data can be efficiently exchanged with the CPU 5. Further, when serial data is not transmitted / received, it is possible for another functional unit to divert and use the area of the transmission / reception buffer SRB for other purposes. Furthermore, since reception data is stored in the transmission / reception buffer SRB from the change point of the first reception data after the start of reception is set, useless reception data before the first valid reception data is stored in the main RAM 25. Therefore, the received data can be efficiently processed by the CPU 5.

  Further, in the present embodiment, as shown in FIG. 4, since 1 bit before the change at the change point of the first received data SDR is also stored in the transmission / reception buffer SRB, the CPU 5 performs the process of detecting the start bit of the packet and the like. Can be done with higher accuracy.

  Furthermore, in this embodiment, the general-purpose parallel / serial conversion port 91 automatically stops data transmission without receiving an instruction when transmission of a predetermined amount of data is completed. For this reason, the illegal data stored on the transmission / reception buffer SRB is not erroneously transmitted.

  Furthermore, in the present embodiment, the start address SAD and the end address EAD of the area of the transmission / reception buffer SRB are set to arbitrary values by the CPU 5 with the physical address of the main RAM 25. As described above, since the position and size of the area of the transmission / reception buffer SRB can be freely set, a necessary and sufficient amount of area is secured for the transmission / reception buffer SRB, and other functional units use other areas. As a whole system, the main RAM 25 can be used efficiently.

  Furthermore, in the present embodiment, the value of the pointer RWP is incremented every time data is transmitted or received, and is reset to the start address SAD when the value of the pointer RWP matches the end address EAD. In this way, the transmission / reception buffer SRB is used as a ring buffer.

  In addition, this invention is not restricted to said embodiment, It is possible to implement in a various aspect in the range which does not deviate from the summary.

It is a block diagram which shows the internal structure of the multimedia processor 1 by embodiment of this invention. It is a block diagram which shows the internal structure of the external interface block 21 of FIG. FIG. 3 is a block diagram showing an internal configuration of a general-purpose parallel / serial conversion port 91 in FIG. 2. 3 is a timing chart of data reception processing performed by the general-purpose parallel / serial conversion port 91 of FIG. 3 is a timing chart of data transmission processing performed at the general-purpose parallel / serial conversion port 91 in FIG. 2. FIG. 2 is an explanatory diagram of a transmission / reception buffer SRB for a general-purpose parallel / serial conversion port 91 configured on the main RAM 25 of FIG. 1. FIG. 3 is an explanatory diagram of a control register related to the general-purpose parallel / serial conversion port 91 of FIG. 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Multimedia processor, 3 ... External memory interface, 4 ... DMAC, 5 ... CPU, 7 ... CPU local RAM, 9 ... RPU, 11 ... Color palette RAM, 13 ... SPU, 15 ... SPU local RAM, 17 ... GE, 19 ... YSU, 21 ... external interface block, 23 ... main RAM access arbiter, 25 ... main RAM, 27 ... I / O bus, 29 ... video DAC, 31 ... audio DAC block, 51 ... external bus, 50 ... external memory, 55: PIO setting unit, 91: serial conversion port, 900: controller, 902: transmission / reception shift register, 904: transmission / reception buffer register.

Claims (6)

A serial data transmitting / receiving device that transmits and receives serial data in half duplex ,
Serial / parallel conversion means for converting received serial data into parallel data;
Parallel / serial conversion means for converting parallel data into serial data and transmitting the data;
Transmission / reception buffer access means for writing reception data to a transmission / reception buffer configured on a shared memory provided outside the serial data transmission / reception device, and reading transmission data stored in the transmission / reception buffer,
The serial / parallel conversion means monitors the received data, and sends the received data as valid received data from the change point of the first received data after setting of the reception start to the transmission / reception buffer access means,
The parallel / serial conversion means transmits the transmission data received from the transceiver buffer access means after setting the start of the transmission as valid transmission data,
The shared memory in which the transmission / reception buffer is configured is shared by the serial data transmission / reception device and other functional units,
The transmission / reception buffer is a serial data transmission / reception device used for both transmission and reception .   When the serial / parallel conversion means detects the change point of the first received data after setting the reception start, it outputs to the transmission / reception buffer access means as valid received data including one bit before the change. Item 2. The serial data transmitting / receiving apparatus according to Item 1.   3. The serial data transmission / reception apparatus according to claim 1, wherein the parallel / serial conversion unit stops data transmission without receiving an instruction when transmission of a predetermined amount of data is completed.   4. The serial data transmission / reception apparatus according to claim 1, wherein a start address and an end address of the transmission / reception buffer area are set by an address of the shared memory by an external functional unit of the serial data transmission / reception apparatus.   5. The serial data transmitting / receiving apparatus according to claim 4, wherein the start address and the end address of the transmission / reception buffer area can be set to arbitrary values by the external functional unit. The transmission / reception buffer access means includes a pointer that indicates a reading position of transmission data from the transmission / reception buffer or a writing position of reception data to the transmission / reception buffer,
6. The serial data transmitting / receiving apparatus according to claim 4, wherein the value of the pointer is incremented every time data is transmitted or received, and is reset to the start address when the pointer value matches the end address.

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