JPH1198200A - Start-stop synchronization type serial data transmission and reception method, transmitter, receiver and transmitter-receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a transfer error with higher precision than that of a conventional parity check by taking synchronization on the way of serial data and avoiding a transfer error caused by out of synchronism due to a clock error between transmission and reception. SOLUTION: At a transmitter side, a modulation circuit 32 modulates 1-bit data into 2-bit data consisting of different logical values to convert a parallel input signal 104 of 1-byte length into transfer data 201 of 2-byte length and serial data are sent via a transmission buffer 33 and a shift register 24. At a receiver side, a changed point of a logical value of 2-bit to be modulated is detected and a reception clock signal 211 in synchronism with bit data is generated to receive data, then a transferred error is avoided. An error detection circuit 38 uses it that exclusive OR of the modulated 2-bit data is '1' to attain detection of the transferred error with high precision.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous serial data transmission / reception method, a transmission device, a reception device, and a transmission / reception device.

[0002]

2. Description of the Related Art A conventional start-stop synchronous serial data transmission / reception method will be described with reference to FIG. FIG. 5 is a timing chart of start-stop synchronous serial data. The start-stop synchronization method is a method in which a transmitting side and a receiving side synchronize by dividing a data signal at the same timing regardless of a clock. As shown in FIG. 5, for example, a start bit 11, a stop bit 12 and a parity bit 13 for dividing a data signal are added to 8-bit data portions d0 to d7 and transferred. In the state 14 where transmission has not started yet, "1" is transmitted. When transmitting, 1-bit "0" called a start bit 11, which is a data transmission start signal, is transmitted first. Subsequently, an 8-bit data portion d0 to d7 is transmitted from the lower bit, and then a parity bit 13 is transmitted. After that, as the stop bit 12 which is a data end signal, one or two bits "1"
Is sent.

On the receiving side, the start bit 11 is set to "0"
Is detected, and the subsequent data is received with a certain timing. The next reception is prepared by detecting "1" of the stop bit 12. In FIG. 5, small arrows arranged in parallel to indicate each bit indicate the reception timing by the reception clock.

FIG. 6 is a block diagram showing a configuration of a conventional start-stop synchronous serial data transmitting / receiving apparatus. This conventional start-stop synchronous serial data transmission / reception device, as a transmission unit,
A transmission control unit 21, a transmission buffer 22, a frequency dividing circuit 23, and a transmission shift register 24 are provided.
A reception control unit 25, a reception clock generation circuit 26, a reception shift register 27, and a reception buffer 28 are provided.

The transmission control section 21 receives a latch signal 102 and an operation start signal 10 from an external transmission control signal 101.
3 is generated. The transmission buffer 22 transfers the parallel input signal 104 input from the outside for transmission to the transmission shift register 24 by the latch signal 102 from the transmission control unit 21. The frequency dividing circuit 23 outputs the operation clock 10
5 to generate a transmission clock 106 and transfer it to the transmission shift register 24. The transmission shift register 24 receives the parallel input signal 104 transferred from the transmission buffer 22.
Is transmitted as a serial output signal 107 with a start bit 11, a parity bit 13 and a stop bit 12 added by the transmission clock 106 and the operation start signal 103 from the transmission control unit 21. When the transmission of the serial output signal 107 is completed, the transmission completion signal 10
8 to the transmission control unit 21.

The reception control unit 25 receives a latch signal 110 and a reception enable signal 1 from an external reception control signal 109.
11 is generated. The reception clock generation circuit 26 generates a reception clock 113 by synchronizing the operation clock 105 with the start bit 11 of the serial input signal 112. The reception shift register 27 receives the reception clock signal 11 from the reception enable signal 111 from the reception control unit 25.
3, the serial input signal 112 is divided into a data part 114 and a parity bit 13. When the reception is completed, a reception completion signal 115 is transferred to the reception control unit 25.
The reception buffer 28 outputs the data section 114 from the reception shift register 27 to the outside as a parallel output signal 116 in accordance with the latch signal 110 from the reception control section 25.

[0007] Further, how to synchronize the serial input signal 112 in the reception clock generation circuit 26 will be described with reference to FIG. FIG. 7 is a timing chart showing a method for achieving synchronization using the start bit 11 and the operation clock 105. Transfer rate of serial input signal 112 (1
(Time per bit) is determined in advance at the same transfer rate as the transmitting side. 16 of the clock of the serial input signal 112
The serial input signal 112 is sampled by the operation clock 105 having a double frequency, and the start clock 11 is detected.
A clock having a cycle 16 times as large as 5 is generated and used as a reception clock 113. Hereinafter, when the serial input signal 112 is sampled for each edge of the reception clock 113, serial input data can be captured. The operation clock 105 includes eight times the serial input signal 112,
In some cases, a clock having a frequency of twice or 64 times is used.

[0008]

However, in the above-mentioned conventional configuration, there is always an error in the speed of the clock of the serial input signal 112 and the speed of the reception clock 113. When the error is large, only the start bit 11 of the serial input signal 112 is used. However, there is a problem that the synchronization is lost in the middle of the serial data even when the synchronization is performed, resulting in a transfer error.

In addition, the error detection using the parity bit 13 has a problem that if there is a 2-bit transfer error at the same time, it is not detected as an error. The present invention provides a start-stop synchronous serial data transmission / reception method, a transmission device, a reception device, and a transmission / reception device that enable synchronization in the middle of serial data and can avoid a transfer error caused by loss of synchronization due to a clock error between transmission and reception. The purpose is to:

A further object of the present invention is to provide a start-stop synchronous serial data transmission / reception method, a reception apparatus and a transmission / reception apparatus capable of detecting a transfer error with higher accuracy than the conventional parity check.

[0011]

According to a first aspect of the present invention, there is provided an asynchronous start / stop serial data transmission / reception method for transmitting / receiving serial data with a data portion interposed between a start bit and a stop bit. A transmission / reception method, in which a transmission side modulates 1-bit data into 2-bit data having different logical values to convert n-bit parallel data (n is a predetermined integer) into 2 bits.
Transfer data having an n-bit length is divided into n-bit length units, and two serial data pairs are transmitted with each of the divided data portions. On the receiving side, two serial data pairs are transmitted. When receiving serial data, reception is performed in synchronization with the bit data by detecting a change point of a logical value of 2-bit data having different logical values of the received serial data, and receiving the data portion of the received serial data. Is characterized by demodulating 2-bit data having different logical values into 1-bit data.

According to this transmission / reception method, serial data is transmitted by modulating 1-bit data into 2-bit data having different logical values, and a change point of the logical value of the 2-bit data is detected on the receiving side. By doing so, reception synchronized with the bit data is performed, so that it is possible to avoid a transfer error caused by loss of synchronization in the middle of serial data due to a clock error between transmission and reception.

According to a second aspect of the present invention, there is provided the asynchronous serial data transmitting / receiving method according to the first aspect of the present invention, wherein the transmitting side converts the 1-bit data to 2-bit data having different logical values. Is characterized by using binary phase modulation, and demodulating 2-bit data having different logical values to 1-bit data on the receiving side by using binary phase demodulation.

As described above, by using binary phase modulation and demodulation, it is possible to easily modulate 1-bit data into 2-bit data having different logical values and vice versa. According to a third aspect of the present invention, there is provided an asynchronous serial data transmission / reception method.
In the start-stop synchronous serial data transmission / reception method described above,
On the receiving side, the exclusive OR of each 2-bit data is obtained for all 2-bit data having different logical values of the received serial data, and all the values of the exclusive OR of each 2-bit data are calculated. When it is 1, it is determined that there is no transfer error, and in other cases, it is determined that there is a transfer error.

This makes it possible to detect a transfer error with higher precision than the conventional parity check. A start-stop synchronous serial data receiving apparatus according to claim 4, wherein the start-stop synchronous serial data transmission / reception apparatus performs transmission of serial data with a data portion interposed between a start bit and a stop bit, and divides a basic clock. And a frequency dividing circuit for generating a transmission clock, and modulating 1-bit data into 2-bit data having different logical values to convert n-bit (n is a predetermined integer) parallel data of 2n-bit length. A modulation circuit that outputs the transfer data, a 2n-bit length transfer data output by the modulation circuit, a transmission buffer that divides the transfer data into n-bit length units, and outputs the data; A pair of serial data is transmitted using the transmission clock of the frequency dividing circuit, with each of the transmission data divided in bit length units being a data portion. Characterized in that a transmission shift register for.

According to this transmitting apparatus, by transmitting serial data obtained by modulating 1-bit data into 2-bit data having different logical values, the receiving side changes the logical value of the 2-bit data. Can be detected and reception synchronized with the bit data can be performed, and it is possible to avoid a transfer error caused by loss of synchronization in the middle of serial data due to a clock error between transmission and reception.

According to a fifth aspect of the present invention, there is provided a start-stop synchronous serial data transmission / reception apparatus for receiving serial data having a data portion interposed between a start bit and a stop bit. Length (n
Is a predetermined integer) by modulating 1-bit data into 2-bit data having different logical values to obtain 2n-bit length data. This data is divided into n-bit length units. Two pairs of serial data, each transmitted as a data portion, are received, and a change point of a logical value of 2-bit data composed of different logical values of the serial data is detected, thereby receiving data synchronized with the bit data. A receiving clock generating circuit for generating a clock, a receiving shift register for receiving a pair of serial data using the receiving clock of the receiving clock generating circuit and extracting a data portion, and forming a pair with the receiving shift register 2 extracted from two serial data
A reception buffer for storing a data portion of n-bit length, and a data portion of 2n-bit length stored in the reception buffer is demodulated so that 2-bit data having different logical values is converted into 1-bit data. And a demodulating circuit that performs the demodulation.

According to this receiving apparatus, detecting the change point of the logical value of 2-bit data of serial data transmitted by modulating 1-bit data into 2-bit data having different logical values. Therefore, a reception clock synchronized with the bit data is generated and reception is performed, so that a transfer error caused by a loss of synchronization in the middle of serial data due to a clock error between transmission and reception can be avoided.

According to a sixth aspect of the present invention, there is provided the start-stop synchronous serial data receiving apparatus according to the fifth aspect, wherein 2n stored in the reception buffer.
The exclusive OR of each 2-bit data is obtained for all 2-bit data having different logical values in the data portion corresponding to the bit length, and all values of the exclusive OR of each 2-bit data are 1 In some cases, it is determined that there is no transfer error,
In other cases, an error detection circuit for determining that there is a transfer error is provided.

This error detection circuit makes it possible to detect a transfer error with higher accuracy than the conventional parity check. The start-stop synchronous serial data transmitting / receiving device according to claim 7, comprising a start-stop synchronous serial data transmitting / receiving device including a serial data transmitting unit and a receiving unit sandwiching a data portion between a start bit and a stop bit, The transmission unit has an n-bit length (where n is a predetermined integer) by dividing a basic clock to generate a transmission clock and modulating 1-bit data into 2-bit data having different logical values. ), A modulation circuit that outputs the parallel data as 2n-bit length transfer data, and a transmission buffer that stores the 2n-bit length transfer data output by the modulation circuit, and divides the transfer data into n-bit length units for output. And dividing the pair of serial data, each of which is a data portion, of transfer data divided into n-bit units output by the transmission buffer. A transmission shift register for transmitting using a transmission clock of the channel, and the receiving unit modulates the 1-bit data into 1-bit data into 2-bit data having different logical values, thereby obtaining 2n-bit data. The data is divided into n-bit length units, each of which receives two pairs of serial data transmitted as a data part, and receives two bits of different logical values of the serial data. A reception clock generation circuit that generates a reception clock synchronized with the bit data by detecting a change point of the logical value of the data, and receives a pair of serial data using the reception clock of the reception clock generation circuit. Shift register for extracting the data section by using the serial data paired by the shift register for reception. A reception buffer for storing a data portion of a length of 2n bits, and a data portion of a length of 2n bits stored in the reception buffer is demodulated so that 2-bit data having different logical values is converted into 1-bit data. And a demodulating circuit that performs the demodulation.

According to this transmitting / receiving apparatus, the transmitting unit transmits serial data obtained by modulating 1-bit data into 2-bit data having different logical values, so that the receiving side transmits 2-bit data. It is possible to detect a change point of the logical value and perform reception synchronized with the bit data, and it is possible to avoid a transfer error that is lost in the middle of serial data due to a clock error between transmission and reception. Further, the receiving unit modulates 1-bit data into 2-bit data having different logical values and detects a changing point of the logical value of the transmitted 2-bit data of the serial data to convert the data into bit data. Since a synchronized reception clock is generated and reception is performed, it is possible to avoid a transfer error caused by loss of synchronization in the middle of serial data due to a clock error between transmission and reception.

According to an eighth aspect of the present invention, there is provided the start-stop synchronous serial data transmitting / receiving apparatus according to the seventh aspect of the present invention, wherein the receiving section includes a data section corresponding to the 2n-bit length data section stored in the receiving buffer. The exclusive OR of each 2-bit data is calculated for all 2-bit data having different logical values. If all values of the exclusive OR of each 2-bit data are 1, a transfer error is generated. An error detection circuit is provided which determines that there is no transfer error, and otherwise determines that there is a transfer error.

This error detection circuit makes it possible to detect a transfer error with higher precision than the conventional parity check.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a start-stop synchronous serial data transmission / reception device according to an embodiment of the present invention. In FIG. 1, reference numeral 31 denotes a transmission control unit;
2 is a modulation circuit, 33 is a transmission buffer, 34 is a reception control unit, 35 is a reception clock generation circuit, 36 is a reception buffer, 37 is a demodulation circuit, and 38 is an error detection circuit. In FIG. 1, a frequency dividing circuit 23, a transmission shift register 24,
The receiving shift register 27 has the same configuration as that of the conventional example.

The operation of the start-stop synchronous serial data transmitting / receiving apparatus according to the present embodiment will be briefly described. The modulation circuit 32 converts the 1-byte parallel input signal 104 input from the outside for transmission into the 2-byte transfer data 20.
The data is modulated to 1 and the transfer data 201 is transferred to the transmission buffer 33. The transmission control unit 31 receives a transmission control signal 202 from the outside and receives a latch signal 203 and an operation start signal 2.
04 is generated. From the transmission control unit 31 to the transmission buffer 33
, The latch signal 203 transferred twice is transferred twice per data of the transmission buffer 33 and one data (two bytes).
One byte of data 205 is transferred from the transmission buffer 33 to the transmission shift register 24 for each latch signal. In the transmission shift register 24, a serial bit having a start bit 11, a parity bit 13, and a stop bit 12 (see FIG. 5) added by the transmission clock 106 generated by the frequency dividing circuit 23 and the operation start signal 204 from the transmission control unit 31. The output signal 206 is transmitted. When the transmission of the serial output signal 206 is completed, the transmission completion signal 108 is transferred from the transmission shift register 24 to the transmission control unit 31.

The reception control section 34 generates a reception enable signal 208 and a latch signal 209 from an external reception control signal 207. As in the case of the reception clock generation circuit 26 of FIG. 6, the reception clock generation circuit 35 includes an operation clock (basic clock) 105 and the received serial input signal 2.
The receiving clock 211 is generated by synchronizing with the start bit 11 of ten, and the receiving clock 211 is generated by synchronizing even during the data of the serial input signal 210. The reception shift register 27 receives the reception enable signal 208 from the reception control unit 34 and divides the serial input signal 210 into a data part 212 and parity bits 13 using a reception clock 211. At that time, the reception completion signal 213 is transferred to the reception control unit 34. In the reception control unit 34, the reception completion signal 21
When 3 is transferred twice, the latch signal 209 is transferred to the reception buffer 36. The reception buffer 36 stores the data portion 212 from the reception shift register 27 for a 2-byte length, that is, stores the serial input signal 210 twice, and the 2-byte length data is demodulated by the latch signal 209 from the reception control portion 34. And to the error detection circuit 38. The demodulation circuit 37 demodulates 2-byte length data into 1-byte length original data, and outputs it as a parallel output signal 214 to the outside. The error detection circuit 38 performs error detection using the property that the data portion of the received serial input signal 210 becomes “1” when exclusive OR is performed for every two bits.

Hereinafter, the configuration and operation of the main part will be described in more detail. First, referring to FIG.
Operation 2 will be described in detail. Here, a case where binary phase modulation is used will be described as an example. FIG. 2A is a diagram illustrating how data is modulated by binary phase modulation, and FIG. 2B is a diagram illustrating examples of waveforms before and after binary phase modulation.

In the binary phase modulation, as shown in FIG. 2A, 1-bit data "0" is replaced with 2-bit data "0".
The 1-bit data "1" is modulated to "1" into 2-bit data "10", whereby the waveform in FIG. 2B becomes twice as long as the waveform in FIG. And
The modulated waveform A is always "0" every two bits.
A change point (arrow portion) of “1” or “1” → “0” exists. In the modulation example of FIG. 2B, 1-byte data “96” is modulated into 2-byte data “9665”. In the binary phase modulation, 1-bit data “0” may be modulated to “10” and “1” to “01”.

Here, the flow of data in the transmission section will be described with an example. For example, the one-byte parallel input signal 104 of “96” is modulated by the modulation circuit 32.
The data is modulated into 2-byte data 201 of “9669” and transferred to the transmission buffer 33. Transmission buffer 33
In this case, the 2-byte data is converted to the lower byte data “6”.
9 "and data" 96 "of the upper byte, and are transferred to the transmission shift register 24 one byte at a time from the lower byte by the twice latch signal 203 from the transmission control unit 31. The transmission shift register 1 transferred to 24
The byte-length data is added with a start bit 11, a parity bit 13, and a stop bit 12 (see FIG. 5), and is transferred twice as a serial output signal 206, respectively.

Next, the operation of the reception clock generation circuit 35 will be described with reference to FIGS. 5 and 2B. The data part of the received serial input signal 210 has been subjected to binary phase modulation, like the data part of the serial output signal 206. Therefore, for example, if one of the data portions d0 and d1 of the serial data in FIG. 5 is "1", the other is "0". Hereinafter, similarly, in the data portions d2 and d3, d4 and d5, and d6 and d7 (hereinafter, referred to as “pair bits”), if one is “1”, the other is “0”. Therefore, for example, as shown by an arrow A in FIG.
There is always a transition point where data is inverted, that is, an edge. By detecting this edge, synchronization can be easily achieved even in the middle of data. Therefore, the reception clock generation circuit 35
When generating 1, the synchronization is performed by the start bit of the serial input signal 210, and the synchronization is performed by the edge existing between each pair of bits in the data portion. It is not necessary to synchronize at all edges when synchronizing at the edge between the bits of the paired bits. However, as the number of synchronizing edges increases, the circuit becomes more complicated but the number of errors decreases.

Next, the operation of the error detection circuit 38 will be described with reference to FIG. As described above, if one of the data portions d0 and d1 of the serial data in FIG. 5 is "1", the other is "0". Therefore, if an EX-OR (exclusive OR) of the data parts d0 and d1 is taken, the value will always be 1. Using this, the error detection circuit 3
In step 8, EX-OR is performed for all pair bits, and if all of them are 1, it is determined that there is no transfer error. If any of the EX-OR is 0, it is determined that a transfer error has occurred. The error detection circuit 38 can be realized by a circuit as shown in FIG. 3, for example. That is, in the case of FIG. 3, the EX-OR circuit 3 that takes the EX-OR of each pair bit
9 to 42, and a NAND circuit 43 for negating the logical product of the output signals n0 to n3 of the EX-OR circuits 39 to 42. The output signal Y of the NAND circuit 43 is "0".
If it is, there is no transfer error, and if "1", it means that a transfer error has been detected.

Next, the operation of the demodulation circuit 37 will be described. The 2-bit data is demodulated into 1-bit data by a demodulation method corresponding to the modulation method shown in FIG. At this time, 2 received by the serial input signal 210 twice
The data having the byte length is demodulated together and converted into a 1-byte length, and is transferred to the outside as a parallel output signal 214. FIG. 4 is a diagram showing a method of demodulation by the demodulation circuit 37.
Assuming that the lower one byte of the 2-byte data received twice is d'0 to d'7 and the upper one byte is d "0 to d" 7, the signal of the upper bit of each pair bit is taken. The 8-bit signals d0 'to d7' become the demodulated parallel output signal 214.

As described above, according to the present embodiment, serial data obtained by modulating 1-bit data into 2-bit data having different logical values is transmitted,
Since the reception synchronized with the bit data is performed by detecting the change point of the logical value of the bit data, it is possible to avoid a transfer error caused by the loss of synchronization in the middle of the serial data due to a clock error between transmission and reception.

Further, by adding the error detection circuit 38, it is possible to detect a transfer error in units of bits, and it is possible to detect a transfer error with higher accuracy than in the conventional parity check. The output of the parity bit 13 from the register 27 is unnecessary. Therefore, if the error detection circuit 38 is provided on the receiving side, it is not necessary to insert the parity bit 13 into the serial input signal 210, that is, the serial output signal 206 on the transmitting side. If the error detection circuit 38 is not added, a conventional parity check may be performed using the parity bit 13 from the reception shift register 27.

In the present embodiment, the data portions of the serial output signal 206 and the serial input signal 210 are 8 bits.
Although described as bits, arbitrary bits of 5 to 8 bits may be used. Although the present embodiment has been described as a start-stop synchronous serial data transmission / reception device, it goes without saying that a start-stop synchronization serial data transmission device including only the transmission unit in FIG. 1 can be realized.
Needless to say, it is possible to realize a start-stop synchronous serial data receiving apparatus provided only with the receiving unit in the above.

[0036]

As described above, according to the present invention, serial data in which 1-bit data is modulated into 2-bit data having different logical values is transmitted, and the logical value of the 2-bit data is transmitted on the receiving side. Since the reception synchronized with the bit data is performed by detecting the change point of the data, it is possible to avoid a transfer error caused by the loss of synchronization in the middle of the serial data due to a clock error between transmission and reception.

Further, the exclusive OR of each 2-bit data is obtained for all 2-bit data having different logical values of the serial data received on the receiving side, and the exclusive-OR of each 2-bit data is obtained. When all the values are 1, it is determined that there is no transfer error, and in other cases, it is determined that there is a transfer error, so that a transfer error can be detected with higher accuracy than the conventional parity check. .

[Brief description of the drawings]

FIG. 1 is a block diagram of a start-stop synchronous serial data transmission / reception device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating binary phase modulation by a modulation circuit according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of an error detection circuit according to the embodiment of the present invention.

FIG. 4 is a diagram illustrating a demodulation method by a demodulation circuit according to the embodiment of the present invention.

FIG. 5 is a timing chart of start-stop synchronous serial data.

FIG. 6 is a block diagram of a conventional asynchronous serial data transmission / reception device.

FIG. 7 is a diagram showing how to synchronize a serial input signal in a conventional start-stop synchronous serial data transmission / reception device.

[Explanation of symbols]

 23 frequency dividing circuit 24 transmission shift register 27 reception shift register 31 transmission control unit 32 modulation circuit 33 transmission buffer 34 reception control unit 35 reception clock generation circuit 36 reception buffer 37 demodulation circuit 38 error detection circuit 104 parallel input signal 105 operation clock 106 transmission clock 201 modulated transfer data 202 transmission control signal 203 latch signal 204 operation start signal 205 transfer data 206 serial output signal 207 reception control signal 208 reception enable signal 209 latch signal 210 serial input signal 211 reception clock 212 data section 213 reception Completion signal 214 Parallel output signal

Claims (8)

[Claims] An asynchronous serial data transmission / reception method for transmitting and receiving serial data with a data portion interposed between a start bit and a stop bit. By modulating the data into 2-bit data consisting of values, parallel data having an n-bit length (n is a predetermined integer) is converted to transfer data having a 2n-bit length, and the transfer data is divided into n-bit length units. Is transmitted as the data portion. When receiving the two serial data forming the pair, the receiving side transmits two bits of the different logical values of the received serial data when receiving the two serial data. By detecting the change point of the logical value of the data, reception synchronized with the bit data is performed, and the data portion of the received serial data is Asynchronous serial data transmission and reception method characterized by demodulating the 2-bit data consisting of serial phase different logic one bit of data. 2. Modulation of 1-bit data to 2-bit data having different logical values on the transmitting side uses binary phase modulation, and 1-bit of 2-bit data having different logical values on the receiving side. 2. The asynchronous serial data transmission / reception method according to claim 1, wherein the demodulation to said data uses binary phase demodulation. 3. On the receiving side, exclusive OR of each 2-bit data is obtained for all 2-bit data having different logical values of the received serial data.
3. The method according to claim 1, wherein if all values of the exclusive OR of the bit data are 1, it is determined that there is no transfer error, and otherwise, it is determined that there is a transfer error. Asynchronous serial data transmission / reception method. 4. An asynchronous serial data transmitter for transmitting serial data with a data portion interposed between a start bit and a stop bit, wherein the frequency divider divides a basic clock to generate a transmission clock. A modulation circuit that modulates 1-bit data into 2-bit data having different logical values and outputs n-bit (n is a predetermined integer) parallel data as 2n-bit length transfer data; A transmission buffer that stores 2n-bit transfer data output from the modulation circuit and divides the transfer data into n-bit length units and outputs the transmission data; and a transmission buffer that divides the transfer data into n-bit length units and outputs the transmission buffer. A transmission shift register for transmitting two serial data pairs each having the data portion using a transmission clock of the frequency dividing circuit; Asynchronous serial data transmission apparatus characterized by comprising. 5. An asynchronous serial data receiver for receiving serial data with a data portion interposed between a start bit and a stop bit, wherein data having an n-bit length (n is a predetermined integer) is 1 The bit data is modulated into 2-bit data having different logical values to form 2n-bit data, which is divided into n-bit length units, and each is transmitted as the data portion. Receiving clock generation for receiving a pair of two serial data and detecting a change point of a logical value of 2-bit data having the different logical values of the serial data to generate a receiving clock synchronized with the bit data And receiving the pair of serial data using the reception clock of the reception clock generation circuit and extracting the data portion. A receiving shift register to be output, a receiving buffer storing a data portion of 2n bits extracted from the paired serial data by the receiving shift register, and the 2n bits stored in the receiving buffer. A demodulation circuit for demodulating the data portion of the minute data so that the 2-bit data having the different logical values is converted into 1-bit data. 6. An exclusive OR of each 2-bit data is obtained for all 2-bit data consisting of different logical values of a data portion of a 2n-bit length stored in a reception buffer, and the 2-bit data is calculated. If all the values of the exclusive OR of the data are 1, it is determined that there is no transfer error,
6. The start-stop synchronous serial data receiving device according to claim 5, further comprising an error detection circuit for determining that there is a transfer error in other cases. 7. An asynchronous serial data transmitter / receiver comprising a serial data transmitting unit and a receiving unit sandwiching a data portion between a start bit and a stop bit, wherein the transmitting unit divides a basic clock. A frequency dividing circuit for generating a transmission clock by dividing the data; and modulating 1-bit data into 2-bit data having different logical values to convert n-bit parallel data (n is a predetermined integer) into 2n-bit data. A transmission circuit that stores 2n-bit length transfer data output from the modulation circuit, divides the transfer data into n-bit length units, and outputs the data; and a transmission buffer that outputs the transmission data. Using the transmission clock of the frequency dividing circuit, two serial data pairs forming the data portion each of the transfer data divided into n-bit length units are used. And a transmitting shift register for transmitting provided, the receiving section 2 by the data of n bits length is modulated into 2-bit data consisting of different logic value 1-bit data
n-bit data, the data is divided into n-bit length units, each of which receives a pair of serial data transmitted as the data part, and receives the different logical values of the serial data. A reception clock generation circuit for generating a reception clock synchronized with the bit data by detecting a change point of the logical value of the 2-bit data comprising: a reception clock generation circuit; A reception shift register for receiving serial data and extracting the data portion; a reception buffer for storing a data portion of 2n bits extracted from the pair of serial data by the reception shift register; The 2n-bit data portion stored in the buffer is converted into a 2-bit data having different logical values. Asynchronous serial data transmission and receiving apparatus, characterized in that provided a demodulation circuit for demodulating the data such that the 1-bit data. 8. A receiving unit calculates an exclusive OR of each 2-bit data for all 2-bit data consisting of different logical values of a data portion of a 2n-bit length stored in a receiving buffer, An error detecting circuit is provided, which determines that there is no transfer error when all values of the exclusive OR of the two-bit data are 1, and that there is a transfer error in other cases. 7. The start-stop synchronous serial data transmission / reception device according to 7.