JPH07302255A - Semiconductor integrated circuit device, processor for emulating the same and emulator - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit device capable of performing data transfer by a lot of interruption and intrinsic processings for respective users and improving processing efficiency and to provide an emulator capable of improving the debugging efficiency of the semiconductor integrated circuit device further. CONSTITUTION:This device is a single-chip microcomputer and is constituted of the function blocks of CPUs 1 and 2, ROMs 1 and 2, RAMs 1 and 2, a RAMP, a timer, a pulse output circuit, an SCI, an A/D converter, an TOP 0-the TOP 11, an interruption controller, a bus controller and a clock oscillator. For the function blocks, the CPU 1, the ROM 1 and the RAM 1 are connected to an TAB 1 and an IDB 1, the CPU 2, the ROM 2 and the RAM 2 are connected to the IAB 2 and the IDB 2 and the RAMP is connected to a PAB and a PDB. Then, the CPU 1 and the CPU 2 are parallelly operable by the independent interfaces of the TAB 1, the TAB 2 and the PAB and the IDB 1, the IDB 2 and the PDB.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and for example, enables data transfer by a large number of interrupts in a single chip microcomputer and unique processing for each user, and improves processing efficiency. The present invention relates to a technology which is effective when applied to a semiconductor integrated circuit device capable of improving the debugging efficiency of the single-chip microcomputer, a processor for emulation thereof, and an emulator.

[0002]

2. Description of the Related Art For example, a single-chip microcomputer is a program centered on a central processing unit (CPU) as described in "LSI Handbook" P540 and P541 issued by Ohmsha, Ltd. on November 30, 1984. Functional blocks such as a holding ROM (read only memory), a data holding RAM (random access memory), and an input / output circuit for inputting / outputting data are formed on one semiconductor substrate.

In such a single chip microcomputer, a direct memory access controller (D
Incorporating MAC) and data transfer independent of the CPU, the "H" issued by Hitachi, Ltd. in March 1993
8/3003 hardware manual ”or Japanese Patent Application No. 4-137954. The DMAC can be activated by an interrupt request, can perform a repeat mode, a block transfer mode, and the like, and is suitable for controlling a stepping motor and print data of a printer. For example, a maximum of 8 channels can be transferred.

Further, since the DMAC transfer is independent of the CPU, only the number of cycles required for data transfer is controlled by the CPU.
The CPU can continue the process being executed. For example, in the case of transferring byte data and incrementing the transfer source / transfer destination address, in the above example, the data transfer is 6 states including the dead cycle 1 state.

[0005]

However, in the above-described DMAC, since each channel has a transfer source address, a transfer destination address, a transfer counter, and a control register, it is attempted to perform data transfer of many channels. If
It is necessary to provide a large number of the registers, and the DMAC's
As a result, the logical and physical scale of the entire semiconductor integrated circuit device is increased. Furthermore, the increase in scale increases the manufacturing cost. That is, it is difficult to transfer all or most of the interrupt factors.

On the other hand, such a register is arranged on a general-purpose RAM having a high storage density, so that a so-called data transfer controller (DTC), which is a data transfer device that prevents an increase in logical and physical scale, is built in. , Showa 63
December, "H8 / 532 Hardware Manual" published by Hitachi, Ltd., etc. In this DTC, data transfer can be performed by virtually all interrupt factors.

However, since the register holding the transfer information is arranged on the general-purpose RAM, this register is read into the DTC prior to the data transfer, the data transfer is performed according to the read contents, and the data is updated by the data transfer. It is necessary to save the register information in RAM. During this period the CPU must be stopped,
Compared with data transfer, a large amount of time is spent reading and saving registers.

Therefore, the processing efficiency of the single-chip microcomputer or the entire semiconductor integrated circuit device is reduced. For example, in the case of transferring byte data and incrementing the transfer source / transfer destination address, in the above example, 30 states are required to read / save registers from the data transfer 5 states, and the CPU is stopped for a total of 35 states. Will be done.

The control of the operation of the DMAC or DTC is specified by the content of the control bit of the control register, and only the transfer mode and the activation factor can be selected. If the number of control bits is increased, transfer data addition (checksum) and parity calculation can be performed, but it is difficult for each user to perform unique processing. Further, if various processes are to be realized, the logical and physical scale of the circuit that controls the processes will increase.

Naturally, the CPU can be used to perform the processing unique to each user associated with the data transfer. For example, when an interrupt occurs, the main processing is interrupted and desired processing is performed. However, the main processing to be performed by the CPU has to be interrupted, and the internal state of the CPU must be saved / restored, which causes overhead and improves the overall processing performance of the single-chip microcomputer. You will not be able to do it.

Therefore, an object of the present invention is to enable data transfer by a large number of interrupts and unique processing for each user,
Another object of the present invention is to provide a single-chip microcomputer or semiconductor integrated circuit device capable of improving processing efficiency.

Further, the present invention provides a processor and an emulator for emulation of a semiconductor integrated circuit device which can improve the debugging efficiency of this single chip microcomputer.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0014]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the semiconductor integrated circuit device of the present invention is provided with the second data processing device, and the first bus used by the first data processing device and the second bus used by the second data processing device. Of the first data processing device and the bus of the second data processing device can be used at the same time, and the operation of each of the first data processing device and the second data processing device can be separated. A first readable and connectable functional block or module required for each by a respective first or second bus, in particular a program capable of being executed by the first data processing device and the second data processing device. A storage means and a second readable storage means are provided, and the first data processing device is a first readable storage device and the second data processing device is a second readable storage device. It is obtained so as to operate by reading the program from.

Further, the first and second data processing devices and a readable storage means common to them are connected to each other by a bus, and the first data processing device is larger than an instruction executable in a unit time. A second data processing that minimizes a reduction in instruction execution speed of the first data processing device without reading the storage means using the bus and reading the storage means continuously using the bus. The device reads out the command from the storage means.

In this case, among the interrupt factors, the first factor makes it possible to request the first data processing device and the second factor makes it possible to request the second data processing device. The address space of the processing device may include the address space of the second data processing device, and the input / output means is readable / writable by the first data processing device and the second data processing device. A function of arbitrating the operation of the data processing device is provided.

The emulation processor for evaluating the semiconductor integrated circuit device is provided with a signal indicating which data processing device uses the bus on which the first and second data processing devices operate exclusively. For outputting the first and second data processing devices to stop the first and second data processing devices.
It has a break interrupt input terminal.

Further, the emulator equipped with this processor stores the operation information of the first and second data processing devices in the storage means at the same time, or selectively stores the operation information of one of the data processing devices in the storage means. Whether to perform the break interruption based on the designation from the system development device, or independently to the condition for requesting the break interrupt to the first and second data processing devices based on the designation from the system development device. It has a means for setting.

[0020]

According to the above-described semiconductor integrated circuit device, the instructions stored in the two readable storage means independent from each other can be read by the buses arranged in parallel in the two data processing devices, or the width of the bus can be expanded to read the data. Allow the processor to read more instructions than can be executed in a unit time,
By incorporating a function for supplying an instruction capable of operating two data processing devices side by side, a plurality of storage means can be selected at the same time, and by simultaneously writing or reading the plurality of storage means, an interrupt is generated. It is possible to eliminate the restriction on the number of channels for data processing and to set the content of data processing arbitrarily.

Further, since the first and second data processing devices operate simultaneously, the processing speed of the single chip microcomputer or the semiconductor integrated circuit device can be improved.

Further, an emulation processor,
Also, according to the emulator equipped with the same, the first data processor can be stopped by the first break interrupt, and the second data processor can be stopped by the second break interrupt. By having an interrupt that independently stops the data processing device, debug efficiency can be improved.

[0023]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a single-chip microcomputer which is an embodiment of the present invention, FIG. 2 is an explanatory view of an entire address map in the single-chip microcomputer of this embodiment, and FIG. Is a block diagram of a bus connection state of a single-chip microcomputer, FIG. 4 is a schematic block diagram of an interrupt controller, FIG. 5 is a schematic block diagram of an interrupt request bit and an interrupt permission circuit, and FIG. 6 is an operation timing diagram of the bus. 7, FIG. 7 is a schematic block diagram of a low power consumption state control circuit, FIG. 8 is an explanatory diagram of a register configuration for controlling input / output ports, FIG. 9 is a schematic block diagram of input / output ports, FIG. 10 is a PROM address map, and FIG. 11 is a block diagram of the main part of the PROM mode,
12 is a block diagram of the main part of the test mode, FIG. 13 is a schematic block diagram of the emulation processor, and FIG.
4 is a schematic block diagram of the emulator, and FIG. 15 is a block diagram showing a modification of the single-chip microcomputer in this embodiment.

First, the configuration of the single-chip microcomputer of this embodiment will be described with reference to FIG.

The single-chip microcomputer of this embodiment includes a central processing unit (CPU1: first data processing device, CPU2: second data processing device), read-only memory (ROM1: first readable storage means). ,
ROM2: second readable storage means), random access memory (RAM1, RAM2, RAMP), timer, pulse output circuit, serial communication interface (SCI), A / D converter (A / D), input / output port (IOP0 to IOP11: data input / output means), an interrupt controller (interrupt control means), a bus controller (bus control means), and a functional block (or module) of a clock oscillator, which are formed on one semiconductor substrate. ing.

These functional blocks are connected to each other by an internal bus. The internal bus includes a read signal and a write signal in addition to the address bus and the data bus, and may further include a bus size signal or a system clock.
This internal address bus includes IAB1 (first bus),
There are IAB2 (second bus) and PAB (third bus), and IDB1 (first bus) as the internal data bus,
There are IDB2 (second bus) and PDB (third bus). This internal data bus IDB1, IDB2, PDB
Has a 16-bit configuration. The instructions of CPU1 and CPU2 are in 16-bit units.

The CPU 1, ROM 1 and RAM 1 are I
Connected to AB1 and IDB1, CPU2, ROM2, R
AM2 is different in that it is connected to IAB2 and IDB2. RAMP is connected to PAB and PDB. These IAB1, IAB2 and PAB are interfaced by a bus controller, and similarly, IDB1, IDB2,
The PDB is interfaced with the bus controller.

PAB and PDB are bus controller, RAMP, timer, pulse output circuit, SCI, A /
It is connected to the D converter, the interrupt controller, and IOPs 0-11. One of CPU1 and CPU2 is PAB, P
These can be read / written using the DB. The interrupt controller inputs an interrupt signal output from a timer, SCI and an input / output port, and outputs an interrupt request signal and a vector number to the CPU1 or CPU2.

The input / output port is also used as an external bus signal and an input / output signal of the input / output circuit. IOP0-3 are address bus outputs, IOP4, 5 are data bus input / output, IOP
OP6 is also used as a bus control signal input / output signal. The external address and external data are transferred to the IAB1 and IDB via buffer circuits included in these input / output ports.
It is connected to 1. PAB and PDB are used to read / write the register of the input / output port and have no direct relation with the external bus.

The bus control signal output includes address strobes, high / low data strobes, read strobes, write strobes, bus acknowledge signals, and the like, and bus control input signals include wait signals, bus request signals, and the like. These input / output signals are not shown. Expansion of the external bus is selected depending on the operation mode, and the functions of these input / output ports are also selected.

IOP7 is a timer input / output, IOP8
Is also a pulse output, IOP9 is an SCI input / output, IOP10 is an analog input, and IOP11 is also used as an external interrupt request (IRQ) input. Input / output signals of the timer, SCI, A / D converter and IOP7, IOP9, IOP10 are not shown.

In addition, power supply terminals Vcc and Vss, analog power supply terminals AVcc and AVss, reset input RE
S, standby input STBY, interrupt input NMI, clock inputs EXTAL, XTAL, operation mode input MD0,
There are input terminals such as MD1 and MD2.

The pulse output circuit has a register (ND) (not shown) according to a trigger signal given from a timer.
The content held in R) is output from the terminal which is also used as IOP8.

Next, the address map of the single-chip microcomputer will be described with reference to FIG.

For example, CPU1 has an address space of 4 Gbytes, and CPU2 has an address space of 64 kbytes. The ROM1 and RAM1 exist only in the address space of the CPU1, and the ROM2 and RAM2 exist only in the address space of the CPU2. RAMP indicated by shaded areas, timer, pulse output circuit, SCI, A / D converter,
The addresses of the IOPs 0 to 11 and the functional blocks of the interrupt controller, that is, the internal registers have a unique logical address in the address space of each CPU for one physical address.

The addresses are associated with each other. Specifically, the address obtained by adding H'FFFF to the upper address of the CPU 2 becomes the address of the CPU 1. For example, the start address of RAMP is CPU
H'FFFFFB80 for 1 and H'FB8 for CPU2
It is 0.

That is, the CPU 1 is a ROM 1 and a RAM
1, RAMP, internal register can be read / written, C
PU2 can read / write ROM2, RAM2, RAMP, and an internal register.

Next, referring to FIG. 3, the connection state of the address bus and the data bus of this single chip microcomputer will be described.

In FIG. 3, the I / O is the timer of FIG.
Pulse output circuit, SCI, A / D converter, IOP0 to 1
1. Includes each functional block of the interrupt controller. The clock oscillator is omitted because it is not connected to the bus.

CPU as an address bus and a data bus
1, ROM1, RAM1, IAB1 for connecting the outside, and IAB2 for connecting CPU2, ROM2, RAM2,
There is also a PAB that connects RAMP and I / O. Such address bus and data bus are interfaced by a bus controller (BSC).

For example, when the CPU 1 reads a program from the ROM 1 or reads / writes data from / to the RAM 1, the operation is performed using the IAB1 and IDB1. This CPU 1 does not use PAB or PDB.

On the other hand, when the CPU 2 reads a program from the ROM 2 or when reading / writing data from / to the RAM 2, the operation is performed using the IAB2 and IDB2. This CPU 2 does not use PAB or PDB. At this time, the CPU 1 and the CPU 2 operate using buses independent of each other and can operate in parallel.

When either the CPU 1 or the CPU 2 reads / writes data from / to the RAMP or I / O, bus arbitration is performed. In this case, CP
The bus right request by U2 has priority over the bus right request by CPU1. This bus arbitration is performed by the bus controller in accordance with the address indicated by IAB1 / IAB2 and the command signal output from CPU1 / 2. The command signal includes a read request, a write request, a size signal, and the like.

When one tries to read / write data with RAMP or I / O while the other reads / writes data with RAMP or I / O, the latter will wait until the former read / write is completed. A standby signal is given from the bus controller to put it in a standby state. For example,
CPU2 reads / reads data from RAMP or I / O
While writing, CPU1 is ROM1, RAM1
Can be read / written.

Further, the CPU1 and the CPU2 simultaneously read the R
When an attempt is made to read / write data from / to the AMP or I / O, one CPU is brought into a stopped state, but the program is not placed in the RAMP or I / O, so that the RAMP or I / O It is possible to reduce the frequency by limiting the read / write of data to and from only the data.

In this case, since the data is read / written based on the read instruction, the ratio of the number of times the instruction is read and the number of times the data is read / written does not exceed 1/2. Further, since the entire program is not constructed by the data read / write command, the ratio can be further reduced. It is generally considered to be about 1/4 to 1/5. The program described in this example shows the same. Therefore, CP
The parallel operability of U1 and CPU2 can be improved.

In order to effectively use such parallel operation, the CPU 1 sets the overall settings and the ROM 1 and RAM 1
Alternatively, main program processing using an external device may be performed, and the CPU 2 may sequentially control I / O. In addition, the instructions of the CPU are stored in the ROM 1 or RO.
The work area may be arranged in M1 and the work area may be arranged in RAM1 or RAM2.

Next, the interrupt controller will be described in detail with reference to FIG.

For example, there are two types of interrupt factors, an internal interrupt and an external interrupt, each having an interrupt factor flag.
The factor flags of this internal interrupt are timer, SCI, A / D
"1" when the input / output circuit of the converter is in the specified state
The external interrupt factor flag is set to "1" when the external interrupt input terminal reaches a predetermined level or when a predetermined signal change occurs. This interrupt factor flag is cleared to "0" by the write operation of CPU1 / 2.

The output of each bit of the interrupt factor flag is input to the interrupt permission circuit, and the content of the interrupt permission register, that is, the interrupt permission bit is further input to this interrupt permission circuit. This interrupt permission register is a register readable / writable by the CPU 1/2, and selects whether the corresponding interrupt is permitted or prohibited.

For example, if the interrupt factor flag is set to "1" and the interrupt enable bit is set to "1", an interrupt is requested. That is, the interrupt permission circuit is composed of a logical product circuit in which the corresponding interrupt factor flag and interrupt permission bit are input.

The output of the interrupt permission circuit is input to the CPU selection circuit, and the contents of the interrupt selection register IRQSEL are further input to the CPU selection circuit. This interrupt selection register is used by the CPU 1 or C when an interrupt is requested.
Select which of PU2 is allowed to interrupt.

For example, when the bit of the interrupt selection register is set to "1", the CPU 2 is requested to interrupt. When the bit of the interrupt selection register is cleared to "0", the interrupt of CPU1 is requested. That is, C
The PU selection circuit is composed of a logical product circuit of the corresponding interrupt signal and the interrupt selection bit, and a logical product circuit of the interrupt signal and the inverted signal of the interrupt selection bit. The output of the former AND circuit is the CPU2 interrupt request signal, and the output of the latter AND circuit is the CPU1 interrupt request signal.

As the output of the CPU selection circuit, the CPU1 interrupt request and the CPU2 interrupt request are independently input to the priority determination circuit, and the output of the priority register is further input to the priority determination circuit. This priority register sets, for example, two levels of priority for each group of interrupt factors.

In this case, the priority is determined for each CPU 1/2 interrupt request. As a result of this determination, the highest priority is selected, a vector number is generated, and each vector number of the CPU1 / 2 interrupt request is output.

This CPU1 / 2 interrupt request signal and vector number are input to the mask level determination circuit, and the interrupt mask bits of the corresponding CPU1 / 2 are also input to this mask level determination circuit. Where the requested interrupt is C
If it is below the PU interrupt mask level, it is suspended. Then, an interrupt request signal and a vector number are output to each of the CPUs 1/2. The CPU 1 has 2 mask bits, while the CPU 2 has 1 mask bit.

Furthermore, when the interrupt request signal for each CPU becomes active, this CPU starts interrupt exception handling at the end of the instruction being executed, and switches the branch destination address from the vector address corresponding to the vector number. It fetches and branches to the interrupt processing routine.

Such priority determination and interrupt mask level are known in the above-mentioned March 1993, "H8 / 3003 Hardware Manual" issued by Hitachi, Ltd. or Japanese Patent Application No. 4-137955. Therefore, detailed description will be omitted.

The vector number is constant regardless of which of the CPU 1 and the CPU 2 requests it. However, in accordance with the size of the address space, the vector address is set in 4-byte units in the CPU 1 and in 2-byte units in the CPU 2.

The non-maskable interrupt NMI is input from one terminal NMI, but two CPUs can be requested to interrupt at the same time. It has no corresponding interrupt enable bit. This NMI interrupt is used to forcibly stop the processing of the CPU when the single-chip microcomputer or the semiconductor integrated circuit is out of control due to the non-maskable characteristic. It is convenient to request both CPUs 2 for NMI interrupts. Compared to using at least two terminals, one terminal can be saved and can be effectively used as an input / output port.

Further, the interrupt factor flag has an interrupt request bit writable by the CPU 2. When the interrupt permission bit is set to "1", the CPU1 can be requested to interrupt. The interrupt request bit can be set to "1" by the CPU 2 and can be cleared to "0" by the CPU 1. When the CPU 1 clears to "0", it is necessary to read the state of "1" in advance and then write "0".

Next, in the interrupt controller, the interrupt request bit and the interrupt permission circuit will be described in detail with reference to FIG.

For example, two flip-flops FF
1 and FF2 are included. This FF1 constitutes an interrupt request bit, and the reset signal RESET is used as a clear signal CLR.
Is entered. Further, the set signal S includes an AND circuit AN
The output of D1 is input, the output of the AND circuit AND3A is input to the reset signal R, and the output Q is the AND circuit A.
In addition to being output as an interrupt request via ND4, it is input to the AND circuit AND2 and the output buffer.

A bus right signal of the CPU 2, a register write signal, and a predetermined bit of the internal data bus are input to the AND circuit AND1. The register read / register write signal is a signal generated by a logical product of a read signal / write signal and a signal indicating that the register is selected by decoding the address. For example,
The register write signal becomes active state "1" when the CPU 2 or CPU 1 writes to the address of the interrupt request bit.

FF2 controls the interrupt request bit,
The reset signal RESET is input as the clear signal CLR. The output of the AND circuit AND2 is input to the set signal S, and the AND circuit AND2 is input to the reset signal R.
3A output is input, output Q is AND circuit AND3A
Entered in.

The AND circuit AND2 outputs the output of FF1 to
The bus right signal of the CPU 1 and the register read signal are input.

The output of FF2, the inversion of a predetermined bit of the internal data bus, and the output of AND3B are input to the AND circuit AND3A. The bus right signal and the register write signal of the CPU 1 are input to the AND 3B.

The AND circuit AND4 outputs the output of FF1 to
An interrupt enable signal, which is an output of a predetermined bit of an interrupt enable register (not shown), is input, and the output is an interrupt request signal. No selection bit is provided, and C is always used.
PU1 should be requested to interrupt.

The output buffer receives the output of FF1 as data and the register read signal as a clock signal. This output is coupled to a predetermined bit on the internal data bus.

Therefore, when the CPU 2 writes "1" in the address of the interrupt request bit, the output of AND1 becomes "1" and FF1 is set to "1". As described above, when the predetermined bit of the interrupt permission register is set to "1", the CPU 1 is requested to interrupt.

Further, when the CPU 1 reads the address of the interrupt request bit in this state, the content of the interrupt request bit is output to the data bus via the output buffer, and the output of AND2 becomes "1". FF2 is "1"
Is set to.

Subsequently, when the CPU 1 writes "0" in the interrupt request bit, the output of the AND3A becomes "1" and the FF1 and FF2 are cleared to "0". Similarly, the CPU 1 has a writable interrupt request bit,
This interrupt permission bit can be written only by the CPU 2, and C
PU2 can be requested to interrupt.

In the so-called read modify write instruction, it is preferable not to release the bus between read and write. For example, the bit set instruction fetches the data at the specified address into the CPU in byte size,
One bit designated inside the U is set to "1" and data is written in byte size.

Between this read and write, PAB, PDB
Not be released to the other CPU. The signal for prohibiting the release of the bus can be included in the command signal output by the CPU 1/2 to the bus controller.

Next, an example of the operation timing of the internal bus will be described with reference to FIG.

The single-chip microcomputer of this embodiment operates, for example, in synchronization with the system clock φ, IAB1 / 2 is output in synchronization with φ # which is an inverted signal of φ, and ROM1 // of CPU1 / 2 2 and RA
Reading to M1 / 2 is performed in one state.

First, IAB1 / 2 outputs one state in synchronism with φ # and is not particularly limited, but ROM1
It is latched in // 2 and in RAM1 / 2 in synchronization with φ. Read data corresponding to this is output in synchronization with φ #, and is fetched by the CPU while φ # is active.
For example, the data corresponding to the address output to IAB1 / 2 in synchronization with φ # of T1 is taken in by CPU1 / 2 while φ # of T2 is active.

On the other hand, read / write for RAMP is performed in two states, and read / write for I / O is performed in three states. The IAB1 / 2 synchronized with φ # is synchronized with φ by the bus controller.

In this case, the program of CPU 1 is as follows. In addition, the notation method of the instruction is 7
Mon, same as CPU described in "H8 / 300 Series Programming Manual" issued by Hitachi, Ltd.

CMP. B #CODE, R0L BEQ N1 BTST # 0, @PORT BNE N2 For example, CMP, BEQ, and BNE instructions have a 2-byte length,
The TST instruction is 4 bytes long.

First, the CMP instruction is read from the address n. When the execution of this CMP instruction is started, the BEQ instruction is read from the address n + 2, and the immediate data CODE and the general-purpose register R0L are internally read.
Compare the contents of and reflect in the condition code.

Further, when execution of the BEQ instruction is started,
First, the BTST instruction is read from the address n + 4.
Next, the instruction is read from the branch destination address N1 and it is determined whether the comparison results match. If they do not match, the instruction at address N1 is ignored and the BTST instruction that has already been read is executed.

Then, the second word of the BTST instruction is read. When this BTST instruction is executed, PAB / PDB is used to read data in byte size from the I / O designated by the absolute address PORT. Next, the BNE instruction is prefetched from the address n + 6.

The program of the CPU 2 is as follows.

BCLR # RDRF, @ SSR For example, the BCLR instruction has a length of 4 bytes.

First, the BCLR instruction is read from the address m and the address m + 2. When the execution of this BCLR instruction is started, the I / O specified by the absolute address SSR is first
Read data from O in byte size using PAB / PDB.

Then, the next instruction is prefetched from the address m + 4, and the bit designated by the immediate data RDRF of the read data is internally cleared to "0". This data is written to the I / O specified by the absolute address SSR using PAB / PDB. The execution of the next instruction is started, and the next instruction is prefetched from the address m + 6.

At T1, the instruction is fetched from the ROM1 / 2 of the CPU1 / 2, and the address is output to the IAB1 / 2.

At T2, ROM1 / 2 to IDB1 / 2
The CPU 1/2 fetches the instruction code (the first word of the CMP instruction and the BCLR instruction) read out at 1, and the address of the next instruction fetch is output to IAB1 / 2.

At T3, ROM1 / 2 to IDB1 / 2
The CPU 1/2 fetches the instruction code (the second word of the BEQ instruction and the BCLR instruction) read to the CPU 1, and the CPU 1 fetches the address of the next instruction fetch as CP.
U2 outputs the address SSR to IAB1 / 2, respectively.

In this case, since only the CPU 2 uses the PAB / PDB, the use of the PAB / PDB by the CPU 2 is permitted. Here, since the SCI read requires three states, the CPU2 standby signal goes high.

At T4, the bus right signal goes low, indicating that the CPU 2 is using the PAB / PDB. IA
The contents of B2 are output to PAB, and the SCI register S
The contents of SR are read. This read data is obtained at T6.

In this case, the instruction code (first word of the BTST instruction) read from the ROM1 to the IDB1 is C
The CPU 1 outputs the branch destination address N1 to the IAB1 as the PU1 fetches it (the second word of the BTST instruction).

At T5, the CPU 1 fetches the instruction code read from the ROM 1 to the IDB 1, but this is not executed because the branch condition is not satisfied. BT that has already been fetched
The first word of the ST instruction becomes valid. In this case, CP
U1 sets the address of the next instruction fetch to IAB1
Output to.

At T6, the data read from the SCI register SSR is sent to the CPU2 via the PDB and IDB2.
Takes in. Further, the CPU2 standby signal goes low, and the address of the next instruction fetch is output to IAB2.

In this case, the CPU 1 sends the address PORT
Is output to IAB1 and the use of PAB / PDB of CPU2 is completed, the use of PAB / PDB of CPU1 is permitted. Here, since the PORT read requires three states, the CPU1 standby signal becomes high level.

At T7, the bus right signal goes high, indicating that the CPU 1 is using the PAB / PDB. IA
The content of B1 is output to PAB, and the content of the register PORT of the input / output port is read. This read data is obtained at T9.

In this case, the CPU1 standby signal goes low, the address of the next instruction fetch is output to IAB1, and the CPU2 outputs the address SSR to IAB2. Here, since the PAB / PDB is used by the CPU1, the operation of the CPU2 is suspended and the CPU2 standby signal becomes high level.

At T8, the CPU 2 outputs the data to be written to the address SSR to the IDB2.

At T9, the register POR of the input / output port
The CPU 1 fetches the data read from T via the PDB and IDB2. This CPU1 outputs the address of the next instruction fetch to IAB1. In this case, the CPU
The 1-wait signal goes low, and the address for the next instruction fetch is output to IAB1.

At T10, the CPU 1 fetches the instruction code (BNE instruction) read from the ROM 1 into the IDB 1. The address of the next instruction fetch is output to IAB1. In this case, the bus right signal goes low and C
Display the PAB / PDB usage of PU2. The contents of IAB2 are output to PAB, and the contents of IDB2 are written to the SCI register SSR.

The write operation is performed at T11 and T12.
In this case, the CPU2 standby signal goes low at T12, and the address of the next instruction fetch is output to IAB2. Further, the CPU 1 repeats the same operation as above.

The CPU 1 can be an external CPU, and the external CPU can read / write the common portion as a peripheral function. When the CPU 2 reads / writes the common portion, the wait signal is activated by the external CPU and the CPU is put on standby. At this time, the single-chip microcomputer outputs an interrupt signal to the external CPU.

Next, an example of a data transfer program is shown below. Here, it is assumed that the check data of the SCI received data is performed and the result is stored in the work address SUM arranged on the internal RAM 2. Further, it is assumed that the number of received data is stored in the work address SUM arranged on the built-in RAM 2.

In addition, a work address CNT for storing the number of transfers and a reception data register RDR for SCI,
The status register SSR and the interrupt selection register IRQSEL of the interrupt controller are used.

PUSH R0 (1) MOV. B @RDR, R0L (2) MOV. B @SUM, R0H (3) ADD. B R0L, R0H (4) MOV. B R0H, @SUM (5) MOV. B @CNT, R0H (6) DEC. B R0H (7) MOV. B R0H, @ CNT (8) BEQ L1 (9) BCLR #RDRF, @SSR (10) BRA L2 (11) L1: BNOT #RXI, @IRQSEL (12) L2: RTE (13) First received by CPU2 Completion interrupt RXI is requested and branches to the interrupt routine. First, the general-purpose register R0 is saved in the stack (1). Then, the contents of the SCI reception data register RDR are read into the lower 8 bits R0L of the general-purpose register R0 (2).

Further, the contents of the work address SUM arranged on the built-in RAM 2 are read into the upper 8 bits R0H of the general register R0 (3). Then, the contents of R0H and R0L are added (4). The result of this addition is the address SUM
Write to (5).

Further, the contents of the work address CNT arranged on the internal RAM 2 are read into the general-purpose register R0H (6). Then, the contents of R0H are decremented (-
Do 1) (7). This decrement result is the address CN
Write to T (8).

If the content is "0", the flow branches to L1 (9), and the bit corresponding to the reception completion interrupt RXI of the interrupt selection register IRQSEL is inverted (12). At this time, since the interrupt request flag RDRF is still set to "1", the CPU 1 is requested for the reception completion interrupt RXI. Then, the process returns from the interrupt routine (13).

If the content written to the address CNT is not "0" (9), the interrupt request flag RDR
Clear F to "0" (10). Then, after executing the branch instruction (11), the routine returns from the interrupt routine (1
3).

Further, the following program example can determine the address of multiprocessor reception. In this case, if the received address matches the own address as a result of the address determination, the request destination of the reception completion interrupt is changed to the CPU 1.

PUSH R0 (1) MOV. B @RDR, R0L (2) CMP. B # ID, R0L (3) BEQ L1 (4) BCLR #RDRF, @SSR (5) BRA L2 (6) L1: BNOT #RXI, @IRQSEL (7) L2: RTE (8) First received by CPU2 Completion interrupt RXI is requested and branches to the interrupt routine. First, the general-purpose register R0 is saved in the stack (1). Then, the contents of the SCI reception data register RDR are read into the lower 8 bits R0L of the general-purpose register R0 (2).

This content is compared with the own ID received by the multiprocessor (3). As a result, if they match,
It branches to L1 (4) and inverts the bit corresponding to the reception completion interrupt RXI of the interrupt selection register IRQSEL (7). At this time, since the interrupt request flag RDRF remains set to "1", the CPU 1 receives the reception completion interrupt RX.
I is required. Then, the process returns from the interrupt routine (8).

If the result of comparison with its own ID does not match (4), the interrupt request flag is cleared to "0" (5). Then, after executing the branch instruction (6), the routine returns from the interrupt routine (8).

In this case, a plurality of transfers can be performed with one interrupt. For example, a stepping motor can be driven and this acceleration / deceleration can be performed. Further, the data output from the port is updated for each compare match interrupt OCMI of the timer to drive the motor. Further, the contents of the compare register can be updated to change the data output cycle to accelerate / decelerate.

The contents of the work address UPDW arranged on the internal RAM 2 are used for displaying this state. When this bit 6 is cleared to "0", it is a constant speed operation, and when it is set to "1", it is acceleration or deceleration.
That is, when bit 7 is cleared to "0", deceleration is performed, and when it is set to "1", acceleration operation is performed. The initial value is set to "1" for both bits 6 and 7.

The next output pulse is stored in the next data register NDR of the pulse output circuit, and the pulse output cycle is set in the constant register OCR of the timer. When the timer counter matches the value of the constant register, a compare match signal (not shown) is generated,
The content of NDR is output from the terminal that also serves as IOP8.
At the same time, the value of the timer counter is cleared to 0. This N
DR is 4 bits.

Such a pulse output is the same as that in Japanese Patent Application No. 4-117969.

PUSH R0 (1) MOV. B @NDR, R0L (2) ROTL. B R0L (3) BLD # 4, R0L (4) BST # 0, R0L (5) MOV. BR0L, @ NDR (6) First, the CPU 2 is requested to execute the compare match interrupt OCMI, and the process branches to the interrupt routine. First, general-purpose register R
0 is saved in the stack (1). Then, the contents of the next data register NDR are read into the lower 8 bits R0L of the general-purpose register R0 (2).

The contents are rotated (3). Here, 4
In order to rotate in bit units, bit 4 after rotation is stored in the carry flag (4), and this carry flag is stored in bit 0 (5). The result of the completion of the rotation in units of 4 bits is written in NDR (6). This content is output from the pin at the next compare match.

BTST # 6, @UPDW (7) BEQ L3 (8) MOV. W @ OCR, R0 (9) BTST # 7, @UPDW (10) BNE L1 (11) SUB. W #CNST, R0 (12) BRA L2 (13) L1: ADD. W #CNST, R0 (14) L2: MOV. WR0, @ OCR (15) Then, the content of bit 6 of the address UPDW is checked (7). If this content is "0" (constant speed operation), L3
(8) and the content of the constant register OCR is retained. If not "0", the constant data register OC
The content of R is read into the general-purpose register R0 (9).

Further, the content of bit 7 of the address UPDW is inspected (10), and if this content is "0" (deceleration operation), branch to L1 (11), and if not "0" (acceleration operation). ), The constant value CNST is subtracted from the general-purpose register R0 (12), and the process branches to L2 (13). At this L1, the constant value CNST is added to the general-purpose register R0 (14), and L
In 3, the contents of the general register R0 are written in the constant register OCR (15).

L3: MOV. B @CNT, R0H (16) DEC. BR0H (17) BNE L5 (18) BTST # 6, @UPDW (19) BEQ L6 (20) BTST # 7, @UPDW (21) BEQ L4 (22) BCLR # 6, @UPDW (23) MOV # CNT1 , R0H (24) BRA L5 (25) L4: BSET # 6, @UPDW (26) BCLR # 7, @UPDW (27) MOV # CNT2, R0H (28) L5: MOV. BR0H, @ CNT (29) BRA L7 (30) L6: BNOT # OCMI, @ IRQSEL (31) L7: RTE (32) Then, the content of the address CNT is read into the general register R0H (16). The content of this content R0H is decremented (-1) (17). If this content is not "0", it branches to L5 (18), and if it is "0", the content of bit 6 of the address UPDW is checked (19).

Further, if the content is "0" (constant speed operation), the process branches to L6 (20), and if not "0", the content of bit 7 is checked (21). If "0" (deceleration operation), branch to L6 (22),
If it is not "0" (acceleration operation), bit 6 of the address UPDW is cleared to "0" and the operation shifts to the constant speed operation (2
3) The rotational speed CNT1 for low speed operation is set to R0H (24). Then, the process branches to L5 (25).

At L4, in order to transit to the deceleration operation, bit 6 of the address UPDW is set to "1" (26),
Bit 7 is cleared to "0" (27). Further, the rotation speed CNT2 of the deceleration operation is set to R0H (28).

Further, at L5, the contents of the general register R0H are written to the address CNT (29). And
After executing the branch instruction (30), it returns from the interrupt routine (32).

After the deceleration operation is completed, a compare match interrupt OC is stored in the interrupt selection register IRQSEL at L6.
The bit corresponding to MI is inverted (31). At this time,
Since the interrupt request flag OCMF is still set to "1", the CPU 1 is requested for the reception completion interrupt RXI. Then, the process returns from the interrupt routine (32).

Further, the activation may be performed by requesting an interrupt from the CPU 1 to the CPU 2 using the interrupt request register and arranging a command at a predetermined address on the RAMP, for example.

From the above, for example, Japanese Patent Application No. 4-1379.
Compared to the method described in Japanese Patent Application No. 54 or Japanese Patent Application No. 4-179169, there is no need to expand data in RAM, and R
The amount of AM used can be saved.

If the CPU 2 is mainly used for data processing corresponding to an interrupt, the CPU 2 does not always have a program to be processed. Therefore, if there is no program to be processed at the time when data processing by one interrupt is completed, it is preferable that the CPU 2 be in a low power consumption state, so-called sleep state.

In this sleep state, a dedicated SLEEP
A transition is made by executing an instruction. And CPU2
The clock supplied to is stopped. When the interrupt is requested, the sleep state is released.

Next, the low power consumption state control circuit will be described in detail with reference to FIG.

The low power consumption state control circuit is constructed in, for example, a clock oscillator, and the low power consumption state control circuit includes three flip-flops SLPF1, SLPF2,
It is controlled by SSBYF.

The flip-flop SLPF1 is the CPU1.
When the SLEEP instruction is executed, the set state is set. At this time, the CPU 1 enters the sleep state. Also, CPU
When an interrupt request for 1 is generated, the status is cleared.

The flip-flop SLPF2 is the CPU2.
When the SLEEP instruction is executed, the set state is set. At this time, the CPU 2 enters a sleep state. Also, CPU
When an interrupt request for 2 occurs, it goes into the clear state.

In the flip-flop SSBYF, one CPU is in the sleep state and the other CPU is in the S state when the control bit SSBY (not shown) is set to "1".
When the LEEP instruction is executed, the set state is set. In this software standby state, start the clock oscillator,
All functions stop working. The inside is reset.

However, as long as the specified voltage is applied, the contents of RAM1, RAM2 and RAMP are retained. Also, the state of the input / output port is retained. And
When an NMI interrupt request is generated, it goes into the clear state. In addition,
Since the inside is in the reset state, no interrupt request other than NMI is generated.

In order to shift to the software standby state, one CPU may set the SSBY bit to "1" and execute the SLEEP instruction. The other C
Depending on the state of the PU, it is automatically selected whether to immediately transit to the software standby state or to transit to the sleep state and then to the software standby state after the other CPU executes the SLEEP instruction. Therefore, when creating a program, it is not necessary to check the mutual operating states, and the efficiency of creating the program can be improved.

Further, when the interrupt processing is started, it is preferable to provide a bit indicating whether it was in operation or in a sleep state immediately before. If an interrupt is accepted during this operation, the contents of the internal register of the CPU must be saved. However, if the interrupt is accepted during sleep, the internal register of the CPU will not contain the data being processed. There is no need to evacuate. If the save operation and the return operation at the end of processing are not performed, the speed can be increased.

Further, the input / output port is the CPU
From writable or selectable.

Next, the registers of the input / output ports will be described in detail with reference to FIG.

The registers of this input / output port are the data direction register (DDR) and the data register (D
R) and a port control register (PSEL).

DDR is a write-only register,
It is an input when it is cleared to "0" and an output when it is set to "1".

DR stores output data. This DD
When R is set to "1", the contents of DR are output.
At the time of reading, the content of DR or the state of the terminal is read. That is, when DDR is cleared to "0", the state of the terminal, and when set to "1", DR
The contents of are read.

The PSEL selects which CPU controls each input / output terminal. The control bit of this port control register (PSEL) is the data register (DR).
And the bits of the data direction register (DDR) are commonly controlled. When PSEL is cleared to "0", writing is performed by CPU1, and when it is set to "1", writing is performed by CPU2.

When a pull-up MOS is built in the port or a dual output buffer is used, the registers for controlling these may be commonly controlled by PSEL. An example of such a register is the above-mentioned March 1993,
"H8 / 3003 Hardware Manual" issued by Hitachi, Ltd. P263-P306, P419-P445
It is described in.

Next, the input / output ports will be described in detail with reference to FIG.

In the input / output port of this embodiment, the data direction register (DDR), the data register (DR) and the port control register (PSEL) are composed of flip-flops. In both cases, a predetermined bit of the internal data bus is used as a data input (D) and a reset signal (R
ESET) is a clear input (CLR).

The DDR input clock (C) is the output of the AND circuit AND1. This output (Q) is used as a control signal for the output buffer OBUF and a selection signal for the selector SEL1.

The input clock (C) of DR is the output of the AND circuit AND2. This output (Q) is used as the data input of the output buffer OBUF and the data input of the selector 1.

The input clock (C) of PSEL is PSE
This is the L read signal WRPSEL. This output (Q) is used as a selection signal for the selector SEL2.

The output buffer OBUF has a DDR output as a control signal and a DR output as a data input, and the output signal is connected to the terminal P.

In the input buffer IBUF, the input signal is connected to the terminal P and the output signal is used as the data input of the selector SEL1.

The selector SEL1 uses the DDR output as a selection signal and the DR output and the input buffer IBUF output as data inputs. When the DDR output is "0", the input buffer IBUF output is selected, and when the DDR output is "1", the DR output is selected. The output of the selector SEL1 is input to the DR read buffer.

The selector SEL2 uses the PSEL output as a selection signal and the CPU1 / 2 bus right signal as a data input. This output becomes a write enable signal. When PSEL is "0", the CPU1 has the bus right and the CPU1 is in the write enable state. When PSEL is "1", the CPU2 bus is granted and C
PU2 is in the write enable state.

The DR read buffer DRBUF inputs the output of the selector SEL1 and uses the DR read signal RDDR as a clock, and the output signal is connected to a predetermined bit of the internal data bus. When this RDDR is active, the output of the selector SEL1 is output to the internal data bus.

PSEL read buffer PSBUF is P
The output of the SEL flip-flop is input, the PSEL read signal RDPSEL is used as a clock, and the output signal is connected to a predetermined bit of the internal data bus. This RDPSE
When L is active, it outputs the output of the PSEL flip-flop to the internal data bus.

The AND circuit AND1 receives the write enable signal and the DDR write signal WRDDR as its inputs, and outputs an output signal of D
It becomes the DR input clock.

The AND circuit AND2 receives the write enable signal and the DR write signal WRDR as input, and the output signal becomes the DR input clock.

The ROM1 and the ROM2 can be PROMs, and when the PROMs are programmed from the outside, it is preferable that the two ROMs have consecutive addresses from the outside.

Next, the address map of the PROM will be described with reference to FIG.

For example, PROM1 has 64 kbytes, P
ROM2 is 32 kbytes. In MCU mode, P
ROM1 is H'00000000-H'0000FFF
In F, the PROM 2 is arranged in H'0000 to H'7FFF.

In the PROM mode, PROM1 is set to H'0000 to H'0FFFF and PROM2 is set to H '.
It is arranged in 10000 to H'17FFF.

Next, the PROM mode will be described in detail with reference to FIG.

In this PROM mode, the mode terminal MD
It is set by setting all 1, MD0, and STBY terminals to low level. At this time, the internal signal EPM is activated (high level) by a mode setting circuit (not shown). In the PROM mode, the CPU1 / 2 are separated from the address bus and the data bus by BUFC1 / 2.

In FIG. 11, the CS controller, the buffer BUFC1 / 2, etc. are included in the bus controller.

The PROM is the ROM1 and the ROM2 in FIG. 1, and comprises a memory array, an address decoder, an input / output circuit, and a control circuit. An address is input to the address decoder, an input / output circuit inputs / outputs data, and a control circuit inputs a control signal to control the input / output circuit to write / read data. Further, the memory array is arranged with non-volatile storage elements.

The control circuit includes an EPM, CS-1 / 2 #,
OE #, PGM #, MS-1 / 2 #, and a read signal are input. When this EPM is active, PROM
Write / read operation as CS-1 / 2 #, O
It is performed based on E # and PGM #. When the EPM is inactive, RO in the CPU address space
The read operation as M is performed based on MS-1 / 2 # and the read signal.

In the PROM mode, VPP, CS #,
It is controlled by OE # and PGM #. Such control is performed, for example, in "HIT" issued by Hitachi, Ltd. in March 1993.
ACHI IC Memory Data Book
No. 2 (10th Edition) ”P510-P
This is the same as the PROM described in 524.

The VPP terminal is connected to the RES terminal, CS #, OE
# And PGM # are terminals P61, P62 and P63, addresses A0-15 are terminals P00-07 and P10-17, A
16 is a P60 terminal, and data D7-0 is P40-P47.
It is also used as a terminal. Although not shown, VPP is given to PROM1 / 2.

As internal signals, OE # and PGM # are input through the buffer circuit, and PROM1 and PROM2 are input.
Is supplied to. CS-1 # is an address upper signal A16
The logical product signal with the inversion signal of CS-2 #, CS-2 #, is generated with the inversion signal of the address upper signal A15 and the logical product signal with A16. These CS-1 # and CS-2 # are given to PROM1 and PROM2, respectively.

In the PROM mode, IDB1 and IDB
2 are connected via a buffer. Data in PROM2 is input / output via IDB2, IDB1 and IOP3. That is, when CS-2 # is in the active state and a read operation is performed, the content of IDB2 read from PROM2 is I
It is output to DB1. Furthermore, during a read operation, I
The contents of DB1 are output to the outside via IOP3.

In the write operation, the external contents are I
It is input to IDB1 via OP3. When CS-2 # is in the active state and the write operation is performed, the contents of IDB1 are IDB2.
Output to the PROM2. Furthermore, IDB
The content of 1 is output to the outside through IOP3.

In PROM mode, IAB1 and IAB
2 are connected via a buffer. That is, IOP
The address of IAB1 input via 1, 2 is IA
It is input to B2 and given to PROM2. In addition, PR
Since the maximum capacity of OM1 / 2 is 64 kbytes, the address given to each PROM is 16 bits.

For example, the read operation is CS-1 / 2
# And OE # are active and PGM # is inactive, and the write operation is performed when CS-1 / 2 # and PGM # are active and OE # is inactive.

Besides, verification and page writing can be performed, but since the present invention has no direct relation to them, detailed description thereof will be omitted.

In one PROM mode, PROM1, PROM
The ROM 2 can be externally written as one PROM at a time. As a result, writing can be performed efficiently.

Next, the test mode will be described in detail with reference to FIG.

In this test mode, the mode terminals MD1 and
It is set by setting both MD0 to low level and the STBY terminal to high level. At this time, the internal signal TM is activated (high level) by a mode setting circuit (not shown).

In FIG. 12, control circuit 1/2, bus arbitration circuit, selection circuit, buffer BSBUF, buffer B
UFC1 / 2 is included in the bus controller.

The bus right arbitration circuit selects which one of the CPU1 / 2 uses the PAB / PDB to select the control signal P.
Output AK. CP when this PAK is at high level
When U1 and PAK are low level, CPU2 is in PAB
/ Use PDB. In the test mode, the PAK signal is controlled by the selection signal given from the P62 terminal.

In the test mode, CPU1 / 2 are BU
It is separated from the address bus, the data bus, and the read signal / write signal by FC1 / 2.

Addresses are input from IOP3 to IOP0 to IAB1 via the buffer BUFP, and further to BS.
Input to IAB2 and PAB via BUF. It should be noted that IAB1 is 3 GB corresponding to the address space of 4 GB.
Although it has two addresses, IAB2 has 16 addresses corresponding to an address space of 64 kbytes, and PAB has RAMP and I.
It has 10 addresses corresponding to the / O addresses.
Therefore, it is preferable to use IAB1 to give an address from the outside.

The data bus is input / output to / from the IDB1 via the buffer BUFP by the IOP4. Lead /
The contents of the IDB2 or PDB are input / output to / from the IDB1 via the BSBUF according to the write operation and the address.

The read signal and the write signal are supplied to the P60 terminal,
It is input from the P61 terminal via BUFP. RD1 /
2, WR1 / 2, ROM1, RAM1 / ROM
2, supplied to RAM2. In addition, the bus right signal PAK selects RDP and WRP, and RAMP,
Supplied to I / O. In test mode, PAK
Regardless of the signal, RD1 / 2 / P always has the same operation, and WR1 / 2 / P always has the same operation.

The control circuit 1/2 selects the selection signals MSROM1 / 2 and MSRAM based on the address of IAB1 / 2.
1/2, MSRAMP, MSIO are output. MSRA
Since MP and MSIO are common signals, one is output and the other is high impedance based on the PAK signal. For example, when the PAK signal is at high level, the control circuit 1 outputs and the control circuit 2 has high impedance.

In the test mode, MSROM1
/ 2 and MSRAM1 / 2 are prohibited based on the PAK signal. This is so that one functional block can be selected based on the address given from the outside. For example, when the PAK signal is high level, MS
ROM1 and MSRAM1 are outputs based on IAB1, M
SROM2 and MSRAM2 are inactivated.

When testing the ROM1 / RAM1, read / write can be performed by applying an address and a read signal / write signal with the P62 terminal at a high level and the PAK signal at a high level. .

When testing the ROM2 / RAM2, read / write can be performed by applying an address and a read / write signal with the P62 terminal at a low level and the PAK signal at a low level. . Only the lower 16 bits of this address are valid.

Further, when testing the RAMP / I / O, the P62 terminal is set to the high level, the PAK signal is set to the high level, and the address and the read signal / write signal are applied to read / write. It can be carried out.

As described above, the address data for reading / writing the internal functional block from the outside can be supplied from the outside to the internal bus to which the address is given by the CPU and the input / output of the data should be performed.
The data required for this functional block can be directly read / written from the outside, facilitating the test of the functional block incorporated in this single-chip microcomputer and improving the testing efficiency.

When testing the built-in RAM, it is preferable to test the data independently and test the address decoder in parallel. To test this address decoder, RAM1 / 2 / P can be simultaneously selected so that the tests can be performed simultaneously.

In this case, the RAM test mode may be provided for FIG. P in the test mode
When the 63 terminal is set to low level, the same test mode as described above is set, and when the P63 terminal is set to high level, the RAM test mode is set.

In this RAM test mode, RAM1 /
2 / P selection signals MSRAM1, MSRAM2, MSR
The AMP can be activated at the same time. However,
The data to be read is bit 0 to 1 and bit 2 respectively
3 and bits 4 to 7.

CPU1 and CPU2 have substantially the same C
It may be PU or CPU1 may include CPU2 so that the software development environment can be shared. Japanese Patent Application No.
-There is 226447.

In the emulator for evaluating a single-chip microcomputer as described above, when a user externally sets a break condition, it is preferable to be able to specify which CPU the break is set to. Further, it is preferable to be able to specify that a break will occur when the conditions of the two CPUs are both satisfied.

Next, the configuration of the emulation processor will be described with reference to FIG.

The emulation processor is a CPU
1, a microcomputer part including a CPU 2, and an emulation processor dedicated block including a buffer circuit (not shown) and the like, which are formed on one semiconductor substrate by a known semiconductor manufacturing technique.

This emulation processor has a user interface for transmitting and receiving signals to and from the application system, and an emulation interface for transmitting and receiving signals to and from the microcomputer developing device.

As the emulation bus, IAB is used.
1 and IDB1, IAB2 and IDB2 are input / output through the emulation interface. Also, P
A bus right display signal indicating which CPU, AB or PDB, is being used is output. This is P in FIG.
It is assumed to correspond to the AK signal. Further, the bus right arbitration outputs a signal indicating that the CPU is in a standby state.

The access states of PAB and PDB are not explicitly displayed, but the bus right indication signal and IAB1 and IAB
It can be determined by the contents of the emulation bus by DB1, IAB2 and IDB2. This P
By not outputting the emulation bus by AB or PDB, the number of terminals of the emulation processor can be reduced, thereby reducing the package size and eventually the emulator size.

Break request terminals are BRK1 # and BRK.
Two of 2 # are included in the emulation interface. Based on this, the BRK1 and BRK2 signals request the break interrupt to the CPU1 and CPU2, respectively. These do not have a corresponding CPU selection bit, but go through a priority determination circuit and are parallel to the interrupt request signal.
The break request signal for is activated. The vector number signal is also used as a general interrupt request.

When the CPU1 and CPU2 accept the break interrupt, the break acknowledge signal BRK is received.
AK1 and BRKAK2 are activated. For example, C
When the PU 2 is performing the SCI reception processing and the pulse output processing as described above, even if the CPU 1 is stopped by the break interrupt, the CPU 2 interrupts the SCI reception in order to execute the user's processing. It is possible to prevent a so-called overrun error from occurring or the pulse output to be interrupted, which makes it impossible to drive the motor of the user system, for example.

Next, referring to FIG. 14, the configuration of the emulator equipped with the emulation processor will be described.

The connector section is attached to the application system (user system) instead of the single-chip microcomputer. The emulation processor inputs and outputs signals to and from the application system using the target system interface via the connector section and the interface cable.

The emulation processor is connected to the emulation bus 1/2 using the emulation interface. The emulation bus 1 corresponds to IAB1 / IDB1 and the emulation bus 2 corresponds to IAB2 / IDB2. These emulation buses include status signals, control signals, etc. not shown.

Using this emulation bus, the emulation processor outputs information according to the internal states of the application system and the emulation processor.
Various control signals for emulation are input.
Then, the emulation mode terminal (not shown) of the emulation processor is fixed to the power supply level,
The emulation mode is set inside the emulation processor.

The emulation bus is not particularly limited, but is an RA for substituting the memory built into the application system or the target microcomputer.
The control status of the emulation memory such as M and the emulation processor and the status of the emulation bus are monitored, and when the status reaches a preset status, the emulator dedicated interrupt is input and the user by the CPU A break control circuit for stopping the execution of the program and shifting to the emulation program execution state (break) is connected.

Further, this emulation bus has
Based on a signal indicating a read operation or a write operation of the CPU, a signal indicating an instruction read operation, or the like, a real-time trace circuit or the like for sequentially storing the address and data given to the emulation bus and further control information is connected. In this embodiment, the emulation bus 1/2
Are connected to the emulation memory, break control circuit, real-time trace circuit, etc., respectively.

Therefore, the emulation memory is IA
Data of B1 / IDB1 and IAB2 / IDB2 are independently input and output in parallel. Further, the break control circuit independently determines the address / data of IAB1 / IDB1 and IAB2 / IDB2 and other information. After the conditions on the IAB1 / IDB1 side are satisfied, IAB2 /
A break can be requested when the condition on the IDB2 side is satisfied. As mentioned above, the break interrupt is CP
Both U1 and CPU2 can be requested at the same time, or only one CPU can be requested.

The real-time trace circuit is IA
Address of B1 / IDB1 and IAB2 / IDB2 /
Data and other information are stored independently, and when one CPU breaks, only the address / data of the other CPU and other information are stored. Also, one CPU
It is also possible to selectively store only the address / data and other information.

The emulation memory, break control circuit, and real-time trace circuit are connected to the control bus and are controlled by the control processor via the control bus. This control bus is connected to the processor control circuit for emulation, and via the interface circuit,
Although not particularly limited, it is connected to a system development device such as a personal computer.

For example, when the program input from the system development apparatus is transferred to the emulation memory and the CPU reads this program to be arranged in the built-in ROM, the program in the emulation memory is read. Also, break conditions and real-time trace conditions can be given from the system development device.

As the break condition, at least
The conditions of CPU1 and CPU2 can be set independently. As the real-time trace condition, at least the addresses / data of the CPU1 and CPU2 and other information are accumulated at the same time, or one of the CPUs is selectively selected.
It is possible to select whether to store only the address / data of, and other information.

Therefore, according to the single-chip microcomputer of this embodiment, the CP as the data processing device is
U1, CPU2, bus controller as bus control means, ROM1, ROM as readable storage means
2. By making IOP0 to IOP11 as data input / output means a main structure, the following operational effects can be obtained.

(1). IAB connecting CPU1 and ROM1
1, IDB1, IAB connecting CPU2 and ROM2
2, the IDB2 is provided independently, and the program of the CPU1 is stored in the ROM1 and the program of the CPU2 is stored in the ROM2, so that the CPU1 and the CPU2 can operate in parallel, and the RAMP and the input / output circuit by the IOP0 to IOP11, Connected to a common PAB, PDB, C
By making PU1 and CPU2 available, C
Data to be controlled by PU1 and CPU2 can be arbitrarily distributed and used. As a result, the processing speed of the single chip microcomputer can be improved and the resource utilization efficiency can be improved.

(2). By performing two processes simultaneously by one single-chip microcomputer, it is possible to replace the conventional system using a plurality of semiconductor integrated circuit devices and realize miniaturization. .

(3). By allowing the CPU1 and the CPU2 to mutually request interrupts, the CP can be easily executed.
It is possible to realize mutual synchronization of U1 and U2.

(4). In the case where the operation of the CPU1 and the CPU2 brings the entire single chip microcomputer such as software standby to the stopped state, SS
One CPU with the BY bit set to "1"
Executes the SLEEP instruction, the CPU immediately transitions to the software standby state or the sleep state according to the state of the other CPU, and then the other CPU
Automatically selects whether to switch to the software standby state after executing the SLEEP instruction.
When creating a program, it is not necessary to confirm the mutual operating states, and the efficiency of creating the program can be improved.

(5). By providing a register DR that specifies which CPU 1 or 2 uses IOP0 to IOP11 in bit units, one input / output port is set to 2
It can be used by one of the CPUs 1 and 2, and the utilization efficiency of resources can be further improved.

(6). By providing the interrupt permitting circuit with a register for designating which CPU 1 or 2 the interrupt is requested, the input / output circuit is arbitrarily distributed between the two CPUs 1 and 2 and used. It is possible to improve the efficiency of resource utilization.

(7). By using one CPU mainly for data transfer by interruption, various processing at interruption can be easily performed.

(8). When the ROM1 and the ROM2 are composed of the PROM, the ROM1 and the ROM2 are arranged by arranging the ROM1 and the ROM2 at consecutive addresses in the PROM mode.
Can be made compatible with one PROM, and PROM writing can be made efficient.

(9). Corresponding to one physical address, C
Control for selecting which logical address to use when each PU1, 2 has a different logical address, or when it has a different physical address corresponding to one logical address of different CPUs 1, 2. Address data and the like for externally reading / writing a built-in functional block are supplied to a plurality of internal buses to which addresses are given by the CPUs 1 and 2 and data is input / output by giving signals. It is possible to supply data via a smaller number of buffer circuits so that the data required for this functional block can be directly read / written from the outside, facilitating the testing of the functional blocks contained in this single-chip microcomputer. ,
In addition, the testing efficiency can be improved.

(10). By making the CPU 1 and the CPU 2 compatible with each other, the development efficiency can be improved, and the support tools can be made common to improve the development efficiency of the development apparatus. it can. As a result, the number of development devices required by the user can be reduced, and the cost required for the development devices can be reduced.

(11). In the emulator of this single chip microcomputer, two CPUs 1 and 2 are used.
The debug efficiency can be improved by having an interrupt that independently stops the.

Further, in this embodiment, as shown in FIG. 15, a direct memory access controller (DM) is added to the single chip microcomputer of FIG.
AC) is connected to and added to IAB1 and IDB1 as in the case of CPU1, so that CPU1 and DMAC can mutually operate based on the bus right arbitration of the bus controller.

That is, the DMAC is
When the CPU 1 sets a predetermined control bit to “1”, an auto request for data transfer or DM
It has an external request function to perform data transfer when a predetermined signal is given to the A request terminal, and the transfer mode is a burst mode in which the CPU 1 is stopped and the bus is exclusively used to transfer data when in auto request. Alternatively, it is possible by having a cycle steal mode in which the bus right is released for each transfer and the data is transferred while operating alternately with the CPU 1.

Data can be transferred by using the interrupt request signal as a start request signal, and the data transfer can be performed at a higher speed than when the CPU 2 transfers data by interrupt.

Further, bus arbitration may be performed in a time division manner in addition to the read / write conflict.
For example, the bus right is given to the CPU1 and the CPU2 every eight states. If the bus does not end during the eight states, it operates until it ends. For example, CP
Bus states may be given to U1 in 4 states and to CPU 2 in 12 states.

(Embodiment 2) FIG. 16 is a block diagram showing a single-chip microcomputer which is another embodiment of the present invention, and FIG. 17 is a bus operation timing chart in the single-chip microcomputer of the present embodiment.

The single-chip microcomputer of this embodiment is different from that of the first embodiment in that IAB1, IAB2, and IAB1.
DB1 and IDB2 are commonly used as IAB / IDB, the data bus width is 32 bits, and ROM1 and ROM2 and RAM1 and RAM2 are also commonly used and read-only memory (ROM: readable storage means) / random This is an access memory (RAM), and these 32 bits can be simultaneously read / written.

Also, the CPU 1 (first data processing device)
And the CPU 2 (second data processing device) is time-shared,
Internal address bus (IAB) / internal data bus (ID
B /) is used to read / write the ROM / RAM. As described above, these CPU1 / 2 instructions are in 16-bit units, and the minimum instruction is executed in one state.

That is, for one CPU 1/2,
For instructions, read 16 bits in 1 state,
The instruction read amount and the instruction execution amount are equal. If you read an instruction with 32 bits, the number of instruction reads will be halved,
1 / IAB / IDB and ROM / RAM usage frequency
It can be 2. Therefore, CPU1 and CPU
2 can alternately read the instruction from the ROM by using the IAB / IDB, and can execute them in parallel.

Actually, even if an instruction is read with 32 bits such as a branch instruction, 16 bits are wasted, or the frequency of use cannot be reduced when accessing data, so that a complete parallel operation is possible. However, as described above, the number of times the instruction is read is large, and thus the present embodiment does not significantly reduce the processing speed as compared with the first embodiment. Also, by sharing the ROM / RAM,
It is possible to reduce the physical scale and arbitrarily set the memory capacity used by the CPU 1/2.

Next, an example of the operation timing of the internal bus will be described with reference to FIG.

The program for CPU1 / 2 is the same as that shown in FIG. 6, and the right to use the bus is such that CPU1 / 2 that used the bus last time is given priority, and in other cases, CP is used.
U2 has priority.

For example, IAB1 / 2 is output in synchronism with φ #, and reading of ROM and RAM of CPU1 / 2 is carried out in one state for 32 bits at a time. However, this is limited to 32-bit data starting from an address that is a multiple of 4.

First, IAB1 / 2 synchronizes with φ # to 1
ROM is output, but not limited to state output.
And latched in RAM in synchronism with φ. The corresponding read data is output in synchronization with φ #, and φ #
Are taken into CPU1 / 2 during the active state.

Similarly to the above, read / write for RAMP is performed in 2 states and read / write for I / O is performed in 3 states. IAB1 / synchronized with φ #
2 is synchronized with φ by the bus controller. In this case, the addresses m and n at which the head instruction exists are addresses that are multiples of 4.

At T1, the instruction fetch from the ROM of the CPU1 / 2 is requested, but the instruction fetch of the CPU2 is prioritized and the address m is output to the IAB.

At T2, the instruction code (first and second words of the BCLR instruction) read from the ROM to the IDB is changed to C.
The address n of the instruction fetch of the CPU 1 is output to the IAB while being fetched by the PU 2.

At T3, the CPU 1 fetches the instruction code (CMP, BEQ instruction) read from the ROM into the IDB, and the CPU 2 outputs the address SSR to the IAB. The use of the PAB / PDB of the CPU 2 is automatically permitted. In this case, since the SCI read requires three states, the CPU2 standby signal goes high.

At T4, the contents of IAB are output to PAB, and the contents of SCI register SSR are read.
This read data is obtained at T6. On the other hand, the CPU 1 requests the instruction fetch, but since the CPU 2 is using the bus, it is put on hold and the CPU 1 standby signal goes high.

At T5, both CPU 1/2 are in the standby state.

At T6, the CPU 2 takes in the data read from the SCI register SSR via the PDB and IDB. Further, the CPU 2 requests the next instruction fetch, but the instruction fetch of the CPU 1 is prioritized, the CPU 1 standby signal becomes the low level, and the CPU 2 standby signal remains at the high level. In this case, the instruction fetch address n + 4 of the CPU 1 is output to the IAB.

At T7, the instruction code (first word of the BTST instruction) read from the ROM to the IDB is sent to the CPU1.
Takes in. In this case, the CPU 1 requests the fetch of the branch destination instruction, but the instruction fetch of the CPU 2 is prioritized, the CPU 2 standby signal becomes low level, and the CPU 1 standby signal becomes high level.

At T8, the CPU 2 takes in the next instruction code read from the ROM to the IDB. In this case,
The CPU1 standby signal goes low, and the instruction fetch address N1 of the CPU1 is output to the IAB.

At T9, the CPU 1 fetches the instruction code read from the ROM to the IDB, but this is not executed because the branch condition is not satisfied. BTST fetched first
The first word of the instruction is valid. In this case, CPU1
Requests the next instruction fetch, but CPU2 is prioritized and the CPU1 standby signal goes high.

On the other hand, the CPU 2 sets the address SSR to IAB.
Output to. The use of the PAB / PDB of the CPU 2 is automatically permitted. Here, since the SCI read requires three states, the CPU2 standby signal goes high.

At T10, the contents of IAB are output to PAB, and CPU 2 outputs the data to be written in address SSR to PDB via IDB. Here, the CPU 1 is in a standby state.

At T11, the CPU2 standby signal goes low.

At T12, the CPU1 standby signal goes low, and the instruction fetch address n + 6 of the CPU1 is output to the IAB.

At T13, the instruction code (the second word of the BTST instruction) read from the ROM to the IDB is sent to the CPU.
1 takes in. In this case, the CPU1 has the address POR
The CPU 2 requests the read of T and the instruction fetch from the ROM, but the CPU 2 is prioritized and the CPU 1 standby signal becomes the high level. Here, the address m + 8 of the instruction fetch of the CPU 2 is output to the IAB.

At T14, the CPU 2 takes in the next instruction code read from the ROM to the IDB. In this case, the CPU 1 outputs the address PORT to IAB.
Here, since the read of the input / output port requires three states, the CPU1 standby signal becomes high level again.

At T15, the contents of IAB are output to PAB and the contents of the register PORT of the input / output port are read. This read data is obtained at T17. On the other hand, the CPU 2 requests the instruction fetch, but since the CPU 1 is using the bus, it is put on hold and the CPU 2 standby signal goes high.

As described above, in this embodiment, as shown in FIG.
Although the execution time is longer than that of the first embodiment,
It can be shorter than the case where it is realized by at least one CPU 1/2.

First, a CP is executed at an interrupt or a subroutine branch.
The work of saving and restoring the internal state of U1 / 2 can be excluded. Further, the two CPUs 1/2 can be shortened as compared with the case where they are simply operated alternately. This is because a larger amount of instructions that can be executed in a unit time by the CPU 1/2 from the ROM can be read in a unit time, and a time that does not use the bus is created, and this is made available to the other CPU 1/2. Is.

This is particularly effective when the program is arranged in the built-in ROM. Most of the read / write by the CPU is instruction read, and the internal memory has a read speed with respect to the external memory. This is because it is easy to improve and the width of the bus can be easily expanded.

At this time, the CPU 2 causes the DMAC and D
Even with a data processing device such as a TC or a data transfer device, similarly, data transfer can be performed with a minimum decrease in the processing speed of the CPU 1. Particularly, it is particularly effective for the DTC that needs to read the transfer information from the RAM before the data transfer.

Therefore, according to the single-chip microcomputer of this embodiment, the CP as the data processing device is
U1, CPU2, RO as readable storage means
M is the main configuration, IAB / IDB, ROM / RAM
In addition to Embodiment 1, the following operational effects can be obtained.

That is, a plurality of CPU1 / 2 are added to the IAB / IDB capable of reading a larger number of bytes in a unit time than the number of bytes of an instruction that the CPU1 / 2 can execute in a unit time.
, A plurality of CPUs 1/2 can use the IAB / IDB in a time-sharing manner to enable substantially parallel operation, and a common ROM / RAM can be arbitrarily distributed to be used, and a single-chip micro The processing speed of the computer can be improved and the resource utilization efficiency can be improved.

Although the invention made by the present inventor has been specifically described based on the first and second embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, the specific circuit configuration of the bus can be changed in various ways, such as IAB1, IDB1 and PA.
B and PDB may be directly connected. In this case, CPU1
The CPU 2 and the CPU 2 may read the programs in parallel and execute the programs. This increases the frequency of mutually restricting the operations, but the physical scale may be reduced in some cases.

RAM1, RAM2 and RAMP are set to 1
It may be one functional block.

Furthermore, the number of CPUs can be three or more. In this case, a plurality of CPUs are connected to the first bus, the buses are used in a time-sharing manner, and further one or more CPUs are used. The CPU may be connected to the second bus.

The built-in ROM is a mask ROM or PR.
CP such as OM, EEPROM, flash memory, etc.
Any memory may be used as long as it stores a program to be executed by U. The ROM1 and the ROM2 may be different.

Furthermore, there is no restriction on the type, function, number, etc. of the functional blocks requiring interrupts, such as timers and SCIs, or the functional blocks subject to interrupt processing, such as the pulse output circuit.

In the above description, the case where the invention made by the present inventor is mainly applied to the single-chip microcomputer which is the field of use thereof has been described, but the invention is not limited to this and other semiconductor integrated circuit devices. The present invention can also be applied to a semiconductor integrated circuit device including at least a plurality of data processing devices.

[0271]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1). Instructions stored in two independent readable storage means can be made readable by buses arranged in parallel in two data processing devices, or the width of the bus is expanded so that the data processing device can operate in unit time. In a single-chip microcomputer or a semiconductor integrated circuit device having a built-in function of making it possible to read instructions more than the number of executable instructions and supplying instructions capable of operating two data processing devices in parallel, It is possible to select at the same time, and by performing simultaneous writing or simultaneous reading of a plurality of storage means, the restriction on the number of channels for data processing by interruption can be eliminated, and the content of data processing can be made arbitrary. Realization, reduction of physical size, restriction of number of transfer channels, single-chip microcomputer or half It is possible to reduce the manufacturing cost of the conductor integrated circuit device.

(2) According to the above (1), the first and second data processing devices can be operated simultaneously, so that the processing speed of the single chip microcomputer or the semiconductor integrated circuit device can be improved.

(3). According to the emulation processor of the single-chip microcomputer or the semiconductor integrated circuit device, and further the emulator, two data processing devices can be independently stopped, so that debugging efficiency can be improved. Is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a single-chip microcomputer that is Embodiment 1 of the present invention.

FIG. 2 is an explanatory diagram of an entire address map in the single-chip microcomputer according to the first embodiment.

FIG. 3 is a block diagram of a bus connection state of the single-chip microcomputer according to the first exemplary embodiment.

FIG. 4 is a schematic block diagram of an interrupt controller according to the first embodiment.

FIG. 5 is a schematic block diagram of an interrupt request bit and an interrupt permission circuit according to the first embodiment.

FIG. 6 is an operation timing chart of the bus in the first embodiment.

FIG. 7 is a schematic block diagram of a low power consumption state control circuit according to the first embodiment.

FIG. 8 is an explanatory diagram of a register configuration for controlling an input / output port according to the first embodiment.

FIG. 9 is a schematic block diagram of an input / output port in the first embodiment.

FIG. 10 is an address map of the PROM in the first embodiment.

FIG. 11 is a block diagram of a main part of a PROM mode according to the first embodiment.

FIG. 12 is a block diagram of a main part of a test mode in the first embodiment.

FIG. 13 is a schematic block diagram of an emulation processor according to the first embodiment.

FIG. 14 is a schematic block diagram of an emulator according to the first exemplary embodiment.

FIG. 15 is a block diagram showing a modification of the single-chip microcomputer according to the first embodiment.

FIG. 16 is a block diagram showing a single-chip microcomputer that is Embodiment 2 of the present invention.

FIG. 17 is an operation timing chart of the bus in the single-chip microcomputer according to the second embodiment.

[Explanation of symbols]

CPU1 central processing unit (first data processing device) CPU2 central processing unit (second data processing device) ROM1 read only memory (first readable storage means) ROM2 read only memory (second readable storage) Means) RAM1, RAM2, RAMP Random access memory SCI Serial communication interface A / D A / D converter IOP0 to IOP11 I / O ports (data I / O means) IAB1 internal address bus (first bus) IAB2 internal address bus (first) 2 bus) PAB internal address bus (third bus) IDB1 internal data bus (first bus) IDB2 internal data bus (second bus) PDB internal data bus (third bus) DMAC direct memory access controller ROM Reed O Memory (readable storage means) RAM random access memory IAB internal address bus IDB internal data bus

Claims (14)

[Claims] 1. A semiconductor integrated circuit device having first and second data processing devices, bus control means, first and second readable storage means, and data input / output means, wherein: A first data processing device, the bus control means, and the first readable storage means are mutually connected by a first bus, and the second data processing device, the bus control means, The second readable storage means is mutually connected by a second bus, and the bus control means and the data input / output means are mutually connected by a third bus. Selecting whether to connect the first bus and the second bus to the third bus or not, and to perform reading using the first bus of the first data processing device and the second bus. The second bus of the data processing device A semiconductor integrated circuit device characterized in that it is possible to read used data in parallel. 2. A semiconductor integrated circuit device having first and second data processing devices and readable storage means, wherein the first and second data processing devices and the readable storage means are provided. Are connected to each other by a bus, and the first data processing device uses the bus to read and execute an instruction. To reduce the instruction execution speed of the first data processing device to a minimum without continuously reading the readable storage means using the bus and reading the readable storage means using the bus. The semiconductor integrated circuit device, wherein the second data processing device reads an instruction from the readable storage means. 3. The semiconductor integrated circuit device according to claim 1, further comprising an input / output unit capable of requesting an interrupt and an interrupt control unit, wherein the input / output unit capable of requesting the interrupt is provided. An interrupt signal to be output is input to the interrupt control means, and the interrupt control means outputs first and second interrupt request signals to the first and second data processing devices, respectively, A semiconductor integrated circuit device comprising: means for selecting which of the first and second interrupt request signals is to be activated in response to the activation of the signal. 4. The semiconductor integrated circuit device according to claim 1, 2 or 3, wherein said second data processing device has a writable register means, and said first data depends on a state of said register means. A semiconductor integrated circuit device capable of requesting an interrupt to a processing device. 5. The semiconductor integrated circuit device according to claim 1, further comprising a terminal for requesting an interrupt, wherein a predetermined signal change occurs at the terminal, A semiconductor integrated circuit device capable of requesting an interrupt to both of the first and second data processing devices. 6. The semiconductor integrated circuit device according to claim 1, further comprising an input / output unit including a register unit, and at least one of the register units included in the input / output unit. The register means has multiple bits,
A semiconductor integrated circuit device, characterized in that it is possible to select which of the first and second data processing devices is writable by the state of another register means. 7. The semiconductor integrated circuit device according to claim 6, wherein the register means that is selectable from which of the first and second data processing devices is writable controls the state of a terminal. What is claimed is: 1. A semiconductor integrated circuit device. 8. A method according to claim 1, 2, 3, 4, 5, 6 or 7.
The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is entirely stopped, a first standby state in which the first data processing device is stopped, and a second data processing device are stopped. It has an overall stop means, a first standby means, and a second standby means for respectively setting a second standby state, and has the overall stop state, the first standby state, and the second
Of the first data processing device and the second data processing device in response to the execution of a predetermined transition instruction, and the first data processing device sets the whole stop state. When the transition command is executed, if the second data processing device is in the second standby state, transition to the general stop state, and if the second data processing device is not in the second standby state, A semiconductor integrated circuit device, characterized in that it transits to a first standby state. 9. A semiconductor integrated circuit device according to claim 1, 2, 3, 4, 5, 6, 7 or 8, further comprising a test mode setting means and a buffer means. An address, a read and write signal, and an address space selection signal are input when the test mode setting means sets the test mode, and data is input and output according to the read and write signals. Specifies which address space of the first or second data processing device the input address corresponds to, and the readable storage means according to the address space selection signal and the address. Alternatively, the input / output unit is selected, and the readable storage unit or the input / output unit is selected in accordance with the read and write signals. A semiconductor integrated circuit device, which can be read and written. 10. The semiconductor integrated circuit device according to claim 1, 3, 4, 5, 6, 7, 8 or 9, wherein:
The second readable storage means is a first and a second electrically writable storage means, and has a write mode setting means and a buffer means, and the buffer means is the write mode setting means. When the test mode is set, an address, a read and a control signal are input, and writing is performed in the first and second electrically writable storage means according to the control signal. , Second
2. The semiconductor integrated circuit device according to claim 1, wherein the electrically writable storage means is arranged at continuously writable addresses. 11. The method according to claim 1, 2, 3, 4, 5, 6, 7,
An emulation processor for evaluating the semiconductor integrated circuit device according to 8, 9, or 10, wherein any of the data processing devices uses a bus on which the first and second data processing devices operate exclusively. An emulation processor characterized by outputting a signal indicating whether or not. 12. The emulation processor according to claim 11, further comprising first and second break interrupt input terminals for stopping the first and second data processing devices, The first data processing device is stopped in response to a predetermined state of the break interrupt input terminal, and the second data processing is performed in response to the predetermined state of the second break interrupt input terminal. An emulation processor characterized by stopping the device. 13. An emulator equipped with the emulation processor according to claim 11 or 12, further comprising a storage means and a system development device, and simultaneously operating information of the first and second data processing devices. An emulator having means for selecting whether to store in the storage means or selectively store operation information of one data processing device in the storage means based on a designation from the system development device. . 14. An emulator equipped with the emulation processor according to claim 11 or 12, further comprising break interrupt request means and a system development device, wherein the first and second data processing devices have breaks. An emulator having means for independently setting an interrupt request condition based on a designation from the system development device.