JP2001167058A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the wait time of a microprocessor and to improve throughput concerning an information processor which can perform parallel processing by employing a microprocessor typically exemplified by a CPU and a dedicated processor typically exemplified by a floating-point processing unit (FPU). SOLUTION: An information processor has a multi-FPU configuration. The state of FPUs 20a, 20b and 20c are monitored by an FPU state register 42 in an FPU connection control part 40. When a supporting instruction is requested from any one of CPUs 10a, 10b and 10c to an FPU state decoding part 44 in the FPU connection control part 40, an FPU selecting part 30 is controlled so that the FPU in the inactive and idle state can be linked other request CPU on the basis of information in the FPU state register 42. Besides, the trouble of data destruction in the use area of a temporary memory register 50 from a temporary memory register selection control part 70 through the control of a temporary memory register selecting part 60 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating point arithmetic unit (FPU) other than a main microprocessor such as a central processing unit (CPU).
It is related to an information processing device that is equipped with a dedicated processor (coprocessor) such as a processing unit and enables parallel processing of the microprocessor and the dedicated processor. In particular, it increases the use efficiency of the dedicated processor and the processing capacity of the microprocessor. It is related to technology that enhances

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of an electrical configuration of a conventional information processing apparatus having the above configuration. In FIG. 5, reference numerals 511 and 512 denote CPs.
U, 513, 514 are instruction memories (Inst Mem; instruction memory), 515 is data memory (DMEM),
520 is an FPU (floating point processing unit) exclusively for one CPU 512, 530 is a temporary storage register, 600
Denotes a main control unit (Main Ctrl), 601 denotes an instruction memory (Inst Mem), and 602 denotes a data memory (DMEM).

This multi-CPU information processing apparatus of the prior art uses a dedicated floating-point operation when a load to be processed by a CPU as a microprocessor increases, for example, when it becomes necessary to perform a floating-point operation. It is left to the FPU as a processor, and the CPU itself is configured to proceed with another process in the meantime, in other words, the CPU and the FPU can be processed in parallel.

[0004] Main control unit (Main Ctrl) 60
0 compiles (translates) a group of instructions, such as microcode, for each of CPUs 511 and 512;
The CPU determines which CPU is to perform the processing based on the operation state of the PU, and controls the operation of the entire apparatus.
For example, if the process to be performed is a normal calculation process, that is, a process that is completed without using an FPU, or a process of a control system,
Based on the operation status signals of the CPUs 511 and 512, the main control unit 600 determines which of the currently idle CPs
Request processing to U.

When the processing to be performed includes a floating-point operation requiring precision, the processing is requested to the CPU 512 having the FPU 521 as an additional function, regardless of the availability of the processing of the CPUs 511 and 512. Therefore, when the processing using the FPU 521 occurs continuously, the entire apparatus enters a waiting state, and the task is transferred to the CPU 512 only after the processing using the FPU 521 ends.

[0006] In the case of the above prior art, the FPU is connected to a specific CPU, and other CPUs have no right to use the FPU.

Therefore, an information processing apparatus having a multi-CPU / multi-FPU configuration in which FPUs are individually connected to individual CPUs in a one-to-one relationship is conceivable. Individual CPUs have other C
Regardless of whether the PU uses the FPU or not, the PU can be used independently.

[0008]

The prior art in which the FPU 521 is connected only to the former specific CPU 512 has the following problems. That is, after the CPU 512 passes the first task including the floating-point operation to the FPU 521, the CPU 512 performs a unique process. If the first task is not completed, it cannot be passed and the user must wait until the first task is completed.

For example, in an information processing apparatus for performing graphics processing in which the processing speed is increased and the amount of data to be handled is increasing, task processing including a floating-point operation which is indispensable especially for coordinate conversion and the like, and other processing. When tasks that require floating-point operations occur continuously, or when coordinate transformations occur one after another, the processing wait time increases in proportion to the number of coordinate points that need to be transformed. There is a problem that the performance is lowered.

In the case of the prior art in which the FPUs are connected for each CPU in a one-to-one relationship, the FPU
Even if a plurality of PUs are provided, one FPU is a dedicated one.
When a situation in which the FPU is used intermittently occurs in one CPU and the processing including the preceding floating-point operation is not completed in the FPU, the next floating-point operation is performed. However, there is a problem that the processing including the processing must be in a waiting state, and as a result, the performance of the entire apparatus is reduced.

In the above description, a CPU is taken as an example of a microprocessor, and an FP is used as a dedicated processor.
U (floating point arithmetic processing unit) has been taken as an example, but the above problem is not limited to the combination of CPU and FPU.
In general, this applies to an information processing apparatus that enables parallel processing between a microprocessor and a dedicated processor.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and is an information processing apparatus capable of performing parallel processing of a microprocessor such as a CPU and a dedicated processor such as an FPU. The aim is to improve In particular, it is an object of the present invention to improve the processing speed of a multi-CPU type information processing device that performs floating-point arithmetic processing.

[0013]

SUMMARY OF THE INVENTION An information processing apparatus according to the present invention, which aims to solve the above-mentioned problems, comprises:
It is equipped with a plurality of dedicated processors. And
Second, among the plurality of dedicated processors, a dedicated processor that is in an inactive state, that is, in a vacant state, can be selectively used. If a microprocessor occupies one dedicated processor and an instruction occurs on the same microprocessor that requires the assistance of a new dedicated processor, it may rely on another dedicated processor to execute the instruction. it can. Therefore, as long as there is an available dedicated processor, in other words, as long as there is an available dedicated processor,
The microprocessor does not need to wait for processing, can perform its own processing, and increases the processing capacity of the entire device.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be generally described. Hereinafter, instructions that require the microprocessor to support the dedicated processor will be referred to as “support-needed instructions” as necessary.

The information processing apparatus according to the first aspect of the present invention includes a plurality of dedicated processors in addition to the microprocessor, and when the microprocessor issues a request for an instruction requiring support, the information processing apparatus is set to an inactive state among the plurality of dedicated processors. The microprocessor is connected to a dedicated processor located at

According to the first invention, a plurality of dedicated processors are prepared for the microprocessor.
Accordingly, the microprocessor can have a right to use the currently inactive or free dedicated processor among the plurality of dedicated processors. Because there are multiple dedicated processors on the other side that can exercise such usage rights, some dedicated processors already operate when support-requiring instructions that require the support of the dedicated processor occur continuously or intermittently. Even if you are in a state, or the execution of the imposed instruction has not yet finished, you can use other available dedicated processors, so that the microprocessor does not have to wait. It will be good. The probability of not having to wait is greatly increased. This allows
It is possible to improve the processing capacity of the entire apparatus.

According to a second aspect of the present invention, there is provided an information processing apparatus comprising: a microprocessor; a plurality of dedicated processors; a selection means for selecting a connection state between the microprocessor and one of the plurality of dedicated processors; Connection control means for monitoring the state of the processor and controlling the selection means so as to connect the microprocessor to an inactive dedicated processor when requested by the microprocessor; It is. This corresponds to a more detailed description of the first invention.

The operation of the second invention is as follows. The microprocessor issues a request to the connection control means when a support-required instruction requiring the support of the dedicated processor is generated. The connection control means monitors whether a plurality of dedicated processors are currently operating or inactive, but grasps the state of each dedicated processor when there is a request from the microprocessor,
The selection means is controlled so as to connect the inactive and idle dedicated processor to the microprocessor which has made the request.

With the above-described operation, the second invention is, as described in the first invention, a case where a support-needed instruction requiring the support of the dedicated processor occurs continuously or intermittently. In addition, there is no need for the microprocessor to wait, and the probability that any available dedicated processor can be used is greatly increased. As a result, the processing capacity of the entire apparatus is increased. It leads to the improvement of.

According to a third aspect of the present invention, there is provided an information processing apparatus comprising: a plurality of microprocessors; a plurality of dedicated processors; and a selection means for selecting a connection state between one of the plurality of microprocessors and one of the plurality of dedicated processors. And connection control for monitoring the state of the plurality of dedicated processors, and when receiving a request from any of the plurality of microprocessors, controlling connection of the requested microprocessor to the inactive dedicated processor. And means. According to a third aspect of the present invention, in the above second aspect, there are provided a plurality of microprocessors, and any of the microprocessors, and the selecting means for any one of the microprocessors. It has a function.

The operation of the third invention is as follows. For ease of understanding, as an example, it is assumed here that there are two microprocessors μ1 and μ2 and two dedicated processors λ1 and λ2.

In this case, it is of course possible that μ2 activates the use right to λ2 while μ1 occupies λ1. Conversely, while μ2 occupies λ1, μ1
It is of course possible to use the right of use for λ2.

If μ1 occupies λ1 and μ1 receives the next support instruction, μ1 can also activate the right to use λ2.

Similarly, if μ1 occupies λ2 and μ1 receives the next support instruction, μ1 becomes λ2.
It is also possible to activate the use right for 1.

In the state where μ2 occupies λ1,
Assuming that the next support instruction is given to μ2, μ2 can also activate the use right to λ2.

Similarly, if μ2 occupies λ2 and μ2 has a next instruction requiring support, μ2 becomes λ2.
It is also possible to activate the use right for 1.

As another example, there are three microprocessors μ1, μ2, and μ3, and a dedicated processor is λ1
And λ2 and λ3.

In this case, μ1 occupies λ1, and μ2
Assuming that the next support instruction is issued to μ1 while occupying 3, μ1 can also activate the use right to λ2.

Similarly, μ1 occupies λ1, and μ2
If the next support instruction is issued to μ2 in a state in which μ2 is occupied, μ2 can activate the use right also to λ2.

As another example, there are three microprocessors μ1, μ2, and μ3, and a dedicated processor λ
Assume that there are four, 1, λ2, λ3, and λ4. The number of microprocessors and the number of dedicated processors need not necessarily be the same, and either may be greater or less.

In this case, μ1 occupies λ2, and μ2
Assuming that the next support instruction is issued to μ1 while occupying 1, it is possible for μ1 to activate the use right for λ3, and that μ2 has the next assistance instruction required. Then, μ2 can activate the use right for λ4 as well.

Further, if μ1 occupies λ2 and μ2 occupies λ3, and if μ1 receives the next support instruction, μ1 can activate the use right also for λ1. Assuming that μ1 has a further instruction requiring support, μ1 can also activate the right to use for λ4.

In the above example, if a plurality of microprocessors and a dedicated processor are in a parallel processing state and one of the processes is completed and a free space is generated in the dedicated processor, the other dedicated processor is still occupied. If the next microprocessor needs further support instructions, the right to use can be activated even for the dedicated processor having the vacancy.

As described above, according to the third aspect of the present invention, each microprocessor can use a plurality of dedicated processors extremely effectively in a very dynamic and fluid manner. Therefore, the waiting time of the microprocessor is reduced as much as possible, and the probability that the instruction requiring support can be immediately executed by using the dedicated processor is greatly increased, so that the processing capability of the entire apparatus can be greatly improved.

According to the fourth aspect of the present invention, in the information processing apparatus according to the third aspect, the data is received and temporarily stored from the microprocessor which has made the request, and the data is transferred to the requested dedicated processor. A temporary storage unit for relaying, wherein the microprocessor that has made the request performs its own processing after completing the data transfer to the temporary storage unit, and the dedicated processor that receives the instruction from the microprocessor executes the temporary processing. It is configured to execute the processing of the command of the request while accessing the storage means.

According to the fourth invention, when the microprocessor activates the use right for the special purpose processor,
The data necessary for executing the support required instruction is transferred to the temporary storage means. The dedicated processor which has received the request for the support required instruction may read the data necessary for executing the support required instruction from the temporary storage means instead of the microprocessor. As a result, the microprocessor can freely execute its own processing without being restricted by the processing of the dedicated processor, and can further improve the processing capacity.

According to a fifth aspect of the present invention, in the information processing apparatus according to the fourth aspect, between the plurality of microprocessors and the temporary storage means and between the plurality of dedicated processors and the temporary storage means. A temporary storage selecting means for selecting a connection state by being interposed, and setting an area corresponding to the dedicated processor in the temporary storage means based on information on which dedicated processor to be connected from the connection control means; Temporary storage selection control means for controlling the temporary storage selection means so as to connect the microprocessor which has made the request for the data transfer to the set area.

The operation of the fifth invention is as follows. Each dedicated processor is assigned its own area in the temporary storage means. The temporary storage selection control means controls the temporary storage selection means such that an area specific to the dedicated processor that has responded to the request is secured in the temporary storage means. As a result, even in the case where a certain microprocessor is connected to a certain dedicated processor and another microprocessor is connected to another dedicated processor in multiplex parallel processing, the temporary storage means is shared. Since the area used by each dedicated processor is clearly partitioned, it is possible to reliably prevent a problem that data necessary for processing is destroyed by overwriting of erroneous data.

In the information processing apparatus according to a sixth aspect of the present invention, in the first to fifth aspects, the microprocessor is a central processing unit (CPU) and the dedicated processor is a floating point processing unit (FPU). ), Etc. are numerical calculation processors (NDP: Numerical Data Processor).

This is particularly effective in an information processing apparatus for performing graphics processing in which the processing speed is increasing and the amount of data to be handled is increasing in recent years. For example, when task processing including floating-point arithmetic, which is indispensable for coordinate transformation, and other tasks requiring floating-point arithmetic occur continuously, or when coordinate transformation occurs one after another, According to the technology, the processing waiting time increases in proportion to the number of coordinate points that need to be converted, resulting in a decrease in system performance.
Since the overall processing capability is greatly improved as described above, it is possible to sufficiently cope with such graphics processing.

According to a seventh aspect of the present invention, in the information processing apparatus according to the first to sixth aspects, an external CPU is configured to be accessible as the plurality of microprocessors. The resources of the apparatus can be effectively used for the external CPU, and the total capacity can be improved.

In this specification, "CPU"
The description of (Central Processing Unit) only covers typical representatives, and other expressions such as “MPU” (Micro Processor Unit)
In addition to the above-mentioned examples, as a dedicated processor, for example, “DSP” (Digital Signal Process
or), which should be interpreted in the broadest sense.

Hereinafter, specific embodiments of a multi-CPU type information processing apparatus according to the present invention will be described in detail with reference to the drawings. In the following embodiments, a CPU (central processing unit) will be described as an example of a microprocessor, and an FPU (floating point processing unit) will be described as a dedicated processor.
Take for example.

FIGS. 1, 2 and 3 show a hierarchical structure in which a part of them is overlapped as an illustrated display. FIG. 1 is a block diagram illustrating a basic electrical configuration of a multi-CPU type information processing apparatus according to an embodiment of the present invention. FIG. FIG. 3 is a block diagram showing a more detailed wiring relationship and a more detailed relationship between a multi-CPU type information processing device and external elements; FIG.
FIG. 3 is a block diagram illustrating a more detailed configuration of an FPU connection control unit and a temporary storage register selection unit as components of a U-type information processing device.

First, the main configuration of the multi-CPU type information processing apparatus according to the present embodiment will be described with reference to FIG.

In FIG. 1, reference numeral 100 denotes a multi-CPU type information processing apparatus according to the present embodiment, 200 denotes an external storage device, and 300 denotes an external CPU. Also, 10a, 1
CPUs (central processing units) 0b and 10c are typical examples of microprocessors operating independently of each other, and 11a, 11b and 11c are CPUs 10a and 10c, respectively.
instruction memory (instruction memory: IM) storing instructions to be executed by b and 10c, 12a and 12
b and 12c denote data memories (DM) for storing data used by the CPUs 10a, 10b and 10c for processing;
Reference numerals a, 20b, and 20c denote FPUs (floating arithmetic units) that perform floating-point arithmetic processing as typical examples of dedicated processors, and 30 denotes a plurality of CPUs 10a, 10b, 10
c, and a plurality of FPUs 20a, 20b, 20c. The FPU selecting unit 40 switches the connection of control signals between the CPUs 10a, 10b, 10c by controlling the FPU selecting unit 30.
c controls the connection state between the FPUs 20a, 20b, and 20c.
0b, 20c is in an operating state or a non-operating state, and which CPU 10a, 10c
b, 10c and an FPU status register indicating information on which CPU is the master among the external CPUs 100. The FPU status register 42 may be treated as being included in the FPU connection control unit 40. The FPU selection unit 30 corresponds to “selection means” in the claims,
The PU connection control unit 40 also corresponds to “connection control means”.

The FPU status register 42 stores the FPU 20
a, 20b, and 20c are confirmed, and the operation states are transmitted to the CPUs 10a, 10b, and 10c.

The FPU connection control unit 40 includes a CPU 10a,
When a request for floating-point arithmetic processing as a representative example of the instruction requiring support is issued from any of 10b and 10c,
The FPU selection unit 30 is configured to decode the information of the FPU status register 42 and control the FPU selection unit 30 so as to connect any of the inactive, that is, free, FPUs and the requesting master CPU. Have been. C
PU 10a, 10b, 10c and FPU 20a, 20b,
The connection relationship of the connection 20c is not fixed and is always fluid.

The FPU to be connected to the CPU is
It is configured to execute a floating-point operation in response to a floating-point operation instruction from the CPU.

Reference numeral 50 denotes the CPU 10a, 10b, 10
c and a temporary storage register for temporarily storing data when transferring data required for floating point arithmetic processing from the master CPU of the external CPU 100 to the slave FPU. Temporary storage register 50
Includes data to be calculated when the FPU performs processing,
Other coefficients required for the calculation are temporarily stored. This temporary storage register 50 corresponds to "temporary storage means" in the claims.

By the way, for example, when the first CPU 10a and the third FPU 20c are connected, for example, the second CPU 10b and the first FPU 20c are simultaneously connected.
A state in which the terminal 20a is connected may occur. Furthermore, the third connection state may occur simultaneously. In such a case, while a certain CPU is accessing the temporary storage register 50, another CPU will simultaneously access the temporary storage register 50. At that time, accidental destruction of data may occur due to overwriting of data in the storage area of the temporary storage register 50.

Reference numeral 60 denotes a temporary storage register 50 and a CPU 10 for preventing such an inconvenience.
a, 10b, 10c and temporary storage register 50
A temporary storage register selection unit that arbitrates (arbitrates) connection states between the FPUs 20a, 20b, and 20c and between the temporary storage register 50 and the external CPU 300 in a traffic-coordinated manner. Reference numeral 70 denotes a temporary storage register selection control unit that controls the temporary storage register selection unit 60 as described above as a result of the FPU connection control unit 40 decoding the FPU status register 42. The temporary storage register selection unit 60 may be a “temporary storage selection unit”.
And the temporary storage register selection control unit 70 also corresponds to “temporary storage selection control means”.

Next, a more detailed configuration of the relationship between the multi-CPU type information processing apparatus 100 and external elements will be described with reference to FIG.

Reference numeral 200 denotes an external storage device (DMEM) for the multi-CPU type information processing apparatus 100; 300, an external CPU; 310, an external instruction memory (IMEM) storing instructions to be executed by the external CPU 300;
Is an external data memory (DMEM) for storing data used for processing by the external CPU 300.

Reference numeral 81 denotes a multi-CPU type information processing apparatus 1.
00, a data memory interface (DMI) that controls communication with the external storage device 200 to input and output data processed by the CPUs 10a, 10b, and 10c.
F) and 82 are data bus arbitration units (Data Bus Arbiter) for arbitrating access (arbitration) between the CPUs 10a, 10b and 10c and the external storage device 200.
It is. 83 is a multi-CPU type information processing apparatus 100
CPUs 10a, 10b, 10c and external CPU 3
It is an I / O interface (I / O IF) for exchanging commands and data with the 00.

The FPU selection unit 30 and the FPU connection control unit 40 are connected to the CPUs 10a, 10b, and 10c inside the multi-CPU type information processing apparatus 100 in the same manner as described above.
It is also connected to the external CPU 300. In FIG.
FPU connection control unit 40 and CPUs 10a, 10b, 10c
And the external CPU 300 are connected by reciprocating arrow connection lines 84 and 85.
This indicates a request from the CPU and a confirmation (acknowledge) from the FPU.

Next, referring to FIG.
A more detailed configuration of the temporary storage register selection unit 60 will be described.

The FPU connection control unit 40 includes an FPU status decoding unit (DEC; Decode) in addition to the FPU status register 42.
r) 44 and an external CPU interface 46.

Each of the CPUs 10a, 10b, 10c
A request for a floating-point operation is sent to the PU state decoding unit 44. Upon receiving the request, the FPU state decoding unit 44 refers to the FPU state register 42 to determine whether there is any FPU in an inactive state, and which FPU it is in. And inform the results. Further, as described above, the FPU state decoding unit 44
The inactive FPU among the 20a, 20b, 20c is
A control signal is sent to the FPU selection unit 30 so as to connect to the CPU that has made the request. Reference numeral 84a denotes a request signal line, and reference numeral 84b denotes an acknowledge signal line, which correspond to the connection line 84 in FIG.

It should be noted that, in addition to judging the inoperative state of the FPU, strictly the use state of the FPU is defined as
Of course, the state in which the CPU serving as the master of the corresponding FPU is transferring the data for calculation to the temporary storage register 50, and, conversely, the result of the calculation is temporarily stored. This also includes a state in which data is transferred from the register 50 to its own data memory.

The temporary storage register 50 has three FPUs 2
0a, 20b, 20c, three banks 50a,
50b and 50c. The temporary storage register selection unit 60 includes the CPUs 10a, 10b, 10c and the FPU 2
0a, 20b, 20c and external CPU 300
From the first plurality of selectors 60a # for switching the writing to each of the banks 50a, 50b, 50c.
And CPUs 10a, 10b, 10c and FPU 20
banks 50a, 50a from each of a, 20b, 20c
a second selector 60b # for switching the reading of each of the banks b and 50c, and a third selector 60c for switching the reading of each of the banks 50a, 50b and 50c from the external CPU 300. Have.

The temporary storage register selection control section 70 controls each of the selectors 60a, 60a in the temporary storage register selection section 60.
0b and 60c are arbitrated. This prevents the temporary storage register 50 from destroying data due to overwriting. The detailed operation of this will be described later.

Next, the operation of the multi-CPU type information processing apparatus 100 of the present embodiment configured as described above will be described with reference to the flowchart of FIG.

In step S10, external CPU 300
Assigns processing to be performed by the CPUs 10a, 10b, and 10c in each device. In step S20, each of the CPUs 10a, 10b, and 10c is activated to start processing. Each of the activated CPUs 10a, 10b, 10
In step c30, it is determined whether or not the floating-point arithmetic processing is necessary in step S30. If the floating-point arithmetic processing is not necessary, the process proceeds to step S40 to execute normal processing without floating-point arithmetic. Then, in step S200, the process waits until the end condition is satisfied.

On the other hand, if it is determined in step S30 that floating point arithmetic processing is necessary, step S10
0, the corresponding calculation instruction group is stored in the FPU 20a, 20b, 2
0c, the corresponding CPU
A request for using the FPU is issued to the FPU state decoding unit 44 in the U connection control unit 40.

The FPU status decoding unit 44 that has received the request
Checks the status of the FPU status register 42 in steps S110 and S120. That is, the FPUs 20a, 20
It monitors whether any one of b and 20c is inactive, that is, is empty. And
If there is no empty FPU, step S130
To send a standby signal to the requesting CPU.

When there is an empty FPU or when an empty FPU is generated, the request is permitted, and in step S140, the available FPU (20a, 20b, 20c) is released from the CPU. ) Used by the bank (50
a, 50b, or 50c).

Then, in step S150, the corresponding FPU executes the floating-point arithmetic processing according to the instruction of the current master CPU. At this time, the master CPU causes the FPU to execute speculatively. Therefore, the CPUs 10a, 10b, 10
c, and any FPUs 20a, 20b, 2
There are various combinations with any of the speculatively connected FPUs of Oc.

In a state where one CPU and one FPU are connected to execute processing, another CPU and another FPU can execute processing in parallel. It is also possible for the remaining CPUs and the remaining FPUs to execute processing in parallel.

Also, when instructions requiring support of the FPU are generated continuously or intermittently in the same CPU, the same CPU is used for a plurality of different FPUs simultaneously or in parallel. It can happen that you are exercising the right. For details, refer to the operation according to the third aspect of the description. μ _i , λ _i (i = 1, 2 ‥) as described above.

When the floating point arithmetic processing is completed in each FPU, in step S160, the FPU
The status register 42 changes to a status indicating that the processing has been completed for the FPU itself, and notifies the CPU serving as the master. In response, the CPU that has received the notification stores the calculation result in the temporary storage register 50. To its own data memory (any of 12a, 12b and 12c). Then, the process proceeds to step S200, and waits until an end condition is satisfied.

If it is determined in step S200 that the termination condition has been satisfied, the flow advances to step S210 to terminate the external CPU 300 and wait for the next command. That is, in step S220, the external CPU 30
0, and if there is a startup, the process returns to step S20. In step S230, the process waits for the end of the system.
If not, the process returns to step S220.

Next, prevention of data destruction due to data overwriting caused by sharing the temporary storage register 50 will be described.

As described above, the temporary storage register selector 60 is for preventing the data stored in the temporary storage register 50 from being accidentally destroyed by overwriting of incorrect data.

One of the CPUs 10a, 10b, and 10c in the information processing apparatus 100 of the multi-CPU system uses the FP
When it is desired to perform the processing of the floating-point arithmetic system on any of U20a, 20b, and 20c, first, data necessary for the arithmetic operation is stored in the data memory (12a, 12b, 1) of the CPU itself.
2c) to the temporary storage register 50. At this time, the relevant CPU does not overwrite the data in the address area in the temporary storage register 50 that is being accessed by the FPU used by the other CPU. , A FPU use request is issued to the FPU status register 42.
And permits communication to the inactive or empty FPU.

When the FPU status register 42 confirms that a certain CPU is a master for a certain FPU and the FPU itself has not been activated yet, the FPU status decoding unit 44 confirms that fact. Based on the result of the decryption, the selector 60 in the temporary storage register selection unit 60 via the temporary storage register selection control unit 70
a $, 60b}, and a bank (50a, 50b, 50b) of the temporary storage register 50 in an area accessed by the FPU.
50c), the input and output buses from the master CPU are connected to the input and output ports, and control is performed so as to restrict access to only a predetermined address area.

When the master CPU activates the FPU, it is connected to the input and output ports originally used by the FPU, and causes the FPU to perform floating point arithmetic processing.

Finally, when the processing of the FPU is completed and the result remains in the temporary storage register 50, the input and output buses of the master CPU are connected again,
Transfers the operation result to its own memory
The connection control unit 40 is notified of the invalidity of the activation signal, and the processing thereafter is started.

By performing the above connection control,
Destruction of data used by another FPU can be prevented.

As described above in detail, according to the information processing apparatus of the present embodiment, a configuration is employed in which a plurality of FPUs exist, and one of the CPUs causes an existing FPU to process a floating-point arithmetic instruction. Even if it is in a state, when a new floating-point arithmetic instruction is issued to the same CPU, even if the previous FPU has not completed the processing, if another FPU is free, the processing is performed there. It is possible to request. Therefore, the FPU is attached only to a certain CPU, or the CPU and the FPU have a one-to-one correspondence, which is a problem of the related art in an application in which floating-point arithmetic processing frequently occurs.
The problem of the latency of floating-point arithmetic instructions caused by hardware limitations such as not being able to be connected can be solved successfully, the latency can be significantly reduced, and the performance of the entire device is improved. It was possible to do.

The embodiments of the present invention have been described above in detail. However, the present invention is not limited to the above embodiments, and can include the following embodiments. (1) The number of microprocessors represented by the CPU has been described as being plural. However, the number is arbitrary, and a plurality of microprocessors other than the three shown in FIG. Shall be included. That is, even a single microprocessor may include a configuration in which a plurality of dedicated processors are selectively connected thereto. (2) When the master CPU requests the FPU to execute the instruction requiring support, the data is transferred from the CPU to the temporary storage register 50. However, it is not necessary to be limited to this.
May be omitted and the FPU may be configured to access a data memory attached to the CPU. (3) Even if the temporary storage register 50 is provided, a plurality of temporary storage registers dedicated to each FPU may be provided instead of a common one, or a plurality of temporary storage registers dedicated to each CPU may be provided. It may be provided.

The above items (1) to (3) are independent of each other, and any number of these items may be appropriately combined.

It is to be noted that any matter described in the specification or the drawings of the present application may be omitted, added to the claims, and modified in the detailed description of the invention.

[0084]

According to the present invention, a CPU (Central Processing Unit) is used as an example for a microprocessor.
U (Floating Point Arithmetic Processor) is provided with a plurality of dedicated processors as an example, and after confirming that the dedicated processor is not operating and is idle, a reasonable connection between the microprocessor and the dedicated processor When an instruction requiring the assistance of a new dedicated processor occurs in the same microprocessor while the microprocessor occupies one dedicated processor, execution of the instruction is performed by another dedicated processor. Can be relied upon. Therefore, as long as there is an empty dedicated processor, the microprocessor does not need to wait for processing, and can perform its own processing, thereby greatly increasing the processing capacity of the entire apparatus.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic electrical configuration in which a main configuration in a multi-CPU information processing apparatus according to an embodiment of the present invention is extracted and shown;

FIG. 2 is a block diagram showing a more detailed wiring relationship inside the multi-CPU information processing apparatus of the embodiment of FIG. 1 and a more detailed relationship between the multi-CPU information processing apparatus and external elements;

FIG. 3 is a block diagram showing a more detailed configuration of an FPU connection control unit and a temporary storage register selection unit as components of the multi-CPU type information processing apparatus according to the embodiment of FIG. 1;

FIG. 4 is a flowchart showing the operation of the multi-CPU type information processing apparatus according to the embodiment;

FIG. 5 is a block diagram showing an electrical configuration of a conventional multi-CPU type information processing apparatus.

[Explanation of symbols]

10a, 10b, 10c: CPU (Central Processing Unit) as an example of a microprocessor 11a, 11b, 11c: Instruction memory 12a, 12b, 12c: Data memory 20a, 20b, 20c: FPU (Floating) as an example of a dedicated processor Decimal point arithmetic processing unit) 30 FPU selection unit as an example of selection unit 40 FPU connection control unit as an example of connection control unit 42 FPU status register 44 FPU status decoding unit 46 External CPU interface 50 Temporary storage unit Temporary storage registers 50a, 50b, 50c as banks 60 temporary register selection units 60a, 60b, 60c as selectors for temporary storage selectors 70 temporary storage register selection control units 81 as temporary storage selection control units 81 Data memory interface 82 ... Bus are placed arbitration unit 83 ... I / O interface 84a ... signal line 84b ... acknowledge signal line 100 ... multi-CPU system of the information processing apparatus 200 ... external storage device 300 ... external CPU 310 ... external instruction memory 320 ... external data memory request

Claims (7)

[Claims] A plurality of dedicated processors in addition to the microprocessor, wherein the microprocessor is connected to an inactive dedicated processor among the plurality of dedicated processors when the microprocessor makes a request. An information processing apparatus characterized by being configured as described above. 2. A microprocessor, a plurality of dedicated processors, a selection means for selecting a connection state between the microprocessor and one of the plurality of dedicated processors, and a state monitoring the plurality of dedicated processors. An information processing apparatus comprising: a connection control unit that controls the selection unit so as to connect the microprocessor to a dedicated processor in an inactive state when a request is received from the microprocessor. 3. A plurality of microprocessors, a plurality of special purpose processors, a selection means for selecting a connection state between any one of the plurality of microprocessors and any one of the plurality of special purpose processors, and a state of the plurality of special purpose processors And connection control means for controlling connection of the requesting microprocessor to an inactive dedicated processor when a request is received from any of the plurality of microprocessors. Information processing device. 4. A relay temporary storage means for receiving the data from the microprocessor which has made the request and temporarily storing the data, and transferring the data to the requested dedicated processor. After the completion of the data transfer to the temporary storage means, it executes its own processing, and the dedicated processor receiving the instruction from the microprocessor executes the processing of the instruction of the request while accessing the temporary storage means. The information processing apparatus according to claim 3, wherein the information processing apparatus is configured. 5. A temporary storage selecting unit interposed between the plurality of microprocessors and the temporary storage unit and between the plurality of dedicated processors and the temporary storage unit to select a connection state; An area corresponding to the dedicated processor is set in the temporary storage means based on information on which dedicated processor is to be connected from the connection control means, and the microcontroller which has made the request for the data transfer to the set area is set. The information processing apparatus according to claim 4, further comprising: a temporary storage selection control unit that controls the temporary storage selection unit so as to connect a processor. 6. The microprocessor according to claim 1, wherein said microprocessor is a central processing unit (CPU), and said dedicated processor is a numerical processor (NDP) such as a floating point processing unit (FPU). An information processing device according to any one of the above. 7. The information processing apparatus according to claim 1, wherein an external CPU is configured to be accessible as said plurality of microprocessors.