JPH02201559A - Hierarchical memory controller - Google Patents

Abstract

PURPOSE:To access plural memories without a special instruction by deciding the access to a main memory or that to a filing device in accordance with the access address lower than the demarcation point address between the main memory and the filing device or higher than the address. CONSTITUTION:A memory bus 3 is connected to a system bus 1, to which an arithmetic processor 2 is connected, through a bus isolation mechanism 4, and a main memory 5 and a file memory 62 are connected to the memory bus 3. The address of access from the arithmetic processor 2 to the main memory 5 and a filing device 6 is compared with the demarcation point address between the main memory 5 and the filing device 6, and the access to the main memory 5 or that to the filing device 6, and the access to the main memory 5 or that to the filing device 6 is decided in accordance with the comparison result. Thus, plural memories are accessed without a special instruction.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a control device for a hierarchical memory consisting of a plurality of memories, and in particular improves the processing power of the entire system and requires special instructions. The present invention relates to a hierarchical memory control device that allows access to multiple memories without any trouble.

[Conventional technology]

Conventionally, this type of hierarchical memory control device is configured by connecting a file memory to a system bus that connects an arithmetic processing unit and a main memory. Such hierarchical memory control devices employing a direct memory access control method are known. According to a hierarchical memory control device that employs such a direct memory access control method, when it is necessary to access a file memory, the arithmetic processing unit selects a memory address in the file memory, a memory address in the main memory where data is to be transferred, etc. An input/output device control command specifying the address, data transfer amount, and file memory read/write type is specified to the file memory. After that specification, the file memory autonomously transfers data to and from the main memory. When the data transfer is completed, the file memory provides an interrupt signal to the arithmetic processing unit to notify the arithmetic processing unit of the completion of the data transfer.

[Problem to be solved by the invention]

The conventional hierarchical memory control device described above uses a system bus connecting the arithmetic processing unit and the main memory for autonomous data transfer between the main memory and the file memory. There is. Therefore, when the processing unit uses other input/output devices connected to the system bus, if the autonomous data transfer between the main memory and the file memory is not completed, However, in data processing devices that require connection with a large number of input/output devices, there is a drawback that the performance of the entire system is reduced.

Further, although the main memory and the file memory differ in the data storage medium and access time, they are the same type of memory. However, there is a drawback in that there is a software restriction in that special input/output device commands must be prepared in order to access file memories that are of the same type but have different memory hierarchies.

The present invention has been made in order to eliminate the above-mentioned drawbacks, and is a hierarchical memory control device that improves the processing power of the entire system and allows access to multiple memories without the need for special instructions. The purpose is to provide

[Means to solve the problem]

In order to achieve the above-mentioned object, the hierarchical memory control device of the present invention connects an arithmetic processing unit connected to a system bus and performs various arithmetic processing, and the system bus and the memory bus according to the usage state. -Equipped with a bus isolation mechanism for disconnecting, a main memory connected to the memory bus, and a file device connected to the memory bus that can perform data transfer with the main memory. A configuration in which an address to be accessed to the memory and file device is compared with a demarcation point address of the main memory and file device, and it can be determined that the access is to the main memory or to the file device based on whether or not the address exceeds the demarcation point address. It is characterized by the fact that

The present invention connects a memory bus to a system bus connected to an arithmetic processing unit via a bus isolation mechanism,
By connecting the main memorized file memory to this memory bus, the processing capacity of the entire system is improved, and the address accessed by the arithmetic processing unit to the main memory and file power 1ξ to the file device and the main memory file device By providing a function that can determine whether or not the access exceeds the demarcation point address with the demarcation point address of the demarcation point address of the This allows access to the site.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a hierarchical memory control device of the present invention.

In FIG. 1, the hierarchical memory control device connects an arithmetic processing unit 2 connected to a system bus l and executes various arithmetic processes, and a system bus 1 and a memory bus 3 according to the usage state of the memory bus 3. a bus isolation mechanism 4 that connects and disconnects with the memory bus 3; and a main memory 5 connected to the memory bus 3;
and a file device 6 connected to the memory bus 3 and capable of transferring data to and from the main memory 5. The file device 6 includes a file memory control device 61 and a file memory 62. A file memory control device 61 in the file device 6 includes a main memory 5 from the arithmetic processing device 2 and a file memory 6 of the file device 6.
2 is compared with the demarcation point address of the main memory 5 and file memory 62, and it is determined that the access is to the main memory 5 or the file memory 62 based on whether the address exceeds the demarcation point address. The structure is such that it is possible to do so. Further, the file memory 62 of the file device 6 and the bus isolation 1lfa structure are connected so that the use request signal 100 and the use permission signal 200 of the memory bus 3 can be exchanged.

FIG. 2 is a block diagram showing the detailed configuration of the bus isolation mechanism 4 used in the same embodiment.

As shown in FIG. 2, the bus isolation mechanism 4 includes a bus interface circuit 41 that connects the system bus 1 and the memory bus 3, and a bus interface circuit 41 that connects the system bus 1 to the memory bus 3 during use. Display signal 300 and use request signal 1 from file device 6
00, and a competition circuit 42 that performs competition control with respect to 00. The contention circuit 42 is configured to supply a use permission signal 200 to the file device 6 and the bus interface circuit 41.

FIG. 3 is a block diagram showing the detailed configuration of the file device 6 used in the same embodiment.

In FIG. 3, the file device 6 includes an address buffer register 611 that receives memory address information from the memory bus 3, a memory demarcation point register 612 that stores the upper limit memory address of the main memory 5, and the contents of the address buffer register 611. a comparator 613 that compares the contents of the memory demarcation point register 612 with the memory bus interface control circuit 614 connected to the memory bus 3 and activated by the comparison result of the comparator 613; memory 6
2, and a device control circuit 615 for controlling the device control circuit 615. Memory bus interface control circuit 614
transmits the use request signal 100 to the bus isolation mechanism 4.
It is also possible to output a use permission signal 200 from the bus isolation mechanism 4.

The operation of the embodiment configured in this way will be explained.

Access from the arithmetic processing unit to the main memory> When it becomes necessary to access the main memory 5 from the arithmetic processing unit 2,
The arithmetic processing unit 2 transmits the address of the main memory 5, an instruction for reading/writing the main memory 5, and data in the case of writing onto the system bus l. System bus 1
The above information is received by the bus interface circuit 41 in the bus isolation mechanism 4. If the memory bus 3 use permission signal 200 from the contention circuit 42 is off at this point, the bus interface circuit 41 enters the through state, and the system bus 1 and memory bus 3 become logically directly connected, and the bus The busy display signal 300 output from the interface circuit 41 to the competition circuit 42 is turned on.

As a result, the address of the main memory 5 on the system bus 1, instructions for reading and writing the main memory 5, and in the case of writing, the write data are also sent to the memory bus 3 in the same way. Access to the main memory 5 is executed from the arithmetic processing unit 2.

Access from the processing unit to the file device> On the other hand,
When it becomes necessary to access the file device 6 from the arithmetic processing unit 2, the file device 6 can be accessed using the same procedure as for accessing the main memory 5, without requiring special input/output instructions as in the past. may be accessed. That is, the memory addresses of the main memory 5 and the file memory 62 of the file device 6 are allocated as consecutive addresses, and the demarcation point address is set in the memory demarcation point register 612 of the file device 6 shown in FIG. There is. The arithmetic processing unit 2 transmits a main memory address corresponding to the file memory 62 and main memory read/write instructions onto the system bus 1. Prior to this transmission, the arithmetic processing unit 2 determines in advance the number of words and the memory address of the main memory 5 necessary for exchanging data between the file device 6 and the main memory 5.
The only difference between access to the file device 6 and access to the main memory 5 is that it is set above .

This difference is due to the difference in access speed between the main memory 5 and the file memory 62 of the file device 6, and is intended to prevent the arithmetic processing unit 2 from opening or stopping access to the file device 6. This does not affect the effect of this embodiment in any way.

The main memory address and main memory read/write instructions sent on the system bus 1 are sent to the main memory 5.
It is received by the bus interface circuit 41 of the bus isolation mechanism 4 in the same way as the access to. Competitive circuit 4
If the use permission signal 200 from the system bus 2 is in an off state, the bus interface circuit 41 enters a through state and transmits information on the system bus 1 to the memory bus 3. Information on the memory bus 3 is received by the file memory control device 61 of the file device 6 shown in FIG.

Among these, the memory address of the memory is the file device 6
is set in the address buffer register 611 of the file memory control device 61. Address buffer register 6
11 and the contents of the memory demarcation point register 612 are as follows.
A comparator 613 compares them. If the memory address on the memory bus 3 set in the address buffer register 11 is equal to or greater than the value of the memory address set in the memory demarcation point register 612, it is identified as an access to the file memory 62, and the memory bus Interface control circuit 614 is activated. The memory bus interface control circuit 614 accesses the main memory 5 in order to obtain the number of words required for exchange with the main memory 5 and the transfer address of the main memory 5 set in the preliminary main memory 5. . In this case, the memory bus interface control circuit 614 turns on the main memory 5 use request signal 100. This use request signal 100 is received by the competition circuit 42 of the bus isolation mechanism 4. Further, if the in-use display signal 300 of the memory bus 3 of the system bus 1 is in the off state, the memory bus interface control circuit 614 turns on the use permission signal 200 of the memory bus 3, and the memory bus interface control circuit 614
It is also sent to the bus interface circuit 4I. As a result, the bus interface circuit 41 disconnects the system bus 1 and the memory bus 3 (isolates them).

The memory bus interface control circuit 614 that has received the use permission signal 200 connects the main memory 5 on the memory bus 3.
By transmitting the memory address and instructions for reading/writing the main memory 5 and accessing the main memory 5,
Receive information that has been set in advance. After that, the memory bus interface control circuit 614 sends an activation signal to the device control circuit 615, and the file memory 6
Start accessing 2. Device control circuit 615
When the file memory 62 is accessed, data transfer is performed between the main memory 5 and the file memory 62. At this time, too, the memory bus interface control circuit 614 sends the use request signal 100 to the bus. After transmitting the signal to the isolation mechanism 4 and receiving the use permission signal 200, the main memory 5 is accessed through the memory lot 3, thereby making it possible to access the main memory 5 while being disconnected from the system bus 1.

According to the embodiment described above, the memory bus 3 is connected to the system bus 1 to which the arithmetic processing unit 2 is connected via the bus isolation mechanism 4, and the main memory 5 is connected to the memory bus 3.
By connecting the file memory 62 of the file device 6 to the file memory 62 of the file device 6, the processing capacity of the entire system can be improved.

Further, according to the embodiment described above, from the arithmetic processing unit 2 to the file device 6, the main memory 5 right side and the file device 6
The access address is compared with the demarcation point address of the main memory 5 and the file device 6, and it can be determined that the access is to the main memory 5 or the file device 6 based on whether or not the address exceeds the demarcation point address. By providing this, multiple memories can be accessed without requiring any special instructions.

〔Effect of the invention〕

The present invention connects a memory bus to a system bus connected to an arithmetic processing unit via a bus isolation mechanism,
Connect the main memory and file device to this memory bus,
Compare the address accessed from the processing unit to the main memory and file device with the demarcation point address of the main memory and file device, and determine whether the main memory access or the file exceeds the demarcation point address. By providing a function that can determine that the access is by a device, the processing capacity of the entire system is improved and multiple memories can be accessed without the need for special instructions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the hierarchical memory control device of the present invention, FIG. 2 is a block diagram showing the detailed configuration of the bus isolation mechanism used in the embodiment, and FIG. 3 is a block diagram showing the detailed configuration of the bus isolation mechanism used in the embodiment. FIG. 2 is a block diagram showing the detailed configuration of the file device used. l...System bus, 2...Arithmetic processing unit, 3...Memory bus, 4...Bus isolation mechanism, 5...
...Main memory, 6...File device 61...File memory control device 62...
...File memory. Applicant NEC Corporation Representative Patent Attorney Umeo Yamauchi

Claims (1)

[Claims] an arithmetic processing unit connected to the system bus that performs various arithmetic processing; a bus isolation mechanism that connects and disconnects the system bus and the memory bus according to usage conditions; and a main memory connected to the memory bus. , a file device connected to the memory bus and capable of performing data transfer with the main memory, and the file device includes an address accessed from the arithmetic processing unit to the main memory and the file device, and a main memory/file device. A hierarchical memory control device characterized in that it can determine whether the access is a main memory access or a file device access based on whether or not the access exceeds the demarcation point address.