JPH0689258A - Bus control system - Google Patents

Abstract

PURPOSE:To improve the deterioration of the transfer ability of a bus, which occures by the internal processing time of a slave, and also to obtain a same kind of effect even in the continuous operation of a same master when the plural masters continueouly execute an operation in a data transmission bus. CONSTITUTION:The transfer control part 1m7 of the master 1 can receive a new transfer request in spite of the previously received transfer request from a main processing part and executes transfer to a bus in accordance with request receiving order. When response for a command transmitted to the bus is transmitted from the slave, the completion of transfer is recognized but, regardless of presence or absence of responce, the master can issue the command. When the command from the master is received, the transfer control part 4s6 of the slave 4 permits a command and data storage part 4s7 to store it, transmit it to a pre-processing part 4s8 in accordance with reception order and transmits responce from a responce and data transmissting part 4s5 to the bus when the pre-processing part 4s8 executes the access of a memory 4s1 so that are command processing is completed.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a bus control system.

[0002]

2. Description of the Related Art In the conventional bus control system, a master performing data transfer requests the use of the bus, and when the use of the bus is permitted by arbitration, the bus monopolizes the bus, issues a transfer command and transmits the transfer data. The reception is performed, and after the transfer is completed, the bus is released to control one transfer cycle. Therefore, while the slave receives and processes the command issued from the master, the master keeps the bus exclusively, and the other master cannot use the bus during that time. Also,
Since the master cannot execute one transfer cycle, when the same master operates continuously, the waiting time of the bus has a great influence.

[0003]

In the conventional bus control method, when one master device uses the bus, a bus use request is issued, and when the use of the bus is permitted, the exclusive command is issued and issued. Data transmission / reception is performed during one bus cycle. Therefore, if the time required for command and data processing by the slave becomes longer, one bus use cycle becomes longer, and the data transfer of the bus is not actually performed during the internal processing of the slave. There was a problem that it decreased. In addition, in the solution of the problem in the bus system, when considering the pipeline of a plurality of masters, if the same master operates continuously, a new cycle cannot be executed during its own bus cycle. Therefore, there is a problem that the transfer efficiency of the bus decreases.

Further, even if the transfer efficiency is improved by pipelining the transfer cycle of the bus, a new command cannot be executed during the preprocessing other than the access execution processing of the memory in the slave. However, there is still a drawback that it becomes a waiting time of the bus cycle and reduces the transfer efficiency.

Further, there is a drawback that exclusive memory access cannot be performed because the bus cycle is executed in a pipeline.

[0006]

According to the bus control method of the first invention, (A) the master requests the bus to be used by the main processing unit and requests the bus to be used, and the transfer control unit controls the bus to the bus. Command / data transmitting section that transmits command data by the slave, receives the response command sent from the slave to the command sent to the bus, recognizes that it is a response to the command sent by itself, and transfers the command. A response / data receiving unit that notifies the transfer control unit of the end and ends the transfer cycle, and receives data and sends it to the main processing unit when data is read from the slave. Even if there is a transfer request that has already received a transfer request from the command / data storage unit and main processing unit that stores the command data sent from the processing unit, Command data is stored in the command data storage unit according to the order of the received transfer requests, and the command data transmission unit is controlled in the order of reception to send the command data to the bus. When the response is sent from the slave and the response / data receiving unit receives the response reception notification, the main processing unit is notified of the completion of the transfer of the corresponding command in the command / data storage unit. A control signal transmission / reception unit that transmits / receives a bus control signal under the control of the control unit, notifies the response reception timing under the control of the transfer control unit when the response is received, and ends the response reception cycle under the control of the response reception unit. ) The slave sends the command sent from the master according to the command reception timing from the control signal transmitter / receiver. Command data receiving unit for sending the command data storage unit to be described later receives over data, command sent from the command data receiving unit
When the command / data storage unit that temporarily stores data and the pre-processing unit can accept processing, the unprocessed command data is sent from the command / data storage unit to the pre-processing unit in the oldest order, and the memory access ends. Then, the bus use request unit is controlled, the bus use request is made, and when the use of the bus is permitted, the response / data transmission unit is controlled to transmit the response and the data, and at the same time, the control signal transmission / reception is controlled and the transfer having the function of transmitting / receiving the control signal is performed. A bus use request unit that issues a bus use request under the control of the control unit and transfer control unit, and notifies the transfer control unit of the bus use permission when the bus use is permitted, and a response or data to the master when the memory access ends Of the response / data transmission section that transmits the control signal and the control signal of the transfer control section when transmitting the response, and the command signal when receiving the command / data. Control signal transmission / reception unit for notifying the data reception unit of command / data reception timing and ending the command cycle, processing command / data sent from the command / data storage unit to access the memory, and internal It has a pre-processing unit that executes processing sequentially.

The bus control method of the second invention comprises a plurality of processing units for executing actual memory access in the preprocessing unit,
A pre-processing control unit is provided for managing the operating state of the processing unit and controlling the most recently used processing unit to be used in the next process.

In the bus control system of the third invention, a command transmitted from the master has an instruction (hereinafter referred to as a prohibition instruction) for prohibiting execution processing of subsequent commands in the slave, and a command having a prohibition instruction. When the command is received, the execution of the subsequent received command is prohibited, and when a command having an instruction (hereinafter, referred to as a permit instruction) for permitting the execution processing of the command is received, the execution is prohibited by the prohibit instruction after the completion of the execution processing of this command. A transfer control unit for restarting the execution of the command is provided.

[0009]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention. Reference numeral 1 denotes a main processing unit 1m1 that performs basic processing other than bus transfer control, a bus use request unit 1m2 that requests bus use, a control signal transmission / reception unit 1m3 that transmits and receives and controls bus transfer control signals, and commands to the bus. -Command for sending data-Data sending section 1m4, Response from slave to command sent by master itself to bus-Response for receiving data-Data receiving section 1m
5, a command / data storage unit 1m6 for temporarily storing command data sent from the main processing unit 1m1, and a transfer control unit 1m7 for controlling bus use request and transfer according to a transfer request from the main processing unit 1m1. It

The slave 4 has a memory 4s1, a bus use request unit 4s2 for making a use request to the bus, and a control signal transmitting / receiving unit 4 for transmitting / receiving and controlling a transfer control signal for the bus.
s3, a command / data receiving section 4s4 that receives command / data transmitted from the master and sends the command / data to the command / data storage section 4s7, a response that sends a response to the master and data after processing of the command sent from the master
A data transmission unit 4s5, a transfer control unit 4s6 that controls the processing in which the commands sent from the master are received, and a command / data storage unit 4s that temporarily stores the command data sent from the command / data reception unit 4s4.
7. The pre-processing unit 4s8 processes command data sent from the command / data storage unit 4s7 and directly accesses the memory 4S1.

Masters 1 to 3 and slave 4 are control buses b
1 and a command / data bus b2, and is connected to the bus arbitration unit 5 by bus use request means r1, r2, r3, r4 and bus use permission notifying means a1, a2, a3, a4.

Next, the operation of the present embodiment thus constructed will be described. When the main processing unit 1m1 of the master 1 needs to transfer to the bus, it sends a transfer request to the transfer control unit 1m7 and sends command data to the command
Send to the data storage unit 1m6. The transfer control unit 1m7 notifies the bus use request unit 1m2 of the bus use request, and the bus use request unit 1m2 makes a bus use request to the bus arbitration unit 5 via the bus use request unit r1. When the bus use request is arbitrated by the arbitration unit 5 and the bus use is permitted via the bus use permission notifying means a1, the bus use request unit 1m2 notifies the transfer control unit 1m7.

The transfer control unit 1m7 causes the command / data storage unit 1m6 or the oldest command and data to be transmitted to the command / data transmission unit 1m4, and the command / data transmission unit 1m4 transmits the command and data to the command / data bus b2. Is sent. At the same time, the transfer control unit 1m7 controls the control signal transmission / reception unit 1m3 to send a bus control signal to the control bus b1. When a command is sent to the bus, the slave control signal transmitter / receiver 4s3 sends the command reception timing to the command / data receiver 4s4 from the timing sent from the control bus b1, and the command / data receiver 4s4 sends the command / data at this timing. The data is received and sent to the command / data storage unit 4s7. The control signal transmitting / receiving unit 4s3 sends a command cycle end notification to the master via the control bus b1. When the command transfer is completed, the transfer control unit 1m7 of the master 1 waits for a response from the slave.

The main processing section 1m1 can issue a transfer request to the transfer control section 1m7 when the next transfer is required, and sends the command data to the command / data storage section 1m6 for storage. The transfer control unit 1m7 is the main processing unit 1
The order of transfer requests from m1 is stored, and command data is transferred to the bus in the order received. The command can be issued even if the response from the slave 4 to the previously transmitted command is not transmitted. In the slave 4, the command data received by the command data receiving unit 4s4 is the command data storage unit. Sent to 4s7.

If the preprocessing unit 4s8 can accept the process, the transfer control unit 4s6 causes the command data storage unit 4s7 to send the command data to the preprocessing unit 4s8. The pre-processing unit 4s8 is capable of pipeline operation, and the memory 4s
The next command data can be processed before one access. When the next command data can be processed, the transfer control unit 4s6 is notified. If the next command data is stored in the storage unit 4s7, it is continuously sent to the preprocessing unit 4s7. The preprocessing unit 4s8 notifies the transfer control unit 4s6 when the access to the memory 4s1 is completed.

The transfer control unit 4s6 is a bus use request unit 4s2.
To request the bus use to the bus arbitration unit 5 via the bus use requesting means r4. When the bus arbitration unit 5 arbitrates and the bus use permission notifying means a4 notifies the bus use permission, the response / data transmission unit 4s5 sends a response through the command / data bus b2 and the control signal transmission / reception unit 4s.
3 sends a control signal via the control bus b1. When data is read from the slave 4, data is sent from the memory 4s1 to the response / data sending unit 4s5 and sent to the command / data bus b2.

When the response command is sent to the bus, the control signal transmission / reception unit 1m3 of the master 1 receives the control signal and sends the response reception timing to the response reception unit 1m5. At this timing, 1m5 receives a response, and when reading data from the slave 4, receives the data and sends the data to the main processing unit. When the transfer control unit 1m7 receives the response, it controls the control signal transmitting / receiving unit 1m3 to notify the end of the response cycle via the control bus b1. Upon receiving the response, the transfer control unit 1m7 notifies the main processing unit 1m1 that the transfer request has been completed, and in the case of reading, the response data receiving unit 1 receives data.
It is sent from m5 to the main processing unit 1m1.

As described above, the master 1 can issue the next command even after the command is issued but before the response is received from the slave, so that the next command transfer cycle is performed even during one bus transfer cycle of the same master. Can be executed.

FIG. 2 is a block diagram of the second embodiment of the present invention. The master and the bus arbitration unit are the same as in FIG. 1, and the preprocessing unit in the slave is configured as shown in FIG. Pre-processing unit 2
0 is a processing unit 2-2 that executes access to the memory 100.
1, 22-2, 2-2n, and a pre-processing control section 2-1 for controlling the command data sent from the command / data storage section 300 to the most recently used processing section. .

Next, the operation of this embodiment will be described. The operation of the master is the same as in claim 1 and only the operation of the preprocessing unit 20 in the slave will be described. The pre-processing control unit 2-1 manages the operating state of the processing units in the pre-processing unit 20 and controls the processing unit that was used most previously to be used next. When the command data is sent from the command data storage unit 3, the command data is sent to the processing unit 2-21 which was used most recently under the control of the preprocessing control unit 2-1. Further, the next command data is sent to the processing unit 2-22, and the processing units 2-21 and 2-22 can operate simultaneously. Each processing unit accesses the memory 100 after the processing is completed.

FIG. 3 is a block diagram of the third embodiment of the present invention. The master and the bus arbitration unit are the same as in FIG. 1, and the command / data storage unit in the slave is configured as shown in FIG. The command / data storage unit 10 is composed of a prohibition control unit 1-2 that controls a prohibition process for executing the command stored in the storage unit 1-1 according to a prohibition command and a permission command included in the command sent from the master. , The command / data receiving unit 200 and the preprocessing unit 30.

Next, the operation of this embodiment having such a configuration will be described. When the prohibition control unit 1-2 receives a command having a prohibition command, the prohibition control unit 1-2 stores the command and data in the storage unit 1-1 and enters a mode in which execution of subsequent commands is prohibited. Therefore, when the command having the prohibition command is sent to the preprocessing unit 30, the command data sent from the command data receiving unit thereafter is only stored in the storage unit 1-1 and is not sent to the preprocessing unit 30.

When the next prohibition control unit 1-2 receives a command having a permission command, the prohibition control unit 1-2 stores it in the storage unit 1-1 and, if the preprocessing unit 30 can accept the process, another command stored in the storage unit. Even if there is data, it is sent to the preprocessing unit 3 with priority. After that, the prohibition of the execution of the commands stored in the storage unit 1-1 is released, and the operation of sending the command data to the preprocessing unit 30 in the stored order is continuously performed.

[0025]

As described above, the bus control system of the present invention has the following advantages. (1) Even if a plurality of masters are connected to the bus, if only one master operates continuously, once on the slave side, By allowing the same master to issue the next command before the end of the command processing, the command is issued even during the waiting time caused by the slave side processing, which has the effect of improving the bus usage efficiency. . (2) In the command execution process on the slave side, there is an effect that the waiting time can be eliminated by a process other than memory access in which simultaneous operation is impossible. (3) There is an effect that exclusive memory access can be performed by temporarily prohibiting the bus access biline operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

[Explanation of symbols]

 1 to 3 master 4 slave 5 bus arbitration unit b1 control bus b2 command / data bus r1, r2, r3, r4 bus use request notifying means a1, a2, a3, a4 bus use permission notifying means 1m1 main processing unit 1m2 bus use request Part 1m3 Control signal transmitter / receiver 1m4 Command / data transmitter 1m5 Response / data receiver 1m6 Command / data storage 1m7 Transfer controller 4s1 Memory 4s2 Bus use requester 4s3 Control signal transmitter / receiver 4s4 Command / data receiver 4s5 Response / data Transmission unit 4s6 Transfer control unit 4s7 Command / data storage unit 4s8 Pre-processing unit

Claims (3)

[Claims] 1. A data transmission bus used in an information processing device, wherein a device (hereinafter referred to as a master) that issues a command (hereinafter referred to as a command) for transferring data and data according to a command issued by the master. A plurality of devices (hereinafter referred to as slaves) for receiving and transmitting data are connected to each other. (A) The master uses a bus use request unit that makes a bus use request at the request of the main processing unit, and a bus is controlled by a transfer control unit described later. Command to send command data to
The data transmission unit receives the response command transmitted from the slave to the command transmitted to the bus, recognizes that it is a response to the command transmitted by itself, and the transfer control unit described later that the command transfer is completed. To the main processing unit when the data is read from the slave, and the data reception unit sends a command to the main processing unit under the control of the transfer control unit described later. A command / data storage unit that stores data, a transfer request from the main processing unit can be continuously received even if a transfer request has already been received, and command data is stored in the command / data storage unit in the order of the received transfer requests. To control the command / data transmission section in the order in which they are received,
When the command / data is sent to the bus, the response from the slave is sent, and when the response / data receiving unit receives the response reception notification, the transfer that notifies the main processing unit of the transfer completion of the corresponding command in the command / data storage unit A control signal for transmitting and receiving a bus control signal under the control of the transfer control unit along with the control unit and command transfer, notifying the response reception timing under the control of the transfer control unit when receiving a response, and ending the response receiving cycle under the control of the response receiving unit (B) The slave has a transmission / reception unit, and the slave receives the command data transmitted from the master in accordance with the command reception timing from the control signal transmission / reception unit, and sends the command data to the command data storage unit described later. Command that temporarily stores command data sent from the receiver
When the data storage unit and the pre-processing unit described later can accept the processing, the command / data storage unit sends unprocessed command data to the pre-processing unit in the oldest order, and when the memory access is completed, the bus use request unit described later. When the bus use is permitted by controlling the control and the bus use request, the transfer / control unit which has a function of controlling the response / data transmitting unit to transmit the response and data and controlling the control signal transmission / reception and transmitting / receiving the control signal, the transfer control When the bus control is permitted by the control unit, the bus use request unit that notifies the transfer control unit of the bus use permission, the response / data transmission unit that transmits the response or data to the master when the memory access is completed, the response transmission Sometimes control signals are sent and received under the control of the transfer control unit, and when command data is received, command data is sent to the command data receiving unit. Control signal receiving unit that performs termination processing command cycle and notifies the signal timing,
A bus control method characterized by including a pre-processing unit for processing command data sent from a command / data storage unit to access a memory, and for sequentially executing internal processing. 2. The pre-processing unit is provided with a plurality of processing units for executing actual memory access, and manages the operating state of the processing units,
2. The bus control system according to claim 1, further comprising a pre-processing control unit for controlling the processing unit used most recently so as to be used in the next processing. 3. A command transmitted from the master has an instruction (hereinafter referred to as a prohibition instruction) for prohibiting execution of subsequent commands in the slave, and when a command having the prohibition instruction is received, subsequent reception commands are received. Prohibit the execution of
A transfer control unit that resumes the execution of a command whose execution is prohibited by the prohibition command after the command execution process is received when a command having a command execution process permitting command execution (hereinafter referred to as a permission command) is received. Item 1
Bus control method described.