JPS58129628A - Data channel device - Google Patents

Abstract

PURPOSE:To reduce the capacity of a buffer memory in a channel common controlling circuit by blocking the buffer memory and enabling each channel to use each block memory optionally. CONSTITUTION:A data channel device 20 consists of n channels 5-1-5-n, the buffer memory 2, a common control part 3, and a buffer memory block specifying part 4. An I/O starting signal is applied from a central processing unit (CPU) to the common control part 3 through a connection line 11. The common control part 3 sends a signal to request an idle memory block to the buffer memory block specifying part 4 through connection line 22. When receiving the address of the idle memory block through a connection line 21, the common control part 3 sends the address to the buffer memory 2 through a connection line 15, so that the idle memory block in the buffer memory 2 corresponding to the address is formed in a channel specified by the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data channel device, and more particularly to a data channel device that commonly controls buffer memories.

Data channel devices are used in computer systems to efficiently transfer data between input/output devices and main storage devices, and their basic operating functions are control of start-up and termination of input/output commands, and data transfer. There is control and input/output interface control. Of these, except for input/output interface control for input/output devices with slow processing speed (the circuit that performs this is called a channel), control is performed between the central processing unit, main memory, etc. The data channel device is capable of increasing speed and is designed to have control circuits such as startup control, termination control, data transfer control, etc. common to multiple channels (this circuit is referred to as a channel common control circuit) for the purpose of simplicity. A so-called common control type data channel device is often used. The data transfer buffer memory used in the data channel device to absorb the processing speed difference between the input/output device and the main memory device is also common to all channels, combining the advantages of centralization and the efficiency of data transfer. The control circuit and each channel are provided separately.

In conventional data channel devices, the buffer memory provided in this channel common control circuit has a fixed area for use for each channel. Therefore, if the usage area required for one channel is % bytes, if the number of channels is n, a buffer memory of K×n bytes is required.

On the other hand, the probability that all channels accommodated in a data channel device use the buffer memory at the same time is extremely small. Therefore, in actual use, the usage efficiency of the above-mentioned K x n byte buffer memory is extremely low, and more than necessary. The disadvantage is that it has a buffer memory with a capacity of .

SUMMARY OF THE INVENTION An object of the present invention is to provide a data channel device that eliminates the drawbacks of the conventional [ffi] described above and greatly reduces the capacity of the buffer memory in the channel common control circuit even though the number of channels is the same.

The device of the present invention includes a plurality of channels and a channel common control circuit that commonly controls the channels, and a data transfer buffer memory provided in the channel common control circuit includes a plurality of memory blocks of a predetermined size. In a data channel device divided into nine memory blocks, a first update signal is generated in response to a memory block request signal indicating a request for a self-memory block, and a first update signal is generated in response to a memory block return signal indicating a return of a free memory block. update signal generation means for generating a second update signal; and update signal generation means provided corresponding to each of the memory blocks to record the empty or full state of the core memory block and generate the first update signal and the buffer memory. In response to the address signal indicating the memory block at 4, the memory contents are updated from empty to full.
memory block state storage updating means for updating stored information from a base to an empty state in response to the update trust address signal of 2; and said buffer memory in response to the storage information of each of said memory block state storage updating means. generating an address signal indicating a free memory block within the block;
and address signal generation/output means for outputting the address signal in response to the update signal.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The data channel device 20, which is an embodiment of the present invention, has n
channels 5-1 to 5-n and buffer memory 2. It is configured to include a common control section 3 and a buffer memory block designation section 4.

In response to instructions from a central processing unit t (not shown), the data channel device 20 connects a storage device 1 to a connection line 17-
Channels 5-1 to 5-n are used to transfer data to and from a large number of input/output devices connected via channels 5-1 to 5-n. Although each input/output device is provided as shown in FIG. It is composed of a common control section 3 and a buffer memory block designation section 4, and is commonly provided for each channel to perform time division multiplex processing.

The input/output device number from the central processing unit via the connection line 11,
Distinction between used channel number and writing/reading.

When an input/output activation signal including the transfer data length etc. is given to the common control unit 3 of the data channel device 20, the common control unit 3 reads the channel command complex from the main storage device 11 and transfers this command to the specified channel. and the input/output device number and start the channel.

In the case of a write command, data is first read from the main memory device l and stored in the buffer memory 2. The channel activates the designated input/output device and sends the command to it based on the input/output device number and command given from the common control unit 3.

In this way, data is transferred from the buffer memory 2 to the channel by the exchange of the data transfer request signal from the channel, the response signal from the common control unit 3, the data transfer request signal from the input/output device, and the response signal from the channel. Transferred from a channel to an input/output device.

Regarding data transfer operation in the case of successive commands,
The data flow of the data transfer operation in the case of a write command can be reversed, and the explanation will be omitted.

The buffer memory used in the above data transfer operation is
In the conventional device, as mentioned above, the memory block is divided into n memory blocks, the same number as the number of channels. The connection from the central processing unit falls to use
When an input/output activation signal is given via the common control unit 3
is the memory block address (hereinafter abbreviated as B address) in the buffer memory so as to use the first memory block of buffer memory 2 corresponding to the 41st channel used for this data transfer. ) is supplied to the buffer memory 2 via the connection line 15. That is, the memory block used by the first channel is fixed to the first memory block, and memory blocks other than the it-th memory block cannot be used.

In this embodiment, if the first channel is an unused memory block (hereinafter referred to as a free memory block, and a memory block in use is hereinafter referred to as a memory block), the first channel is the first channel. ' It is configured so that any memory block can be used according to instructions from the buffer memory block specifying section 4, without being limited to the memory block/.

That is, when an input/output activation signal is given to the common control unit 3 from the central processing unit via the connection line 11, the common control unit 3
is connected to the buffer memory block designation unit 4 via the connection line 22.
A memory block request signal requesting a free memory block is sent to the central processing unit, the B address of the free memory block is received via the connection line 21, this B address is sent out via the connection line 15, and the central processing unit An empty memory block in the buffer memory 2 corresponding to this B address is provided to the designated channel. In this state, the free memory block becomes an island memory block. Furthermore, when the data transfer is completed and the occupied memory block is used, that is, it becomes a free memory block, the common control unit 3 sends a memory block return signal via the connection fs24, and also sends out a memory block return signal to the B address of the returned memory block. is sent out via the connection line 23.

In this way, each channel can use any memory block in accordance with instructions if there is a free memory block in the buffer memory 2.

To do this, a circuit is required to manage the empty and fanned states of memory blocks in buffer memory 2 and supply the B address of the empty memory block, and this role is played by the buffer memory block designator. This is part 4.

FIG. 2 shows a block diagram of the buffer memory block specifying section 4 used in FIG. 41. The illustrated example shows a case where the buffer memory 2 is divided into 16 memory blocks.

The buffer memory block specifying unit 4 specifies the B address of one free memory block, and in response to the memory block request signal from the common control unit 3, the buffer memory block specifying unit 4 uses a memory block return signal to specify whether the memory block is free or not in the buffer memory. The status update instruction circuit 300 and the backup memory management circuit 1 have a function of updating and managing the state of misfortune and creating a free memory prop "B address" to be provided as a free memory block based on this management state.
00 and B address generation circuit 200.

The status update instruction circuit 300 receives a memory block request signal or a memory block return signal from the common control unit 3, and changes the management status of the memory block from empty to blocked.
The first update signal M9 is a circuit that generates a second update signal that updates from 9 occupied to 9 empty.

The buffer memory management circuit 100 is provided with seven lip-flops corresponding to each divided memory block of the batza memory 2, and corresponds the reset state of each lip-flop to the blockage of the corresponding memory block. The usage status of each memory block is grasped in correspondence with the free space of the memory block to be updated, and the first update signal from the status update instruction circuit 300 and the B address from the B address generation circuit 200 (described later) or the status update instruction circuit 300 is generated. The second update signal from the common control unit 3
The usage state of the memory block is updated and managed from the B address and K from the address B, and the logic 1 is obtained from the block 1liIljl"l"70 corresponding to the free memory block.
A state signal of 0@ is supplied to the B address generation circuit 200.

The B address generation circuit 200 reads out the B address of the memory block to be used from the B address memory 203t or 204 according to the status signal supplied from the buffer memory management circuit 100, and sends this to the common control circuit 3 and the Batza memory management circuit reblock. A determining method for determining which one free memory block is used for data transfer can be selected as a predetermined amount, and based on this determining method, A correspondence is established between the status signal and the B address of the free memory block to be used.

If we always use the empty memory block with the lowest number among the 1st to 16th memory blocks, the correspondence between the status 0@ and the B address is the first one.
It becomes like fi.

Table 1 In Table 1, the x mark indicates that logic 11g can be -ao1 or either. For example, when the fifth memory block is to be used, data r0100J indicating the B address is supplied to the connection lines 36-1 to 36-4, and the status signal is [0OOIXXXXX].
XX) CXXXJ is supplied to the connection lines 33-1 to 33-16.

The B address memory 203 also includes connection lines 33-1 to 33-1.
The B address is stored as data in the addresses corresponding to the status signals up to 33-8. For example, r
The “B address” data “o l 00J” is stored at the address “00001xxx” corresponding to the status signal. 9゜rOlOoJ "B address"
The data is stored in each of eight addresses.

Similarly, KB address memory 204 is connected to dllia3-9.
The B address is stored as data at the address corresponding to the status signals from 33-16.

Any one of the connection lines 33-1 to 33-8 is logical %
In the case of 1%, that is, when the acid memory block among the 111th to 8th memory blocks is an empty memory block, the output of the OR gate 201 becomes logic 111, and this is used as a read signal for B. Read B address from address memory 203, all logic 1
If it is not 1I, the output of Nandogoo) 2-02 becomes logic all, and the B address is read from the B address memory 204 using this as a read signal. Reader's use 9B
One part of the address is supplied to the buffer memory management circuit 100, the other part is supplied to the AND gate 2OSD, and is supplied to the common control unit 3 via the connection line 21 in response to the memory block request signal.

Next, the operation of the buffer memory block specifying unit 4 will be explained separately for when a memory block is requested and when a memory block is returned. For convenience of explanation, the B address is 1 of the memory block.
It is set to 4 bits corresponding to 6.

(1) When a memory block is requested A memory block request corresponds to when data transfer is started from the storage device 1 to the buffer memory 2 or from a channel to the buffer memory 2. At the same time that a memory block request signal requesting a memory block to be used for the above data transfer is supplied from the common control unit 3 to the status update instruction circuit 300 via the connection m22, the memory block request signal opens the AND gate 205. Connection line 36
The B address of the free memory block that is supplied to the free memory block via the connection line 36-1 to 36-36
-4) is supplied to the common control unit 3 via the connection line 21.

In the status update instruction circuit 300, a flip-flop 303 is set in response to the memory block request signal, and a logical product of this output and the memory block request signal is created by the AND gate 302, and the result is output via the connection line 28. It is supplied to the buffer memory management circuit 100 as a first update signal.

The first update signal supplied to the buffer memory management circuit 100 drives the selection circuit 101 and connects the % connection line 36 and the connection line 2.
9 and the connection line 21 that was supplied to the common control unit 3 earlier.
The B address via the decoder 102 is supplied to the decoder 102. 1st
The update signal is 104-1-104
-16 to open these AND gates.

The decoder 102 decodes the B address and supplies logic "11" to one of the connection lines 30-1 to 30-16, which are its output lines.The first memory block among the 16 memory blocks Suppose that is a free memory block and it is available for use, the B address "0O00" is decoded by the decoder 102, and the decoder 102 outputs the data to the computer via the connection line 30-1.
Logic all is supplied to 3-1 and 104-1. Since the AND gate 104-1 has already been opened by the first update signal as described above, the logic 11' supplied from the decoder 102 via the connection line 30-1 is connected to the AND gate 104-1 and the connection. is supplied to the flip-flop 105-1 via the line 32-1, and the flip-flop 105-1
1 and resets one of the status signals supplied to the B address generation circuit 200 via the connection line 33-1 to logic I1.
Update from 0 to 10@.

The updated status signal is sent to the B address generation circuit 20.
0 receives and stores the "B address" data at the address corresponding to this updated status signal (OAG)
The B address is continued from the B address memory 203 or 204 by the continuation signal outputted from the Nant gate 201 or the Nant gate 202, and is supplied as the B address of the updated free memory block via the connection line 36 to the AND gate 205 to create a new memory. Prepare for block requests.

(2) When a memory block is returned) 4 When a riff'lock is returned, this corresponds to the time when data transfer from the buffer memory 2 to the main storage device 1 or from the buffer memory to the channel is completed. Common control unit 3
The B address of the 9 memory block used for the above-mentioned data transfer via the connection line 23 and a memory block return signal for returning this memory block are supplied to the buffer memory block specifying unit 4 via the connection line 24. O The status update instruction circuit 300 in the buffer memory block specifying section 4 resets the flip-flop 303 in response to the memory block return signal, and performs the AND gate 3ol between this output and the memory block return signal.
and the second jl! via connection 1i127!
It is supplied to the buffer memory management circuit 100 as a new signal.

The second update signal supplied to the buffer memory management circuit 100 is supplied to AND gates 103-1 to 103-16 to open these AND gates. -Force selection circuit 10
1 connects the connection lines 23 and 29 since the first update signal is not supplied via the connection line 28, and returns the B address of the return memory block supplied from the common control circuit 3 via the connection line 23. is supplied to the decoder 102. The decoder 102 decodes the B address and its output line is the connection f.
Logic 116 is supplied to any one of #130-1 to 30-16) For example, if the 8th memory block is returned, the B address "01ll" is n*s by the decoder 102. Rete, de: ff-da 102
(103-8 and 1 through connection line 30-8)
04-8 and supplies logic 111.

As mentioned above, 103-8 is already in the second
Since the logic 111 supplied from the decoder 102 via the connection line 30-8 is supplied to the flip-flop 105-8 via the AND gate 103-8 and the connection line 31-8, the flip-flop P1
05-8 to update one of the nine state signals supplied to the B address generation circuit 200 via the connection line 33-8 from logic I01 to logic I11.

The updated status signal is sent to the B address generation circuit 20.
0 receives and stores the "B address" data at the address corresponding to this updated status signal, and reads out the "B address" data output from OR gate 201 or ANDGOO) 202 (OR gate 201' in the case of the above example). The signal is read from the B address memory 203 or 204 (B address memory 203 in the above example) and supplied to the AND gate 205 as the B address of the updated empty memory block via the connection line 36 to prepare for a memory block request. do.

As described above, the buffer memory block specifying unit 4 can manage the usage status of memory blocks in the buffer memory 2 and supply the B address of a free memory block to the common control unit 3 in response to a memory block request. can.

In this way, in this embodiment, if there is a free memory block in the buffer memory 2, each channel can use the buffer memory 2 instead of fixing the channel and the memory block used by that channel in a one-to-one relationship as in the conventional device. Any memory block can be used according to instructions from the memory block specifying section 4.

On the other hand, considering that the probability that all channels accommodated in a data channel device use the buffer memory at the same time is extremely small in actual use, the buffer memory of conventional devices that prepares a memory block for each channel is extremely small. Although memory usage efficiency is very low, in this embodiment, free memory blocks can be freely used for any channel, so a buffer memory with high usage efficiency can be constructed with a small capacity. For example, the number of channels operating simultaneously in a data channel device is an average of 3(l) of all channels.
If so, in this embodiment, the capacity of the buffer memory can be reduced by IsO.

In this embodiment, the B address is 4 bytes, but the present invention is not limited to this. Furthermore, the correspondence between the B address and the status signal is not limited to this embodiment, but the correspondence between the B address and the status signal may be determined by adding conditions such as equal use of nine memory blocks in consideration of reliability. I can bring it.

As described above, the present invention blocks buffers and memory, and allows each channel to freely use each memory block without allocating each memory block fixedly to a channel. This has the effect of significantly reducing the capacity of a certain buffer memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 2 is a block diagram of a buffer memory block specifying unit used in the figure. In the figure, l... Main memory value d, 2...
...Buffer memory, 3...Common control unit, 4.
...Buffer memory block specification section, 5-1 to 5
-n...channel, l l~l 6, 1
7-1~l 7-n... Connection line. 20...Data channel device, 21-36...
... Connection line, 100 ... Buffer memory management circuit, 101 ... Selection circuit, 102 ...
...Decoder, 103-1 to 103-16, 104-1
~104-16,205...and gate%
105-1 to 105-16...Flip-flop, 200...B address generation circuit, 201.
...Oagoo), 202...Nant Gate, 203, 204...B address memory, 3
0G...Status update instruction circuit s 301,
302...antogame), 303...
flip frog.

Claims (1)

[Claims] A buffer memory for data transfer, which is made up of a plurality of channels and a channel common control circuit that commonly controls the channels, and which is provided in the scissor channel common control circuit, is arranged in a plurality of memory blocks of a predetermined size. In a divided data channel device, a first update signal is generated in response to a memory block request signal indicating a request for a free memory block, and a second update signal is generated in response to a memory block return signal indicating a return of a free memory block. an update signal generating means for generating an update signal; update the stored information from empty to cloudy in response to an address signal indicating a memory block in the buffer memory; and update stored information in response to the second update signal and an address signal indicating a memory block in the buffer memory. a memory block state memory update means for updating a memory block from a blocked state to an empty state; and an address signal for outputting an address signal indicating a free memory block in the buffer memory in response to the stored information of each of the memory block state memory update means. A data channel device comprising a generation output means.