JPS5710850A - History control system - Google Patents

History control system

Info

Publication number
JPS5710850A
JPS5710850A JP8469980A JP8469980A JPS5710850A JP S5710850 A JPS5710850 A JP S5710850A JP 8469980 A JP8469980 A JP 8469980A JP 8469980 A JP8469980 A JP 8469980A JP S5710850 A JPS5710850 A JP S5710850A
Authority
JP
Japan
Prior art keywords
reg
data
history
effective display
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8469980A
Other languages
Japanese (ja)
Inventor
Akiyoshi Kajiyama
Masaaki Inao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8469980A priority Critical patent/JPS5710850A/en
Publication of JPS5710850A publication Critical patent/JPS5710850A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To collect a necessary data by a history memory having a small capacity, as well, by selectively storing a data only when effective display of a data exists, in a history control system. CONSTITUTION:A data is transferred to registers REG-0, REG-1,...REG-n, and when an effective data has been set to said each register REG-i, ''1'' is set to an effective display bit latch Vi by a controlling circuit. A selecting circuit part 3 selects one of the registers REG-0-REG-n in accordance with contents of an effective display bits, outputs a state of the register to a history writing circuit 10, and writes it into a history memory 11. An error is detected by a malfunction circuit 1, and when a malfunction detecting latch 9 is set, write to the history memory is inhibited thereafter, and the contents of this memory is checked.
JP8469980A 1980-06-23 1980-06-23 History control system Pending JPS5710850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8469980A JPS5710850A (en) 1980-06-23 1980-06-23 History control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8469980A JPS5710850A (en) 1980-06-23 1980-06-23 History control system

Publications (1)

Publication Number Publication Date
JPS5710850A true JPS5710850A (en) 1982-01-20

Family

ID=13837906

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8469980A Pending JPS5710850A (en) 1980-06-23 1980-06-23 History control system

Country Status (1)

Country Link
JP (1) JPS5710850A (en)

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