JPS6454557A - Address parity checking circuit - Google Patents

Abstract

PURPOSE:To eliminate the need of an exclusive bit as a check bit of an address, and to decrease the number of elements of a storage circuit, by containing the check bit of an address data, in the check bit of an arithmetic data, etc., and writing it in the storage circuit. CONSTITUTION:At the time of writing an input data 100, a write signal 107 goes to ON, and a first selecting part 1 selects the data 100, and sets it to a data register 3. Also, a second selecting part 2 selects an address data 103 set to an address register 4, as a write address W. Subsequently, a parity generating part 5 generates an address parity 104 of the address data 103, and also, from a parity 102 of the data 100 set to the register 3, and the parity 104, an exclusive OR gate 6 generates a check data 105. Next, the data 101 of the input data 100 set to the register 3, and the check data 105 are written in the address W of a storage circuit 8, as write data 111, therefore, an address error can be detected as a data error, and the number of elements of the circuit 8 can be decreased.