JPS5672751A - Data transfer buffer unit - Google Patents

Data transfer buffer unit

Info

Publication number
JPS5672751A
JPS5672751A JP15029379A JP15029379A JPS5672751A JP S5672751 A JPS5672751 A JP S5672751A JP 15029379 A JP15029379 A JP 15029379A JP 15029379 A JP15029379 A JP 15029379A JP S5672751 A JPS5672751 A JP S5672751A
Authority
JP
Japan
Prior art keywords
stored
data
memory
memory unit
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15029379A
Other languages
Japanese (ja)
Inventor
Joji Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15029379A priority Critical patent/JPS5672751A/en
Publication of JPS5672751A publication Critical patent/JPS5672751A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to update the contents of a buffer memory by selecting addresses stored in prescribed sequence by providing address storing methods that store write/read positions of information in the buffer memory independently.
CONSTITUTION: Disk controller 4 receives instructions from CPU3 and fetches commands from main memory unit 1 via main memoyr controlle 2 and under those commands, data are selectively transferred between disk device 6 and main memory unit 1 via disk control adaptor 5. This controller 4 is provided with address counters 10W13, address selecting circuit 14 that selects outputs of counters 10W13, register 16 stored with data from device 6, and registers 20W23 and memory 17 stored with data transmitted to and received from main memory unit 1 and in prescribed sequence, addresses stored in memory 17' are selected, so that the contents of the buffer memory can be updated.
COPYRIGHT: (C)1981,JPO&Japio
JP15029379A 1979-11-20 1979-11-20 Data transfer buffer unit Pending JPS5672751A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15029379A JPS5672751A (en) 1979-11-20 1979-11-20 Data transfer buffer unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15029379A JPS5672751A (en) 1979-11-20 1979-11-20 Data transfer buffer unit

Publications (1)

Publication Number Publication Date
JPS5672751A true JPS5672751A (en) 1981-06-17

Family

ID=15493817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15029379A Pending JPS5672751A (en) 1979-11-20 1979-11-20 Data transfer buffer unit

Country Status (1)

Country Link
JP (1) JPS5672751A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59111556A (en) * 1982-12-16 1984-06-27 Fujitsu Ltd Access system of register file
JPS61193230A (en) * 1985-02-20 1986-08-27 Hitachi Ltd Magnetic disk controller
US4890226A (en) * 1984-02-29 1989-12-26 Fujitsu Limited Memory access control apparatus having empty real address storing memory and logical address/reat address pair storing memory

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59111556A (en) * 1982-12-16 1984-06-27 Fujitsu Ltd Access system of register file
JPS6330653B2 (en) * 1982-12-16 1988-06-20 Fujitsu Ltd
US4890226A (en) * 1984-02-29 1989-12-26 Fujitsu Limited Memory access control apparatus having empty real address storing memory and logical address/reat address pair storing memory
JPS61193230A (en) * 1985-02-20 1986-08-27 Hitachi Ltd Magnetic disk controller

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