GB2008817A - Data processing system including a cache store - Google Patents

Data processing system including a cache store

Info

Publication number
GB2008817A
GB2008817A GB7840336A GB7840336A GB2008817A GB 2008817 A GB2008817 A GB 2008817A GB 7840336 A GB7840336 A GB 7840336A GB 7840336 A GB7840336 A GB 7840336A GB 2008817 A GB2008817 A GB 2008817A
Authority
GB
United Kingdom
Prior art keywords
control
unit
store
cache
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7840336A
Other versions
GB2008817B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/853,982 external-priority patent/US4156906A/en
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of GB2008817A publication Critical patent/GB2008817A/en
Application granted granted Critical
Publication of GB2008817B publication Critical patent/GB2008817B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)

Abstract

A data processing system includes a cache store to provide an interface with a main storage unit for a central processing unit. The central processing unit includes a microprogram control unit in addition to control circuits for establishing the sequencing of the processing unit during the execution of program instructions. Both the microprogram control unit and control circuits include means for generating pre-read commands to the cache store in conjunction with normal processing operations during the processing of certain types of instructions. In response to pre-read commands, the cache store, during predetermined points of the processing of each such instruction, fetches information which is required by such instruction at a later point in the processing thereof. The cache store has a plurality of word locations arranged into a number of groups or sets of blocks of word locations, a data directory for storing addresses within a plurality of locations corresponding in number to the number of groups and a control directory including a plurality of multibit locations corresponding in number to the number of groups of blocks. The cache unit further includes an input command buffer for storing commands received by the data processing unit and control logic circuits. The control logic circuits include decoder circuits operative to set to a predetermined state the contents of a predetermined bit of the control directory multibit locations identified by the memory command when the data directory indicates that the information does not reside in the cache unit store. The control logic circuits include circuits for forwarding the command to main store.
GB7840336A 1977-11-22 1978-10-12 Data processing systems including cache stores Expired GB2008817B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US85394477A 1977-11-22 1977-11-22
US05/853,982 US4156906A (en) 1977-11-22 1977-11-22 Buffer store including control apparatus which facilitates the concurrent processing of a plurality of commands

Publications (2)

Publication Number Publication Date
GB2008817A true GB2008817A (en) 1979-06-06
GB2008817B GB2008817B (en) 1982-11-10

Family

ID=27127201

Family Applications (2)

Application Number Title Priority Date Filing Date
GB7840336A Expired GB2008817B (en) 1977-11-22 1978-10-12 Data processing systems including cache stores
GB8101981A Expired GB2080989B (en) 1977-11-22 1978-10-12 Improvements in or relating to data processing systems including cache stores

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB8101981A Expired GB2080989B (en) 1977-11-22 1978-10-12 Improvements in or relating to data processing systems including cache stores

Country Status (3)

Country Link
DE (1) DE2849448A1 (en)
FR (1) FR2425110B1 (en)
GB (2) GB2008817B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4225922A (en) * 1978-12-11 1980-09-30 Honeywell Information Systems Inc. Command queue apparatus included within a cache unit for facilitating command sequencing
US4583165A (en) * 1982-06-30 1986-04-15 International Business Machines Corporation Apparatus and method for controlling storage access in a multilevel storage system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611315A (en) * 1968-10-09 1971-10-05 Hitachi Ltd Memory control system for controlling a buffer memory
US3735360A (en) * 1971-08-25 1973-05-22 Ibm High speed buffer operation in a multi-processing system
FR111574A (en) * 1973-12-13 1900-01-01
JPS5440182B2 (en) * 1974-02-26 1979-12-01

Also Published As

Publication number Publication date
GB2080989B (en) 1982-12-08
GB2080989A (en) 1982-02-10
GB2008817B (en) 1982-11-10
FR2425110A1 (en) 1979-11-30
FR2425110B1 (en) 1986-04-11
DE2849448A1 (en) 1979-06-07

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee