GB1575877A

GB1575877A - Data processing system having writable store configuration

Info

Publication number: GB1575877A
Application number: GB1145178A
Authority: GB
Original assignee: Data General Corp
Current assignee: EMC Corp
Priority date: 1977-03-28
Filing date: 1978-03-22
Publication date: 1980-10-01
Also published as: BR7801804A; AU3329178A; FR2386076A1; JPS53121525A; DE2812982A1; NL7802303A

Description

(54) DATA PROCESSING SYSTEM HAVING AN IMPROVED YVRITABLE STORE CONFIGURATION (71) We, DATA GENERAL CORPORATION, a corporation organised and existing under the laws of the State of Delaware, United States of America, of Southboro Massachusetts 01772, United States of America, do hereby declare the invention, for which we pray that a Patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates generally to a microprogrammable data processing system.

Microprogrammed data processing systems by virtue of their architecture allow a computer instruction (macroinstruction) to be effected in firmware through a microprogram, as opposed to software. Thus an additional writable control storage unit (microinstruction memory) for storing microinstruction words, frequently referred to as a writable control store (WCS), is utilised. Such a writable control store technique enables a user to implement his own instruction set in micro-code. By tailoring the machine's instruction set to its application, overall speed is improved by the use of writable control store techniques.

One such writable control store configuration is described in U.S. Patent No.

3,990,052, issued to R. H. Gruner on November 2, 1976, and assigned to ourselves, specifically in FIG. 18 thereof.

In accordance with such previously described configuration the WCS is, in effect, treated as an output device for the purposes of loading, i.e., writing data therein-, and reading out of microinstruction data therefrom. Each location therein consists of 56 data bits (plus one parity bit) divided into three fields of 16 bits each and one 8-bit field. To load each of these fields requires two I/O instructions, one to specify locations in the fields to be loaded and the other to specify the data to be loaded into that location and field. Thus, eight I/O instructions are required to load each of 256 possible locations of WCS. Additional machine instructions are required for such functions as address calculation and loading of the accumulators with the data to be supplied to the WCS. The data and address information with respect thereto are transferred over the I/O data bus. While such data and address transfers are synchronized with the central processor unit (CPU) operating time cycle, such transfers are not in any sense controlled by the CPU clock.

Moreover, a plurality of I/O instructions are required to transfer the data to the correct location in the WCS, each transfer to data word being performed by separate instructions.

In accordance with such prior use configuration, the overall time for loading a single micro-intruction data word into the WCS is relatively long, particularly where such micro-instruction word is a 56-bit word comprising three 16-bit and one 8-bit macro-words, as in the particular configuration described in the system of the above reference issued patent. An improved method of data transfer and an improved timing system therefor is deemed desirable in order to achieve the desired overall high speed operation required in present day data processing systems.

In accordance with the invention, there is provided a micro-programmable data processing system comprising a central processor unit utilizing a central processor unit clock signal, a read-write micro-instruction memory, a micro-instruction register for the micro-instruction being executed, and control logic operative to write micro-instructions in the memory during a first selected part of the clock signal cycle and to fetch micro-instructions from the memory to the register during a second selected part of the clock signal cycle, in an arrangement such that a micro-instruction loaded into the register is available for execution substantially simultaneously with the writing of micro-instructions into the memory.

The invention further provides a method of writing micro-instruction words into and reading micro-instruction words from a micro-instruction memory of a data processing system having a central processor unit utilizing a specified central processor unit clock signal, wherein the micro-instructon words are written in only during a first selected portion of each operating time cycle and are read out only during a second selected portion of each operating time cycle.

Moreover, the WCS (micro instruction memory) configuration can be so arranged that blocks of data can be loaded therein in accordance with a single macro-instruction which is used to initiate the sequential retrieval from main memory and the sequential loading in WCS of large blocks of data words as opposed to the use of separate instructions required for accessing each of the non-sequentially stored macro-words and storing them into the WCS, as in the prior used system. In accordance therewith a single macro-instruction can initiate the loading of the entire data block into the required WCS storage locations given the address of the location in main memory of the initial macro-word to be loaded, the number of consecutive locations in main memory for the complete data block to be loaded and the location in the WCS memory where the initial macro-word is to be loaded. In order to achieve the high speeds desired, the WCS is no longer treated as an output device. Instead the data and address information are transferred over the memory bus which can be used for high speed data transfers as opposed to the I/O bus which can be used only for lower speed transfers.

The invention can be described in more detail with the help of-the accompanying drawings wherein FIG. 1 shows a block diagram of a preferred embodiment of the micro-control storage configuration of the invention FIG. 2 shows a plurality of waveforms depicting the timing relationship thereof; and FIG. 3 shows a flow chart depicting the process required to provide data transfers in accordance with the invention.

As can be seen in the preferred embodiment of the invention in FrG. 1, the microcontrol storage system includes an appropriate memory for effective permanent storage of data, identified as a read-onlymemory (ROM) 10, and a writable control memory storage device, identified as WCS random-access-memory (RAM) 11. Data is supplied to RAM 11 for writing therein via WCS data register 12, such data being supplied from memory bus 13. Each data word supplied to register 12 is a 14-bit or 15-bit word, as described below, the word being supplied to the register 12 and clocked into the register by an appropriate WCS DATA CLK signal as shown. The address for the data word to be clocked into RAM 11 is supplied via WCS address register 14 (the adress information also being obtained from the memory bus 13), which address is suitably clocked into the register by a WCS ADDR CLK signal as shown. In the system described, three 14bit macro-words and one 15-bit macro-word make up the micro-instruction word, the 15-bit macro-word containing a parity bit.

For convenience the micro-instruction word is referred to as a 56-bit word comprising four 14-bit portions.

The RAM 11 comprises a 1024 X 57 memory unit so that a total of 1024 57bit micro-words can be stored therein.

Each of the macro-words from the main memory, as indicated above, includes 14bit portions of the 56-bit micro-words in WCS, four macro-words from main memory comprising a single complete micro-instruction word. The address which normally comprises 15 bits includes a four-bit field select portion which is supplied directly to the field select input of RAM 11 and is used to identify which 14-bit portion of the 56-bit micro-word is being stored. The remaining 11 bits include 10 bits for identifyng which of the 1024 word locations is to be used in RAM 11 and 1 bit which identifies the address as a WCS address. The use of four equal 14-bit macro-word portions, as contrasted with the three 16-bit words and one 8-bit word of the previous system, makes the layout of the storage components and interconnections on the micro-control storage board more advantageous in that such components can be positioned more closely on the board.

The data from WCS data register 12 is written into the RAM unit upon the application of a suitable WRITE WCS signal as shown. The other input to multiplexer unit 15 is the next micro-address for the microinstruction word which is to be supplied from the WCS memory units 10 or 11 during the read-out portion of the central processor timing cycle. Thus, the multiplexer either supplies the WCS address for data which is to be written into the RAM storage unit 11 (during the write portion of the cycle) or supplies the next microaddress for reading out the appropriate instruction from either ROM 10 or RAM 11 (during the read portion of the cycle). Cbntrol of the multiplexer operation is through ENABLE WCS signal, as shown. The micro-instruction word read from either the RAM or ROM unit during readout is supplied to the micro-instruction register 16, the clocking of such word into register 16 being controlled by the CPU CLK signal as shown.

The timing of the operation of the configuration shown in FIG. 1 can be best understood with reference to the timing waveforms of FIG. 2. As can be seen, waveform (A) represents the system clock signal and waveform (B) represents the CPU CLK signal as conventionally generated therefrom (for purposes of this explanation the inverse clock signal, i.e., the CPU CLK signal is depicted herein). Waveform (C) is the WCS ADDR signal and waveform (D) is the WCS ADDR CLK signal, while waveform (E) is the WCS DATA signal and waveform (F) is the WCS DATA CLK signal, Waveform (G) is the ENAB WCS signal and waveform H) is the WRITE WCS signal.

In a particular embodiment of the invention, as can be seen, the CPU CLK signal has a total time cycle of 200 nanoseconds.

In accordance with the operation of the invention, the WCS is always loaded, i.e., the data is always written into RAM unit 11 during a selected portion (e.g., the first half or first 100 nanosecond portion) of the CPU CLK cycle. As can be seen in FIG.

2, the address information is supplied from the memory bus 13 to the WCS address register 14 and is clocked into the register by the upward trailing edge of the WCS ADDR CLK signal (shown by the arrow thereon) effectively at the end of a CPU CLK cycle (shown by the downward edges of the CPU CLK signal which, as is understood, is the same time as the upward edges of the CPU CLK signal). The WCS ADDR CLK signal is generated by a combination of the CPU CLK and WCS ADDR signals at NAND gate 17.

'The data word is thereupon supplied from the memory bus 13 to the WCS data register 12 and is clocked into the data register by the upward trailing 'edge of the WCS DATA CLK signal (shown by the arrow thereon), again at the end of a CPU CLK cycle. The WCS DATA CLK signal is generated by a combination of the CU CLK and WCS DATA signals at NAND gate 18.

The data and address information are thereupon supplied to the RAM 11 when the ENAB WCS signal is low, which supplies the address via multiplexer 15, and when the WRITE WCS .is low which causes entry of the data at the correct location identified by the address and field select information. As can be seen, the next micoadress for reading out the next mico-instruction from the WCS is normally supplied to the ROM and RAM units at all times except when the ENAB WCS signal is low.

Thus, the next micro-instruction is available at the micro-instruction register 16 but is supplied therefrom only during the latter half of the CPU cycle as controlled by the CPU CLK signal.

Accordingly, the WCS is loaded during the positive portion of the CPU CLK signal and is read during the negative portion of the CPU CLK signal. While the loading operation of the writable control store unit and the reading operation of the next micro-instruction word therefrom are controlled to occur within separate selected portions of the CPU clock cycle, such timing of tht loading and reading can be set up independently of how the data and addresses are transferred in the system.

That is, insofar as it is controlled by the CPU clock signal as discussed above, the data could be supplied on the I/O bus for low-speed transfer as in the prior system but is preferably supplied on the memory bus for high speed transfer and the data is arranged to be transferred by block type loading techniques thereon, as described below.

A flow chart depicting the steps utilized in making such transfer in one preferred method of the invention is shown in FIG.

3. As set forth therein, the CPU -of the data processing system has available to it a number of accumulators for temporarily storing information required for the transfer operations. A first accumulator identified as AC1 is used to store the total count of entire block of micro-instruction words which are to be stored in WCS, each microinstruction word comprising four 14-bit data words stored in main memory. A second accumulator identified as AC2 is used to store the address in main memory (i.e., the source address) of the initial 14-bit data word of the first micro-instruction word. All of the 14-bit data words which make up the complete block of microinstruction words are stored in sequence in main memory so that each increment of the AC2 accumulator provides the next sequential main memory address. A third accumulator identified as AC3 is used to store the address in the WSC (i.e., the destination address) of the initial 14-bit data word of the first micro-instruction word. All of' the 14-bit data words are also stored in sequence in the WCS to make up the com plete block of micro-instruction words therein so that each increment of the AC3 accumulator provides the address of the 14-bit data word.

As can be seen in the flow chart of FIG.

3, the AC1, AC2 and AC3 accumulators are loaded with the total micro-instruction word count, the initial source address, and the initial destination address, respectively.

The initial destination address is transferred to the WCS address register and the initial data word is transferred from its source address in main memory to the WCS data register. The data word is then loaded into the WCS storage unit at the destination address and the address accumulators AC2 and AC3 are incremented. The next destination address (obtained by such increment) and the next data word (obtained at the incremented source address) are transferred and the next data word loaded. The AC2 and AC3 accumulators are again incremented. The process is thereby repeated three times until the four data words which form the first microinstruction word of the block are sequentially loaded at which time the AC1 accumulator is decremented.

The subsequent micro-instruction words are similarly loaded until the complete block of words has been written into the WCS, at which time the AC1 count is equal to zero. The operation is then completed and the system is ready for the next macroinstruction. Since the data words are originally sequentially loaded into the WCS the entire operation can be performed with a single macro-instruction which specifies the arguments of the accumulators which are used, i.e., the total micro-instruction word count, the initial source address and the initial destination address.

Such operation is in contrast with that of the previously described system of the above-referenced patent in which each data word requires separate macro-instructions to perform each of the transfer operations.

It requires a finite time to fetch and decode each separate macro-instruction. Further, each transfer is performed using the lower speed I/O bus, which further increases the overall time required to transfer the entire group of data words which make up the complete set of micro-instruction words to be stored. Moreover, the user must prepare an extensive and complicated program of macro-instructions therefor.

In the described embodiment of the invention, however, only a single macroinstruction specifying the total count and initial source and destinations addresses is required. Accordingly, the time required to fetch and decode an extensive set of instructions is avoided, only a single macroinstruction must be so fetched and decoded.

Further, the sequential block loading is accomplished by using the high speed memory bus which further reduces the overall time previously required. Moreover, the preparation of the single macroinstruction reduces the user's time considerably over that required for the preparation of the more complicated set of macro-instructions needed in the previously described system.

WHAT WE CLAIM IS: 1. A micro-programmable data processing system comprising a central processor unit utilizing a central processor unit clock signal, a read-write micro-instruction memory, a micro-instruction register for the micro-instruction being executed, and control logic operative to write micro-instructions in the memory during a first selected part of the clock signal cycle and to fetch microinstructions from the memory to the register during a second selected part of the clock signal cycle, in an arrangement such that a micro-instruction loaded into the register is available for execution substantially simultaneously with the writing of micro-instructions into the memory.

2. A data processing system in accordance with claim 1, wherein the said selected portions are different halves of the clock signal cycle.

3. A data processing system in accordance with claim 1 or 2, comprising a main memory and a memory bus for providing high speed data transfer thereon, and wherein the micro-instructions are transferred from the main memory to the microinstruction memory on the memory bus.

4. A data processing system in accordance with claim 1, 2 or 3, wherein the control logic includes a multiplexer means for supplying addresses for micro-instructions to be written in the micro-instruction memory only during selected ones of the first selected portions of the clock signal cycle for supplying addresses for read-out from the micro-instruction memory at all other times in the clock signal cycles.

5. A data processing system in accordance with any preceding claim, further including a permanent storage means storing further micro-instructions and capable of having micro-instructions read therefrom into the register.

6. A data processing system in accordance with claim 5, wherein the permanent storage means is a read-only-memory device.

7. A method of writing micro-instruction words into and reading micro-instruction words from a micro-instruction memory of a data processing system having a central processor unit utilizing a specified central processor unit clock signal, wherein the micro-instruction words are written in only during a first selected portion of each operating time cycle and are read out only during a second selected por

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **.

14-bit data word.

As can be seen in the flow chart of FIG.

3, the AC1, AC2 and AC3 accumulators are loaded with the total micro-instruction word count, the initial source address, and the initial destination address, respectively.

The initial destination address is transferred to the WCS address register and the initial data word is transferred from its source address in main memory to the WCS data register. The data word is then loaded into the WCS storage unit at the destination address and the address accumulators AC2 and AC3 are incremented. The next destination address (obtained by such increment) and the next data word (obtained at the incremented source address) are transferred and the next data word loaded. The AC2 and AC3 accumulators are again incremented. The process is thereby repeated three times until the four data words which form the first microinstruction word of the block are sequentially loaded at which time the AC1 accumulator is decremented.

The subsequent micro-instruction words are similarly loaded until the complete block of words has been written into the WCS, at which time the AC1 count is equal to zero. The operation is then completed and the system is ready for the next macroinstruction. Since the data words are originally sequentially loaded into the WCS the entire operation can be performed with a single macro-instruction which specifies the arguments of the accumulators which are used, i.e., the total micro-instruction word count, the initial source address and the initial destination address.

Such operation is in contrast with that of the previously described system of the above-referenced patent in which each data word requires separate macro-instructions to perform each of the transfer operations.

It requires a finite time to fetch and decode each separate macro-instruction. Further, each transfer is performed using the lower speed I/O bus, which further increases the overall time required to transfer the entire group of data words which make up the complete set of micro-instruction words to be stored. Moreover, the user must prepare an extensive and complicated program of macro-instructions therefor.

In the described embodiment of the invention, however, only a single macroinstruction specifying the total count and initial source and destinations addresses is required. Accordingly, the time required to fetch and decode an extensive set of instructions is avoided, only a single macroinstruction must be so fetched and decoded.

Further, the sequential block loading is accomplished by using the high speed memory bus which further reduces the overall time previously required. Moreover, the preparation of the single macroinstruction reduces the user's time considerably over that required for the preparation of the more complicated set of macro-instructions needed in the previously described system.

WHAT WE CLAIM IS: 1. A micro-programmable data processing system comprising a central processor unit utilizing a central processor unit clock signal, a read-write micro-instruction memory, a micro-instruction register for the micro-instruction being executed, and control logic operative to write micro-instructions in the memory during a first selected part of the clock signal cycle and to fetch microinstructions from the memory to the register during a second selected part of the clock signal cycle, in an arrangement such that a micro-instruction loaded into the register is available for execution substantially simultaneously with the writing of micro-instructions into the memory.
2. A data processing system in accordance with claim 1, wherein the said selected portions are different halves of the clock signal cycle.
3. A data processing system in accordance with claim 1 or 2, comprising a main memory and a memory bus for providing high speed data transfer thereon, and wherein the micro-instructions are transferred from the main memory to the microinstruction memory on the memory bus.
4. A data processing system in accordance with claim 1, 2 or 3, wherein the control logic includes a multiplexer means for supplying addresses for micro-instructions to be written in the micro-instruction memory only during selected ones of the first selected portions of the clock signal cycle for supplying addresses for read-out from the micro-instruction memory at all other times in the clock signal cycles.
5. A data processing system in accordance with any preceding claim, further including a permanent storage means storing further micro-instructions and capable of having micro-instructions read therefrom into the register.
6. A data processing system in accordance with claim 5, wherein the permanent storage means is a read-only-memory device.
7. A method of writing micro-instruction words into and reading micro-instruction words from a micro-instruction memory of a data processing system having a central processor unit utilizing a specified central processor unit clock signal, wherein the micro-instruction words are written in only during a first selected portion of each operating time cycle and are read out only during a second selected por

tion of each operating time cycle.
8. A method in accordance with Claim 7, wherein the storing of the microinstruction words includes the steps of storing the data words which form the microinstruction words sequentially in the main memory of the data processing system; moving the data words sequentially from the main memory to the micro-control storage system on a memory bus of the data processing system; and storing the sequentially moved data words in sequence in a writable control storage unit of the micro-control storage system to form the microinstruction words therein.
9. A method in accordance with Claim 8, for storing a plurality of microinstruction words wherein, the moving and storing includes the steps of: (1) storing a count of the total number of the plurality of microinstruction words in a first storage means; (2) storing the source address of the initial data word of the first microinstruction words of the plurality thereof in a second storage means; (3) Storing the destination address of the initial data word in a third storage means; (4) transferring the data word from the source address to the destination address; (5) incrementing the second and third storage means to the next sequential source and destination addresses respectively, of the second data word of the first microinstruction word; (6) repeating steps (4) and (5) for each data word of the first microinstruction word; (7) decrementing the count in the first storage means when said first microinstruction word has been stored; and (8) repeating steps (4) to (7) until all of the plurality of microinstruction words have been stored in the micro-control storage system.
10. A microprogrammable data processing system, substantially as hereinbefore described with reference to and as illustrated by the accompanying drawings.