JPH02149150A - Communication data buffer control system - Google Patents

Abstract

PURPOSE:To always increase the quantity of history information in communication between processors by recording a communication code in a communication code history memory as a history in the communication requiring a communication data buffer. CONSTITUTION:In a communication data buffer control system in an inter-processor communication system where data communication can be performed mutually between plural processors 1 and 2 via a common communication data buffer 30, a plural word storageable area sufficient for the storage of communication data of plural number of times of communication is provided as the communication data buffer 30. In the case of performing the communication interposing the communication data buffer 30, the update of an address register A21 on a transmission side 1 is performed at address modification circuits 13 and 14, and the update of an address register C22 on a reception side 2 is performed, and furthermore, when a communication destination is addressed to its own, the communication code is recorded as the history, and also, the communication data is read out of the communication data buffer 30 to a data control part 6, then, a prescribed processing is executed. In such a way, it is possible to always increase the quantity of the history information of the communication between the processors.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication data buffer control system, and more particularly to a communication data buffer 1 control system for inter-processor communication.

FIG. 4 is a diagram showing the system configuration of conventional inter-processor communication, in which the CPU 50 is on the sending side, the CPU 51 is on the receiving side, and communication data is exchanged via the communication data buffer 75 of the main memory 74. Ru.

When only a communication code is to be transmitted from the CPU 50, the communication code is generated in the control memory 56 and set in the transmission register A62 in the inter-processor communication transmission/reception control unit 52. The inter-processor communication transmission/reception control unit 52 transmits the communication code to all CPUs in the CPU.

The inter-processor communication transmission/reception control unit 53 of the CPtJ51 is a C
Receive the communication code sent from PU50 in register B6
5, and the comparator 73 compares the communication destination CPU number in the communication code with the contents of the register 67 in which the own CPU number is set, and determines whether or not the communication destination is the communication destination. If it is not the user, it is ignored, and if it is the user, an interrupt is generated in the communication code Wl history memory control circuit 61 and the data control unit 55 by the control signal 77 from the comparator 73.

In the communication code MW memory control circuit 61, the CPU
The communication code sent from 50 is sent to the communication code history memory 59 to the address indicated by the address signal 79 from 590 to 59.
Write in the order of 1 → 592 → 593 → 590 → . . . and leave it as a history.

In addition, the data control unit 55 executes a predetermined process based on the communication code from the CPU 50 under the control of the microprogram in the control memory 57, generates a reply communication code for the CPU 50 after completion, and generates a reply communication code for the interprocessor communication transmission/reception control unit 53. This is set in the transmission register 63 in the. The inter-processor communication transmission/reception control unit 53 transmits all CPs of the song.
Send the above reply communication code to U.

The inter-processor communication transmission/reception control unit 52 of the CPU 50 is
Set the reply communication code sent from U51 in the reception register 64, and set the communication destination CPtJPt in the communication code.
The comparator 72 compares the contents of the register 66 to which the own CPU number is set, and the control signal 76 generates an interrupt in the communication code history memory control circuit 60 and data control unit 54, and the reply communication code is sent. To the address indicated by the address signal 78 to the communication code history memory 58, 580→581→582→583→580→...
The writing history is saved in the order of...

In addition, the reply communication code is taken into the data control unit 54 by the microprogram control in the control memory 56, and the CPU, which had temporarily suspended processing by waiting for the reply communication,
50 sequentially executes the subsequent processing again.

When it is necessary to send not only a communication code but also communication data, the sending side uses the communication data buffer 75 on the storage device 74 under the control of the microprogram in the control memory 56.
The communication data is stored in advance by sending it from the data register A70 according to the address indicated by the address register A68, and after the storage is completed, the communication code generated by the data control unit 54 is sent to the transmission register A62 in the inter-processor communication transmission/reception control unit 52. Set to . The inter-processor communication transmission/reception control unit 52 transmits the communication code to all other CPUs.

The inter-processor communication transmission/reception control unit 53 of the CPU 51 on the receiving side sets the communication code sent from the CPU 50 in the reception register B65, and the communication destination CPU in the communication code
Register 6 where the number and your CPU number are set
The comparator 73 compares the contents of 7 with the contents of 7 to determine whether or not the communication destination is the user. If it is not the user, it is ignored, and if it is the user, the communication code is written to the communication code MW memory 59 and left as a write history in the same way as in the case of transmitting only the communication code described above.

In the data control unit 55, the CPU 50 uses a communication data buffer 75 on the main storage device 74 in which communication data is stored.
Then, under the microprogram control in the control unit 157, the address is read out to the data register B71 according to the address indicated by the address register B69, and a predetermined process is executed based on the communication code and the read communication data.
A reply communication code for 0 is generated and set in the transmission register 863 in the interprocessor communication transmission/reception control section 53. The inter-processor communication transmission/reception control unit 53 transmits the reply communication code to all other CPUs.

The CPU 50 receives the reply communication code and executes a predetermined process, as in the case of transmitting only the communication code described above.

In such a system, the communication data buffer 75 has a storage area of 4 words x 4 bytes, which is the communication data area for one time, so the communication codes for the latest four (
n=4) remains after HFM, but since address registers 68 and 69 of the communication data buffer always indicate a fixed address for communication data, if 8 uses the communication data buffer between subsequent processors, , the previous data will be rewritten, and only the latest communication data will remain as a history.

With the conventional method described above, if you want to check the history of communication between processors when a failure occurs, for example, only one piece of data remains, so if the previous data is the cause of the failure, If you do that, not only will it be difficult to analyze, but it will also take a lot of time to solve the problem.
Even in various debugging, there is a drawback that the efficiency is low due to the small amount of data.

Therefore, the present invention has been made to solve such drawbacks of the prior art, and its purpose is to make it possible to store communication data for multiple times so that communication between processors is always maintained. The object of the present invention is to provide a communication data buffer control method that can handle a large amount of historical information.

According to the present invention, there is provided a communication data buffer control method in an inter-processor communication system in which data communication is performed between a plurality of processors via a common communication data buffer, the method comprising: An area capable of storing a plurality of words sufficient to store communication data for a plurality of times is provided as a communication data buffer, and the address of the communication data buffer is sequentially variably controlled according to the number of words of the communication data. A characteristic communication data buffer control method is obtained.

K-Otori 1 Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In inter-processor communication, the CPU 2 is on the sending side, the CPU 2 is on the receiving side, and the communication data buffer 30 on the main storage device 29 has 16
It has a communication data area for words (one word is 4 bytes). Further, CPtJl and CPU2 are provided with an address register A21 and an address register C22, respectively, for storing the address of the communication data buffer, and are further provided with address modification circuits 13 and 14 that add the number of words of communication data to each register. .

When transmitting only the communication code from CPtJl, the data control unit 5 is controlled by the microprogram in the control memory 7.
A communication code is generated and set in the transmission register A15 in the interprocessor communication transmission/reception control section 3.

When sending only the communication code, set the control bit S of the communication code to "0".The 0 communication code is as shown in Figure 3, the communication destination CPU number 43, the communication source CPU number 44, and the communication command. 45, control bit 346, communication data 47 0 communication destination cpu number 44, communication source cp
The u number 45 has bits equal to the number of CPUs, and the communication destination and communication source CPtJ numbers are set by controlling the bits corresponding to each CPU.

When S=0, the data in the communication data field indicates the data itself used for communication, and when S=1, the control bit indicates the number of words of communication data stored in the communication data buffer on the main storage device. By setting S to "0", the contents of the address register A21 are not updated (see FIG. 2), and the interprocessor communication transmission/reception control section 3 transmits the above communication code to all CPUs in the memory.

The inter-processor communication transmission/reception control unit 4 of the CPU 2 is a CPU
Set the communication code sent from
Comparator 2 reads the contents of register 26 to which the number is set.
8 to determine whether the communication destination is itself, but regardless of this determination, since the control bit S is O, the contents of the address register C22 are not updated.

If it is not you, ignore it, if it is you, comparator 28
An interrupt is generated in the communication code history memory control circuit 12 and the data control unit 6 by the control signal 32 from the CPU. 100 → 101 → 10 to the address indicated by 34
Write in the order of 2 → 103 → 100 → . . . and leave it as a history.

In addition, in the data control unit 6, under the control of the microprogram in the control memory 8, a predetermined process is executed based on the communication code from CPtJl, and after completion, a reply communication code is generated for the CPU 1, and the interprocessor communication transmission/reception control unit Set it in the transmission register B16 in 4. The inter-processor communication transmission/reception control unit 4 transmits the reply communication code to all other CPUs.

The inter-processor communication transmission/reception control unit 3 of cptri is the CPU
Receive the reply communication code sent from 2 to register A.
17, the comparator 27 compares the communication destination CPU number in the communication code with the contents of the register 19 in which the own CPU number is set, and the control signal 31 causes the communication code history memory control circuit 11 and the data An interrupt occurs in the control unit 5, and the reply communication code is sent to the communication code history memory 9 at the address indicated by the address signal 33.
→ 91 → 92 → 93 → 90 → . . . are left in the order of writing history.

Also, under the control of the microprogram in the control memory 7, the reply communication code is taken into the data control unit 5, and CPtJl, which was waiting for the reply communication and temporarily interrupting the processing.
executes the subsequent processing in sequence again.

When it is necessary to send not only a communication code but also communication data, the sending side transfers the contents of the address register A21 in the interprocessor communication transmission/reception control unit 3 to the address register in the data control unit 5 under the control of the microprogram in the control memory 7. 823, and the communication data is sent from the data register A 25 and stored in the communication data buffer 30 on the main storage device 29 according to the address indicated by the address register B.

After the storage is completed, the data control section 5 generates a communication code with the number of words of the communication data stored in the communication data buffer and the control bit S set to 1'' (see FIG. 3), and the communication between the processors 18 and the transmission/reception control section 3. This control section 3 is set in the transmission register A15 of the C.
While transmitting the communication code to the PU, the address is added by the number of words of the communication data at the address modification port F#113, and the contents of the address register A are updated.

The interprocessor communication transmission/reception control unit 4 of the CPU 2 on the receiving side sets the communication code sent from cput in the reception register B18, and registers the communication destination CPU number in the communication code and the register 28 in which the own CPU number is set. The comparator 28 compares the contents with the communication destination to determine whether or not the communication destination is the communication destination, but regardless of this judgment, since the control bit S is 1, the address modification circuit 14 stores the communication data in the communication data buffer. Addresses are added by the number of words of communication data, and the address register C22 is updated.

If it is not the user, only the address register C22 is updated, but if it is the user, the communication code is left as a write history in the communication code history memory 10, as in the case where only the communication code is sent.

Also, in the data control unit 6, under the control of the microprogram in the control memory 8, the updated contents of the address register C22 are set in the address register D24, and the data is transferred from the communication data buffer on the main memory according to the address indicated by the address register D. The number of words is sequentially read into the data register B26, and predetermined processing is executed based on the communication code and the read communication data. After completion, a reply communication code is generated for the CPUI, and the transmission within the interprocessor communication transmission/reception control unit 4 is executed. Set in register B16. The inter-processor communication transmission/reception control unit 4 transmits the reply communication code to all other CPUs.

The CPUI receives the reply communication code and executes predetermined processing in the same way as in the case where only the communication code is transmitted as described above.

An example address modification circuit diagram is shown in FIG. 2, control bit S=
When it is 0, the selector 41 selects the lower 6 bits of the address register 42. In other words, the contents of the address register do not change, but when control bit S = t, 2 bits of "00" are added to the lower side of the number of words (4 bits) of communication data set in the communication data field, and 6
The result of adding the data expanded into bits and the lower 6 bits of the address register by the adder 40 is selected, and the contents of the address register are updated. Note that the carry of the adder is ignored.

The contents of the address register are updated according to the number of words of communication data, but the circuit configuration is such that calculations are made on the lower 6 bits of the address, and the other upper bits are fixed, so the address is 300 → 301 →
302→...30F→300→ are cyclic addresses that indicate the start address in each area.

As described above, in the case of communication that does not go through the communication data buffer on the main memory, the communication code generated by the sending side sets the control bit S in the communication code to "0", and the contents of address register A and address register C are set to 0. is not updated, and the receiving side leaves the communication code as a history only when the communication destination is itself, and in the case of communication via the communication data control unit, the sending side sets the control bit S to "1". ”, update address register A on the transmitting side in the address modification circuit, update address register C on the receiving side regardless of whether the communication destination is itself, and further update when the communication destination is itself. The communication code is recorded as a history, and the data control section 1 reads communication data from the communication data buffer and executes predetermined processing.

With this method, the latest 4 communication codes are left as a history for each communication, and the latest minimum to 16 communication data are left as a history for each communication using a communication data buffer.

As explained above, according to the present invention, when inter-processor communication requires communication data transfer on the main storage device, the communication code is stored as a history in the communication code history memory and the communication data is The address register is controlled according to the number of words in the m-word main memory, and the latest communication data can be stored in the communication data buffer on the m-word main memory as communication data for multiple times. This has the effect of being able to be kept as a history. Further, when communication does not require a communication data buffer, only the communication code is left as a history in the communication code history memory.

As a result, the latest n communication codes and the latest m words of communication data are efficiently stored as a history, which is an effective means of solving problems that require time and effort in various debugging and failure analysis. This has the effect of enabling early problem resolution.

[Brief explanation of the drawing]

Fig. 1 is a system block diagram of an embodiment of the present invention, Fig. 2 is a diagram showing an example of an address modification circuit, Fig. 3 is a diagram showing details of a communication code, and Fig. 4 is a diagram showing a prior art between processors. It is a communication system diagram. Explanation of symbols of main parts 1.2... CPU 3.4... Inter-processor communication transmission/reception control unit 5.
6...Data control unit 7.8...Control memory 9.10...Communication code history memory 13.14
... Address modification circuit 29 ... Main memory device 30 ... Communication data buffer Applicant: NEC Corporation (1 other person)

Claims (1)

[Claims] (1) A communication data buffer control method in an inter-processor communication system in which data is communicated between multiple processors via a common communication data buffer, wherein the communication data buffer is used for multiple times of communication. A communication data buffer control method characterized in that an area capable of storing a plurality of words sufficient to store data is provided, and addresses of the communication data buffer are sequentially and variably controlled according to the number of words of the communication data. .