JPH0588995A - Data communication system - Google Patents

Abstract

PURPOSE:To check a transfer error without requiring a data check signal line by transmitting check data at the end of block transfer and monitoring an error detected on the receiving side by a transfer error detector connected to a bus. CONSTITUTION:A data transmitting means 31 in a data processor 1 adds the number of '1's in transferred data at the end of block transfer and transmits the number of '0's and the number of '1's to a data storage device 2 or a peripheral control device (not shown) as check data. The device 2 receives the transmitted data by its data receiving means 32, adds the number of '0's and the number of '1's in the data, compares the added values with the transmitted check data to detect an error. At the time of detecting an error, a transfer error signal 5 is sent to the transfer error detector 4. The detector 5 detects which device generates the error based upon the signal 5 and issues an instruction reexecution signal 6.

Description

Detailed Description of the Invention

[0001]

The present invention is used for data communication in information processing. The present invention relates to a data communication system capable of performing accurate and efficient transfer in data communication that does not have a data check signal on an inter-device interface.

[0002]

2. Description of the Related Art Conventionally, in a data communication system which does not have a data check signal on an inter-device interface of this type, it is necessary to confirm the coincidence of transmission / reception data by some method after data transfer. On the other hand, a method in which the receiving side sends back the data and the sending side checks the data can be considered. Further, a method of performing SUM check of the received data on software, and a method of checking the predetermined code in the received data in places are conceivable.

Further, if a signal for checking parity or other data is added, even if an abnormality occurs in the data during transfer, a check function is provided, so that some countermeasure can be taken. However, the interface width becomes large, and this method cannot be used when the interface width cannot be increased structurally or in specifications.

[0004]

In the above-mentioned conventional data communication system, since there is no function of checking the data being transferred, when some abnormality occurs in the data during the transfer, the incorrect data is transferred as it is. There is also a fear that the data check method after transfer is not efficient and the overall data transfer performance is deteriorated.

The present invention solves such a problem. Even if the interface has no check signal, data check can be performed without changing the bus specification, and the data transfer performance is improved. The purpose is to provide a system that can.

[0006]

According to the present invention, a plurality of devices including a data processing device, a data storage device, and a peripheral control device are connected to one bus, and data is transferred between the devices via the bus. In a data communication system that performs transfer, when data is transmitted by block transfer to a device that is a transmission side, a data transmission unit that transmits check data at the end of the block transfer is provided, and the device that is the reception side transmits the data. It is characterized in that it comprises a data receiving means for receiving the check data transmitted by the means, and a transfer error detecting device for monitoring a transfer error signal from the data receiving means is connected to the bus.

The error signal monitoring means is sent from a receiving side device when one device is a transmitting side and simultaneously transfers data to a plurality of other receiving side devices by using block transfer. The data transmission means, including the error device identification means for taking in the transfer error signal and specifying the device which sent the error signal, and the instruction re-execution instruction means for sending the signal for block transfer again to the transmission side device. Is the first bit 0 that converts the content of the data to be transmitted every cycle into a binary number and detects the number of "1",
1 detection means, the first bit 0 and 1 addition means for adding and storing the detection results for all transmission data during block transfer, and using this as transmission check data, everything to be transmitted by block transfer Check data transmitting means for transmitting transmission check data immediately after the end of the data transfer, the data receiving means converts the content of the data received by one device every cycle into a binary number. Then, the second bit 0, 1 detecting means for detecting the number of "1" s, and the second bit 0 for adding the detection result to all the reception data during the block transfer, and making this the reception check data, Immediately after the 1 addition means and the reception of all the data to be received in the block transfer are finished,
Includes check data receiving means for receiving the transmission check data that has been continuously transferred, and check data comparing means for comparing the reception check data with the transmission check data received by block transfer and generating an error signal if they do not match. Is desirable.

[0008]

The data transmission means of the data transmission side device calculates and adds the number of "1" s of the data transmitted during the transfer at the end of the block transfer, and the number of 0s and 1s is used as the check data. Send to. The device on the data receiving side receives the transmitted data, detects the number of 0s and 1s of the data and adds them, and compares the transmitted check data with the check data of its own device to detect an error. When an error is detected, a transfer error signal is sent to the transfer error detection device,
The transfer error detection device detects in which device the error is detected according to the signal, and issues a re-execution instruction.

As a result, it is possible to perform efficient data communication in which the data content of the block data is guaranteed, and it is possible to check a data transfer error without requiring a data check signal. In addition, the interface width of the system can be reduced accordingly.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. 1 is a block diagram showing the overall configuration of an embodiment of the present invention,
FIG. 2 is a block diagram showing a detailed configuration of the embodiment of the present invention.

In the embodiment of the present invention, a plurality of devices including a data processing device 1, a data storage device 2, and a peripheral control device 3 are connected to one bus 100, and in this example, the data processing device 1 on the transmission side. In addition, when data is transmitted by block transfer, the data transmission means 31 for transmitting check data at the end of the block transfer is provided, and the check data transmitted by the data transmission means 31 is received by the data storage device 2 on the receiving side. The bus 10 is provided with the data receiving means 32.
A transfer error detecting device 4 for monitoring a transfer error signal from the data receiving means 32 is connected to 0.

The data transmitting means 31 converts the contents of the data to be transmitted every cycle into a binary number and detects the number of "1" s, the first bit 0, 1 detecting means 61, and all the blocks being transferred. Immediately after the transfer of all the data to be transmitted by the block transfer and the first bit 0, 1 addition means 63 which adds and saves the detection result for the transmission data of Check data transmitting means 62 for transmitting the transmission check data subsequently, and the data receiving means 32 converts the content of the data received by one device every cycle into a binary number, Second bit 0, 1 to detect the number
The detection means 64, the second bit 0 and 1 addition means 67 for adding the detection result to all the received data during the block transfer and using this as the reception check data, and all the data to be received in the block transfer Immediately after finishing the reception,
Check data receiving means 66 for receiving the transmission check data that has been continuously transferred, and check data comparing means 65 for comparing the reception check data with the transmission check data received by the block transfer and generating an error signal if they do not match. Including error signal monitoring means 60
In one, when one device as a transmitting side simultaneously transfers data to a plurality of other receiving devices by using block transfer, the transfer error signal sent from the receiving device is fetched, Error device identification means 68 for specifying the device that has sent the error signal, and instruction re-execution instruction means 6 for sending a signal to perform block transfer again to the transmission side device.
9 and 9 are included.

The data processing device 1 activates read transfer and write transfer using block transfer to the data storage device 2 and the peripheral control device 3.

Generally, block transfer means a method of transferring one block of information, that is, one block at a time. The block transfer here is a method in which the device that activates the transfer transfers the data of the subsequent address to the transferred device according to the information of the start address, and the transfer is performed in the first cycle for one block transfer. Only send the start address, not the address during subsequent transfers. The address strobe signal is active during the block transfer period, and unit data is transferred at the time when the data strobe signal shifts from the inactive state to the active state every cycle. The unit data means data transferred in one cycle during one block transfer.

On the side of the transferred device, after receiving the start address in the first cycle, this is held in the device,
At the time when the data strobe signal shifts from the inactive state to the active state, the address held internally is subtracted, and the data of the address corresponding to that is made valid. The above operation is continued until the address strobe signal becomes inactive.

The transfer error detection device 4 takes in the transfer error signal 5 from each device, identifies in which device the transfer error occurred, and sends an instruction re-execution signal 6 to the data processing device 1. After receiving the instruction re-execution signal 6, the data processing device 1 immediately performs block transfer again to the device which issued the transfer error signal.

Here, the operation in the write transfer using the block transfer from the data processing device 1 to the data storage device 2 will be described. FIG. 3 is a block diagram showing a configuration example of the data transmitting means 31 of the data processing device in the embodiment of the present invention. As for the structural relationship between FIG. 3 and FIG. 2, the register 11 and the SUM calculator 13 correspond to the first bit 0 and 1 detection means 61, and the adder circuit 14 corresponds to the first bit 0 and 1.
The register 16 corresponds to the adder 63, and the register 16 corresponds to the check data transmitter 62. A timing chart in the data transmitting means 31 is shown in FIG.

When the data transmission means 31 activates data transfer, the counter 10 receives the number of transfer data from the processor side in the data processing device 1. Then register 1
The transfer data from the processor side is input to 1. This timing is 20% on the timing chart shown in FIG.
It is part 1. The signal 12 for fetching the transfer data into the register 11 is generated each time the counter contents are decremented by the counter 10.

The data taken in the register 11 is output to the data bus 114 and the SUM calculator 13. SU
Every time the transfer data is output from the register 11, the M calculator 13 converts the transfer data into a binary number representation and calculates the number of “1” existing therein. In the adder circuit 14,
“1” for each transfer data calculated by the SUM calculator 13
The number of is added to one transfer unit.

When the block transfer is completed, the counter 10
The value within becomes 0 and the transfer end signal 15 is output. This transfer end signal 15 causes the addition circuit 14 to be added to the register 16.
The output 112 from is taken. When all the data transfer is completed, the output 112 from the adder circuit 14 becomes the number of “1” in the data sent in one block transfer. In the timing chart shown in FIG. 4, at the timing of 202, the sequence end signal 15 falls and the register 16 receives the SUMS data which is the transmission check data. The total data of "1" in one block transfer entered in the register 16 becomes the transmission check data.

The data selection circuit 17 uses the transfer end signal 15
Thus, the transmission check data is output to the data bus 115 in the last cycle of the block transfer. Therefore, the data transferred in one block transfer sequence (while the address strobe signal is active) is [block transferred block data] + [number of 1's in the block data transferred by block transfer ( Transmission check data)].

FIG. 5 is a block diagram showing an example of the structure of the data receiving means constituting the data storage device in the embodiment of the present invention. 5 and 2, the register 22, the register 23 and the SUM calculator 26 correspond to the second bit 0 and 1 detecting means 64, and the adder circuit 27 corresponds to the second bit 0 and 1. Corresponding to the adding means 67, the data direction switching means 24, the write signal generating means 21, the register 22 and the register 23 are included in the check data receiving means 6.
6, the register 25, the register 28, and the comparison circuit 29 correspond to the check data comparison unit 65. FIG. 6 shows a timing chart in the data receiving means 32.

After the start address is fetched from the address bus 126 into the counter 20 at the falling edge of the data strobe signal in the first cycle, the transfer data is fetched from the data bus 120 into the register 22 in sequence. The signal 124 for fetching the transfer data in the register 22 is the trailing edge of the data strobe signal indicating that the valid data has been transmitted for each cycle from the transmitter side. Signal 124
The transfer data fetched in the register 22 at the falling edge of is fetched in the register 23 at the next falling edge of the signal 124.

The transfer data taken in the register 23 is output to the data direction switching means 24. The data direction switching means 24 receives the transfer data by the sequence end signal 125 output from the write signal generating means 21 and passes through the path 121 to the memory side and the SUM calculator 26.
Output to or through path 122 to register 25
Decide whether to output to. The SUM calculator 26 performs the same operation as the SUM calculator 13 in FIG. The number of “1” for each transfer data output from the SUM calculator 26 is input to the adder circuit 27 to calculate the total number of “1” in one block transfer.

After the block data transfer in one block transfer is completed, the transmission check data is fetched into the register 22 in the last cycle of the block transfer.
This timing is shown at 60 in FIG.

When one block transfer is completed, an address strobe signal indicating that one data access sequence from the transmitter side is valid, which indicates that the block transfer sequence is in progress here. At a time point 61 shown in FIG. 6, the active state shifts to the negative state. This change is detected by the write signal generator 21 and the sequence end signal 125 is generated.

The register 23 has a sequence end signal 125.
Then, the transmission check data output from the register 22 is fetched and output to the data direction switching means 24. The data direction switching means 24 outputs the transmission check data to the register 25 through the path 122 in response to the sequence end signal 125. The register 25 fetches the transmission check data by the sequence end signal 125. Further, the register 28 uses the total data of "1" calculated by the adder circuit 27 as the reception check data and the data strobe signal 12
Capture with 4.

Finally, the comparison circuit 29 compares the transmission check data 128 and the reception check data 129 at the time when the sequence end signal is input, that is, at the timing of 62 shown in FIG. 127 is output. In this way, data transfer check is performed for each block transfer.

FIG. 7 shows a timing chart on the bus in the block transfer sequence of the data communication system according to the embodiment of the present invention described above. The transfer start address is
Data processing device 1 in the first cycle of the sequence
From DATA to DATA1 on the bus. After the second cycle, the address bus is not valid until the sequence ends. The effective range of the block transfer sequence is from the falling edge 51 of the address strobe signal to the rising edge 57 of the address strobe signal. Sent. At the falling edge 56 of the data strobe signal, SUMS, which is transmission check data, is transmitted to the data bus. Address strobe signal rising 57
Ends the block transfer sequence.

Although the description so far has been made on the write transfer using the block transfer from the data processing device 1 to the data storage device 2, the write transfer from the data processing device 1 to the peripheral control device 3 is similarly performed. Be seen.

Even in the simultaneous block write transfer from the data processing device 1 to the data storage device 2 and the peripheral control device 3, the operation for each individual device is similarly performed. However, when the peripheral control device 3 detects a transfer error at this time, the transfer error signal is transmitted to the transfer error detection device 4 through the transfer error signal line 5 shown in FIG. The transfer error detection device 4 judges that an error signal has come from the peripheral control device 3, and issues a block transfer restart command to the peripheral control device 3 to the data processing device 1.

In the read transfer using the block transfer from the data processing device 1 to the data storage device 2, the data receiving unit shown in FIG. 3 is connected to the data processing device 1 and the data transfer device 2 shown in FIG. The operation is the same as the case of the write transfer except that the transfer direction is changed by connecting the units.

[0033]

As described above, according to the present invention, it is possible to perform efficient data communication in which the data content of block data is assured, and a data transfer error can be achieved without the need of a signal line for checking parity or other data. Since it is possible to check, the interface width of the system can be designed to be small. Further, in the case of the specification that there is no check signal on the interface, there is an effect that the data can be checked without changing the specification of the bus.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of an embodiment of the present invention.

FIG. 3 is a block diagram showing a specific configuration example of a data transmission unit of the data processing device according to the embodiment of the present invention.

FIG. 4 is a timing chart showing the operation timing of the data transmitting means in the embodiment of the present invention.

FIG. 5 is a diagram showing a specific configuration example of a data receiving means of the data storage device in the embodiment of the present invention.

FIG. 6 is a timing chart showing the operation timing of the data receiving means in the embodiment of the present invention.

FIG. 7 is a timing chart showing signal timing on a bus when block transfer is used in the embodiment of the present invention.

[Explanation of symbols]

 1 Data Processing Device 2 Data Storage Device 3 Peripheral Control Device 4 Transfer Error Detection Device 5 Transfer Error Signal 6 Instruction Re-execution Signal 10, 20 Counter 11, 16, 22, 23, 25, 28 Register 13, 26 SUM Calculator 14, 27 adder circuit 17 data selection circuit 21 write signal generation means 24 data direction switching means 29 comparison circuit 31 data transmission means 32 data reception means 60 error signal monitoring means 61, 64 bits 0, 1 detection means 62 check data transmission means 63, 67 Bit 0, 1 addition means 65 check data comparison means 66 check data reception means 68 error device identification means 69 instruction re-execution instruction means 100 bus

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04L 1/16 7190-5K 5/00 8843-5K 12/40 29/14

Claims (3)

[Claims] 1. A data communication system in which a plurality of devices including a data processing device, a data storage device, and a peripheral control device are connected to one bus, and data is transferred between the devices via the bus. When transmitting data by block transfer to the device on the transmitting side, the data transmitting means for transmitting the check data at the end of the block transfer is provided, and the device on the receiving side receives the check data transmitted by the data transmitting means. And a transfer error detecting device for monitoring a transfer error signal from the data receiving unit is connected to the bus. 2. The error signal monitoring means is configured so that, when one device is a transmitting side and simultaneously transfers data to a plurality of other receiving devices by block transfer, 3. An error device identifying means for capturing the transferred transfer error signal and specifying the device which has sent the error signal, and an instruction re-execution instructing means for sending a signal for performing block transfer again to the transmitting side device. The described data communication system. 3. The data transmitting means converts the content of the data to be transmitted every cycle into a binary number and detects the number of "1" s, the first bit 0, 1 detecting means, and all of the block transfer operations. Immediately after the completion of the transfer of all the data to be transmitted by block transfer, and the first bit 0, 1 addition means that adds and saves the detection result for the transmission data of Check data transmitting means for transmitting transmission check data subsequently, wherein the data receiving means converts the content of the data received by one device every cycle into a binary number, and detects the number of "1". Second bit 0, 1 detecting means for adding, and second bit 0, 1 adding means for adding the detection result to all received data during block transfer and making this the reception check data Immediately after receiving all the data that should be received by block transfer, compare the check data receiving means that continuously receives the transmitted check data and the received check data with the transmission check data received by block transfer. 2. The data communication system according to claim 1, further comprising check data comparing means for generating an error signal if they do not match.