JPS603227B2 - Common bus control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a common bus control device for connecting a plurality of computers and the like to perform cooperative operations, and particularly relates to a small-scale system such as a microcomputer.

A conventional device of this type is shown in FIG.

In FIG. 1, la, lb, and lc are computers, 2 is a bus master that controls the common bus, 3 to 5 are REQ signals that request the use of the common bus, and 6 to 8 are ACK signals that permit the use of the common bus. 9 is a common bus line through which computers la, lb, and lc exchange information. Next, the operation will be explained.

When transmitting information via the common bus 9, only one computer must take initiative in using the common bus 9. That is, there may be two or more units on the signal receiving side, but if there is only one unit on the transmitting side, the signals will overlap and the common bus 9 cannot be used. For that reason, the first
As shown in the figure, when three computers request the use of the common bus 9 at the same time, it is necessary to decide the order in which the three computers use the common bus 9, and each computer 1 to 3 requests its use. REQ signals 3 to 5 are sent individually to the bus master 2. Bus master 2 uses an ACK signal (one of 6 to 8) that allows use only to the computer with the highest priority according to the predetermined priority order for simultaneous requests.
). The computer that has received the ACK signal uses the common bus 9 to exchange data with other computers. Conventional devices like this have the disadvantage that the number of REQ signal lines 3 to 5 and ACK signal lines 6 to 8 increases in proportion to the number of computers, and the circuit that determines priority for simultaneous requests is limited to the number of computers. It is necessary to decide according to the purpose of use.
It has the disadvantage that it is very complex to make it flexible enough to be applied in any case.

Furthermore, even if there is no need to prioritize, it is necessary to prioritize as a countermeasure against simultaneous requests.

In order to eliminate the above-mentioned drawbacks, this invention uses a simple bus master that does not increase the number of REQ and ACK signal lines in proportion to the number of computers and can be used even when there is no need to prioritize. This invention provides a common bus control device using a new method.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing the overall configuration of the common bus control device,
In the figure, 10a, 1ob, 10c, and 10d are computers that can exchange data through the common bus 9,
The common bus is controlled by a bus master 11 that accepts bus use requests from each computer and gives permission to use them, and its control lines 12, 13, and 14.

FIG. 3 is a diagram for explaining the operation of the bus master on the common bus line, and shows the relationship between the bus master 11 and one computer, that is, the bus master interface circuit 25 of the computer 10c in FIG. It shows.

The bus master 11 has the output of the clock generator 15 connected to the clock input of the counter 17 through the gate 16.
The output of the counter 17 is connected to the control lines 13 and 14, that is, TS
,,TS. Then, it enters the bus master interface circuit of each computer. Therefore, the control lines 13 and 14 are cyclically "1" while the counter 17 is clocked.
, "0" are repeated. The gate 16 receives a busy signal BSY from each computer indicating that the common bus 9 is in use.
12 outputs the output of the clock generator 15 to the counter 17.
This is a gate that prohibits entry. 18a and 18b are exclusive OR gates, 19 are AND gates, and these three gates make the TS and TSo signals predetermined signals (hereinafter referred to as unit numbers) for the own computer 10c. This circuit detects the common bus use request signal RE using its output signal 20 as a trigger.
When Q22 is “1”, recognition flip-flop ACK F
Set F21.

A signal 23 generated when the use of the common bus is finished is connected to the reset terminal of the ACKF/F, and its output negative signal is connected to the BSY signal 12. Figure 4 is the third
An example is shown in which data is transferred between computers using the common bus control device shown in the figure. This is an example where the computer 10c requests data from the computer 1ob, and 25 is the same as that shown in FIG.
The address signal 32 indicating a predetermined data address in the computer 10b is sent to the gate 31 by the GATE signal 24 of No. 5.
It is connected to the common bus 28 through. This address signal 32 is input to a decoder 35 in the computer 10b, which detects that the computer is its own computer, and outputs data 38 according to its contents to the common signal bus 29 through a gate 36. On the other hand, the gate 37 returns the contents of TS, , TSo as a CDR signal to the computer 10c in response to the READY signal 39 indicating that the data 38 is ready and the output of the decoder 35. The computer 10c is connected to a gate 33 in order to detect that it is its own unit number by a decoder 30 of the CDR signal, and to take in the contents of the data signal bus 29 into the computer using that signal. FIG. 5 is a diagram showing waveforms at various parts.

REQ, GATE, and CMP of 06C, TS, and TS are respectively 15, 14, 13, 22, 24, and 23 as shown in Figure 3.
ADD, DATA, and CDR are signals 28, 29, and 27 shown in FIG.

FIG. 6 shows an embodiment in which the bus master is made redundant, and in addition to the OSC 15 shown in FIG. 3, there is a spare OSC 40.

These two clocks are AND gate 4 1, 42, O
Pass through R Gate 43 and enter Gate 16. OR gate 43
The output clock is output if either gate 41 or 42 is output. clock generator O
SC. 15 is constantly monitored by a clock stop detection circuit 44, and the gates 41 and 42 are switched by the output thereof. The gate 16 is the same as the gate shown in FIG. 3, and its output goes into three counters 17a, 17b, and 17c, and the output is TS, , TSo, which uses a 2/3 selection circuit for each output bit of each counter. is output to the bus line as Next, the function and operation of this invention will be explained.

In general, common bus control devices can be broadly divided into two problems: competition for requests to use the common bus, and problems regarding data exchange methods. That is, in FIG. 2, 10a~
What to do when four computers in 10d issue requests to use the common bus at the same time, and how to transfer the desired data after the computer in 10a acquires the right to use the common bus. The question is whether First, the former will be explained with reference to FIG. To make the explanation easier to understand, the number of computers connected to the common bus is limited to four, and each computer is assigned a number from I0 to I3 as a unit number.

If there is no request to use the bus line from all the computers 10a to 10d, the BSY control signal on the BSY control line 12 is "0", so the gate 16 inputs the output of the clock generator to the counter 17 as it is. ing. As the counter 17, a 2-bit binary counter that can count from 0 to 3 can be used. Of the output of the counter? Bit TSo,? If a bit is connected to TS, then TS and TSo are decoded, and 0 to 3 are cyclically repeated. If the unit number of the computer 10c is 2, when TS, = "1" and TSo = "0", the signal 20' will be "1" and if the REQ signal 22 is "1", the ACKF/ Set F21.

If there is no REQ signal 22, ACKF/F21 will not be set, and TS, and TSo will be set at the next clock.
So=1 and the signal 20 becomes "0". At this time, even if the REQ signal 22 comes, the ACK F/F is not set. When there is a REQ signal and the ACK F/F is set, the BSY control signal becomes “1” and the bus master gate 1
6 is closed, so the counter remains as it is.

In other words, since it stops with the TS and TSo signal states when REQ is detected, the ACKF/F of other unit numbers
becomes impossible to set. Therefore, setting the ACK F/F means that the own computer can use the common bus. When the computer 10c finishes using the bus bar, it generates a CM circle signal 23 and ACK F/F.
Reset.

As a result, the gate 16 becomes a link, the counter 17 starts operating, and cyclically adds a signal to the trigger terminal of the ACK F/F in the order of unit numbers I3, I0, I1, I2. FIG. 4 shows an embodiment of data exchange using a common bus, using the bus master interface circuit 25 shown in FIG.

The bus master interface circuit 25 is connected to three buses TS, , TSo, and BSY as a common bus, and as mentioned above, the computer 10c can obtain the right to use the bus, and the GATE signal 24 at that time allows the computer 10c to obtain the right to use the bus. The side address signal 32 is passed through the gate 31 to the address bus ADD28.
Output to. Usually, there are a plurality of address signal lines, and they are composed of a unit number connected to the common bus DATA 29 and a data address in the other unit. If an address signal is now being sent from 10c to the computer 1ob, the decoder 35 of the computer 10b decodes the unit number and data address and outputs the necessary data 38 to the common bus DATA 29. Also, when the data 38 is ready, a READY signal 39 is generated, and the current TS,
, TSo26 is returned to the computer 10c as a transmission line CDR signal 27. In this way, the computer 10b can be operated without synchronizing with the computer 10c.
When the CDR signal 27 is received by the computer 10c and decoded by the decoder 30, it can be detected that it is the same as its own unit number, and it can be seen that there has been a response to its own transfer command. That is, the common bus DAT
It is known that the data commanded to A29 is being output.
Therefore, using the output signal of the decoder 30 as a trigger, the gate 3
3 can be opened to obtain data 34. calculator 10c
After storing the data 34, a CMP signal is generated to complete the use of the common bus 29, the ACKF/F of the bus master interface circuit is reset, and the common bus 29 is transferred to another unit. Even if a common bus is to be used subsequently, it is necessary to wait until TS, . . . TSo become its own unit number again. Such a control device is effective in slow-speed computers such as microcomputers because other machine cycles such as memory access are much longer than the dedicated time of the common bus line actually used. Also, the frequency of OSC15 is usually 10
Since approximately the female HZ to IMHZ is used, it is considered that there is almost no effect even if the detection goes through one round as described above. FIG. 5 shows the above operation in a time chart. FIG. 6 shows an example of a simplified bus master with a redundant circuit, in which the OSC 15 and counter 17 are made redundant. In the figure, the clock stop detection circuit 44 is operated by the OS.
While the oscillation of C, 15 is stopped and the OSC, 15 is oscillating, the gate 41 is opened by the inverter 45, and the gate 41 is opened.
The port 42 is closed. If the oscillations of 06C and 15 stop, the stop detection circuit 44 is activated, and the gate 41 is opened and the gate 42 is opened, so that the oscillation of the OSC 240 is output. If the counters 17a and 170017c are simple binary counters, highly reliable counters can be easily created using the 3-choice-2 circuit 46.

However, the counters 17a, 17b, and 17c must include a circuit that synchronizes at a certain count value, but the method for doing so is not the purpose of the present invention and will therefore be omitted here. Note that in the above embodiment, TS,,TS
o has two control lines 13 and 14, but if you increase the number of bits of the counter 17 by increasing the number of control lines 13 and 14 to two or more, the maximum number of units that can be connected to the common signal bus is 2n (n = TSo, TS,
It can be increased at a rate of (number of...). or,
In FIG. 4, the CDR signals 27 are TSo, TS. The contents of 26 were used by the gate 37, but the same result can be obtained by sending a special signal line from the computer 10c to the computer 10c at the same time as outputting the address signal separately and using the contents instead of TS, , TSo. You can get the effect. Furthermore, although FIG. 6 shows the oscillator 15 and counter 17 made redundant, it is natural that each circuit including the gate circuit 16 can be made redundant. The counter 17 is not limited to a binary counter, and may be any other means that can achieve the same effect.

In the above explanation, each unit starts from the continuation of the current value of the counter 7 by releasing the AND gate 16 when the use of the common bus is completed, but the counter is reset when the Y signal 12 falls. For example, the counter will start again from the initial value.

If you do this, it will always have the initial value (normal output is 00)
will have priority in bus competition, and units with unit numbers that have large values in the counter output will have the lowest priority.
It is possible to control the common bus line with priority. This invention has the following effects. '11 In the system using a bus master, the number of devices connected to the common bus is up to 2n, where n is the number of lines connecting the bus master and each computer (the number of TS, , TSo in the above example). This makes it possible to reduce the number of wires.

For example, if n=4, up to 16 devices are possible. '21
Since it can be configured with a simple bus master and interface, the reliability of the common bus can be improved.

'3} Since the bus master is simple, a redundant circuit can be provided, making it even more reliable.

[Brief explanation of drawings]

FIG. 1 is a conventional common bus control device, FIG. 2 is a diagram showing the overall configuration of a common bus control device according to the present invention, FIG. 3 is a configuration diagram of a common bus control device according to the present invention, and FIG. The figure shows an apparatus for transferring data using the control device of FIG. 3 according to an embodiment of the present invention, FIG. 5 is an explanatory diagram of waveforms in each part of FIGS. This is an example of redundancy. In the figure, 9, 29 are common bus lines, 10a, 10b, 1
0c, 10d are calculators, 12 is a busy line, 13, 14,
26 is a control line, 15 is an oscillator, 16 is a gate circuit, 17
, 17a, 17b, and 17c are counters, 21 is a recognition circuit such as a recognition flip-flop circuit, 22 is a common bus use request signal, and 25 is a bus master interface circuit of the computer. In each figure, the same reference numerals indicate the same or corresponding parts. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. A counter that controls the use of a common bus line commonly connected to a plurality of computers and serving as a path for information transmission by the computers, which encodes and outputs logic signals on n control lines at least in 2n cycles; A detection circuit provided in each computer decodes the logic signals of all the control lines and outputs an output when it matches its own predetermined value, and the output of this detection circuit and the use from the computer equipped with the detection circuit to the common bus line. A recognition circuit that outputs an output when there is a request signal, first and second gate circuits that stop counting of the counter according to the output of the recognition circuit, and first and second gate circuits that supply clock signals to each of the gate circuits.
The clock generator detects the presence or absence of the output of the first clock generator, operates when the first clock generator stops oscillating, and supplies its output to the second gate circuit, and also supplies the output to the second gate circuit via the inverter. A control device for a common bus line, comprising a clock stop detection circuit for supplying a clock to the first gate circuit, and allowing use of the common bus line by a computer provided with the recognition circuit at the time of output from the recognition circuit.