JP3807616B2 - Microcomputer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microcomputer, for example, a technique effective for use in an interrupt function in a microcomputer and its peripheral controller.
[0002]
[Prior art]
A conventional microcomputer has a built-in peripheral function and a function of accepting an interrupt from an external device, and the acceptance priority and the interrupt from the peripheral function are defined in detail (publicly available). An example of a microcomputer having such an interrupt function is “Hitachi Single Chip Computer H8 / 500 Series Programming Manual: ADJ-602-022” issued by Hitachi, Ltd. When designing a system using multiple microcomputers, use the serial communication function built into the single-chip microcomputer, or configure the general-purpose port as a parallel handshake port according to the original specification, and communicate between the microprocessors. And synchronize instruction units.
[0003]
[Problems to be solved by the invention]
The inventor of the present application configures a system that performs a series of data processing by making full use of a plurality of microcomputers (CPUs), and specializes in a master CPU that controls the entire system and some control functions, or In order to synchronize instruction units with a slave CPU provided to improve the performance of special functions, a communication control system with good responsiveness using an interrupt signal was examined.
[0004]
In this case, when the slave CPU receives a control command or an operation start trigger from the master CPU, the slave CPU starts a control process assigned to itself, and immediately notifies the master CPU when the process ends and operates. To complete. At that time, if the master CPU manages a plurality of slave CPUs, it is necessary to know which slave CPU has completed which task and in what state.
[0005]
The conventional interrupt method is not designed for a high-performance system that makes full use of multiple microcomputers, and is designed to focus on accepting interrupts. The idea of generating is not made. Therefore, when constructing a distributed control type system using a plurality of microcomputers, serial communication or a general-purpose parallel port is used as described above. However, in the former serial communication, communication between relatively remote CPUs has a small number of wires and is resistant to noise, but a large amount of information can be transmitted / received in a short time and responsiveness is required. Not suitable for the system. The latter general-purpose parallel port is difficult to standardize because it is configured according to the function of the CPU used and the user specifications, and it is not suitable for cost reduction and miniaturization because it requires external parts. .
[0006]
In a data processing system with high performance, an 8 / 16-bit single-chip microcomputer is frequently used, and a real-time OS is generally used in distributed control. However, as the performance of the system becomes higher, the demands are increasing. Therefore, it has been considered to synchronize the master CPU and the slave CPU in units of instructions while improving the responsiveness using an interrupt signal.
[0007]
An object of the present invention is to provide a microcomputer having an interrupt function with improved versatility and responsiveness.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, there is a microcomputer capable of performing a series of task processing by inputting a predetermined instruction from an external device, a control arithmetic unit that interprets and executes the instruction, and interrupt information corresponding to the control arithmetic unit interrupt register for storing a interrupt generation control interrupt condition logic that sets an interrupt generation condition for outputting an interrupt signal to the external device is accessible by both the microcomputer and the external device itself Part.
[0009]
According to the above-described means, when a distributed control type system is adopted, a system having good versatility and responsiveness can be easily constructed by adopting the microcomputer.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a block diagram of an embodiment of an interrupt signal generation unit provided corresponding to a control arithmetic processing unit in the data processing apparatus according to the present invention. The data processing device of this embodiment is not particularly limited, but is directed to a slave CPU (microcomputer).
[0011]
The interrupt signal generator is provided corresponding to the control arithmetic unit of the slave CPU, and is provided separately from the conventional publicly available interrupt circuit.
The interrupt generation unit is connected to the control arithmetic unit and the like via an internal bus of the slave CPU, and is configured to be accessible to the inside via an external bus from an external device including an external master CPU. An interrupt signal (IRQ) is output to an external device including an external mask CPU.
[0012]
The interrupt generation control section is roughly an interrupt register having an arbitrary bit length (n bits) for writing interrupt information, and an interrupt condition logic circuit section (Gate etc.) for setting (determining) the conditions for generating an interrupt signal. And a mask register that permits / prohibits the output of the interrupt signal regardless of the establishment of the condition.
[0013]
The slave CPU uses the interrupt generation control unit to report the end of a series of tasks and the situation at the end of the series to the external device including the master CPU, or the situation that occurs during the series of tasks. An interrupt signal (IRQ) is output. The procedure until the interrupt signal is output is as follows.
[0014]
(1) In the initial state of the slave CPU, an interrupt signal (IRQ) is not output from the contents of the interrupt register and the mask register due to a reset signal when the power is turned on.
[0015]
{Circle around (2)} The slave CPU starts operation upon receiving a command for processing a series of tasks from an external device including the master CPU by some means.
[0016]
(3) The slave CPU writes the task completion status and the like to the interrupt register via the internal bus when the series of task processing is completed.
[0017]
(4) The contents written in the interrupt register are input to the interrupt condition logic unit, and the interrupt condition is satisfied in the mask register only when the bit sequence (data code) satisfies the interrupt generation condition. A signal indicating that this has occurred is output. The sequence (data code) that satisfies the interrupt generation condition is, for example, a data code other than the data code written in the initial state described in (1), an arbitrary data code, It is also a collection of them.
[0018]
In the interrupt condition logic circuit section that determines the conditions for generating an interrupt, these conditional expressions are fixedly configured by hardware such as a logic gate (Gate), or registers and latch circuits connected to the internal bus etc. in the logic gate By combining programmable circuits and elements, the conditional expressions can be changed statically and dynamically according to the user's wishes. A signal indicating that the interrupt condition output from the interrupt condition logic circuit unit input to the mask register is satisfied can cause an external device including the master CPU to output an interrupt signal (IRQ) depending on the state of the mask register. Or masked (output prohibited).
[0019]
(5) When an interrupt signal (IRQ) is output from the slave CPU, the external device including the master CPU receives the interrupt signal (IRQ) immediately or when it can move to processing for the interrupt signal ( Routine).
[0020]
In an interrupt processing task (routine) performed by an external device including the master CPU, the external device including the master CPU interrupts the reason why the interrupt signal (IRQ) from the slave CPU is output via the external bus. It knows by reading the contents of the register and executes an appropriate interrupt processing task (routine) based on the information. At that time, for example, the data code indicating the task that has been executed, the status of the slave CPU at the time of task completion, the task result (data, etc.), the completion code or the error code at the time of completion are written in the interrupt register. It has been.
[0021]
(6) After the external device including the master CPU reads the contents of the interrupt register during the interrupt processing task, the output of the interrupt signal (IRQ) to the external device including the master CPU is stopped, and preferably to the slave CPU. It is desirable to output an interrupt response signal notifying that an external device including the master CPU is executing an interrupt processing task. Thereby, it is possible to improve the reliability of control in the system having the multi-CPU configuration as described above.
[0022]
Regarding the method of stopping the output of the interrupt signal (IRQ), after an external device including the master CPU reads the contents of the interrupt register, a data code that does not generate an interrupt signal (IRQ) via the external bus is provided to the interrupt register. Write. In place of this configuration, although not shown in the figure, the slave CPU detects that the external device including the master CPU has read the contents of the interrupt register, and this detection signal automatically sends an interrupt signal (IRQ) to the interrupt register. A data code that does not occur may be written or reset to an initial state. It is also possible to simply stop the output of the interrupt signal (IRQ) by performing the same concept process for the mask register.
[0023]
The method for the output of the interrupt response signal, by writing a data code as a response via the external bus external device to the interrupt register including a master CPU, similar to the case of generating an interrupt signal (IRQ) The signal processing is performed in the interrupt condition logic circuit unit. Alternatively, although not shown, a memory such as a register or a latch circuit determines whether or not to output an interrupt response signal that can be accessed (written / read) by an external device including the master CPU in the interrupt condition logic circuit unit via the external bus. It is good also as a structure which provides a means.
[0024]
(7) Regarding the interrupt condition logic circuit section, (4) describes that the slave CPU can determine and change the output condition of the interrupt signal (IRQ) by the program, but the interrupt signal (IRQ) output condition is not necessarily all There are cases where the external device including the master CPU is not in a condition that requires interrupt acceptance. In this case, an external device including the master CPU needs to be able to access (write / read / change) the interrupt condition logic circuit unit.
[0025]
As for the state of the mask register, the external device including the master CPU is not always in a state where it can always accept the interrupt signal (IRQ), and thus the mask register is also accessed (write / read / change). Be made possible.
[0026]
FIG. 2 is a block diagram showing another embodiment of the interrupt signal generator provided corresponding to the control arithmetic processor in the data processor according to the present invention.
In the embodiment of FIG. 1, the interrupt register is illustratively described as transmitting one factor data code in the output of the interrupt signal (IRQ) from the slave CPU to the external device including the master CPU.
[0027]
In this embodiment, a mask register is provided between the interrupt register and the interrupt condition logic circuit unit. With this mask register, multiple cause data codes can be written at the same time in the interrupt register, in other words, multiple cause data codes can be set, or commentary data codes that are not directly related to the cause (A similar function can be realized if all the interrupt registers are not input to or influenced by the interrupt condition logic circuit section).
[0028]
The configuration of the mask register is not explicitly shown in the figure, but the mask register does not have to have bits corresponding to all bits of the interrupt register, and can be arbitrarily configured according to the system specifications.
[0029]
FIG. 3 shows a logic circuit diagram of an embodiment of the interrupt condition logic circuit unit. In this embodiment, a NAND (NAND) gate circuit that receives the data code of the interrupt register is used to constitute a fixed circuit. That is, in the embodiment shown in the figure, when all the n bits of the interrupt register become logic 1, a low level interrupt signal is generated by the NAND gate circuit.
[0030]
FIG. 4 shows a logic circuit diagram of another embodiment of the interrupt condition logic circuit section. In this embodiment, the data code of the interrupt register is input to a NAND gate circuit that generates an interrupt signal through a gate circuit controlled by a flip-flop (F / F). Since the selective output of the data code of the interrupt register can be controlled by writing to the flip-flop (F / F), the interrupt condition logic can be made programmable.
[0031]
The actual system application is not limited to the embodiment shown in FIG. 3 and FIG. 4, and various methods for implementing an interrupt condition logic circuit can be adopted in accordance with the system entity. is there.
[0032]
FIG. 5 is a schematic block diagram showing an embodiment of a data processing system using the data processing apparatus according to the present invention.
In this embodiment, a system that performs a series of data processing using a plurality of microcomputers (CPUs), specializes in a master CPU and a part of control functions for controlling the entire system, or special functions with high performance. It is composed of a plurality of slave CPUs 0 and CPU 1 provided for the purpose. The other peripheral controllers are omitted because they are equivalent to the slave CPU0 or CPU1. Memory devices and the like are omitted because they are not directly related to the present invention.
[0033]
Each of the slave CPU0 and CPU1 has an interrupt generation control unit as in the embodiment of FIG. 1 or FIG. In the figure, an interrupt register and a gate circuit Gate are exemplarily shown on behalf of the interrupt generation control unit.
[0034]
The master CPU has a slave CPU0 and interrupt input terminal IRQ-in0 corresponding to CPU1 and IRQ-in1. The master CPU instructs selection of the slave CPU0 and CPU1 by addressing. In other words, the decoder decodes the address information from the master CPU, decodes the access to the slave CPU0 or CPU1, generates a selection signal CS, selects the slave CPU0 or CPU1, and sends a command or the like via the data bus. To do. Such a selection operation can be performed in the same manner as the selection operation for a peripheral device such as a memory device when viewed from the master CPU side.
[0035]
The starting method from the master CPU to the slave CPU 0 or CPU 1 or the like may be performed by a dedicated control signal line or the like in addition to the above address designation and command transmission via the data bus.
[0036]
The generation of an interrupt from the slave CPU0, CPU1 side to the master CPU and the corresponding response operation of the master CPU are the same as in the description of FIG.
[0037]
The effects obtained from the above embodiment are as follows. That is,
(1) An interrupt generation control unit comprising an interrupt register having an arbitrary bit length and an interrupt condition logic unit is provided in correspondence with a control arithmetic processing unit that interprets and executes instructions constituting the microcomputer, and transmits interrupt signals to other devices. By enabling the generation and reading of the contents of the interrupt register, other devices that accept the interrupt can read the contents of the interrupt register using data communication means such as a bus. Therefore, it is possible to quickly know the meaning of the occurrence of the interrupt and the communication information in the device that has accepted the interrupt.
[0038]
(2) According to (1) above, by adding an interrupt generation control unit to a microcomputer that has already been developed, a data processing system that performs a series of controls by using a plurality of microcomputers (CPUs) is configured. When synchronizing instruction units between a master CPU that is in charge of overall system control and a part of the control functions or a slave CPU that is provided to improve the performance of special functions. Since a communication system with good responsiveness can be easily realized using the above, an effect of realizing high-speed interrupt responsiveness between the master CPU and slave CPU under real-time OS control can be obtained even in distributed control.
[0039]
The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the slave CPU provided with the interrupt generation control unit may be anything as long as it has a micro control function. The interrupt condition logic unit may have n systems of interrupt registers so that a large amount of additional information can be delivered, or may be managed independently for each task. It is also possible to use an electrically writable programmable memory element to allow the user himself to set the interrupt condition logic.
The present invention can be widely used in data processing apparatuses.
[0040]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. When a distributed control system is employed, a system with good versatility and responsiveness can be easily constructed by employing the above-described microcomputer.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of an interrupt signal generating unit provided corresponding to a control arithmetic processing unit of a data processing apparatus according to the present invention;
FIG. 2 is a block diagram showing another embodiment of the interrupt signal generating unit provided corresponding to the control arithmetic processing unit of the data processing apparatus according to the present invention;
FIG. 3 is a logic circuit diagram showing an embodiment of an interrupt condition logic circuit provided in the interrupt signal generator.
FIG. 4 is a logic circuit diagram showing another embodiment of the interrupt condition logic circuit provided in the interrupt signal generator.
FIG. 5 is a schematic block diagram showing an embodiment of a data processing system using the data processing apparatus according to the present invention.
[Explanation of symbols]
IRQ: Interrupt signal, F / F: Flip-flop.

Claims (4)

In a microcomputer capable of performing a series of task processing by inputting a predetermined instruction from an external device,
The microcomputer is
A control operation unit for interpreting and executing the predetermined instruction;
An interrupt generation control unit including an interrupt register provided corresponding to the control operation unit and an interrupt condition logic unit for setting an interrupt generation condition for outputting an interrupt signal to the external device;
The interrupt register is composed of a plurality of bits, and is configured to store a plurality of interrupt factors including information to be transmitted to the external device.
Said interrupt condition logic unit is to have a mask register having a number of bits corresponding to the number of bits representing the interrupt condition stored in said interrupt register further configured to be accessed by both the microcomputer and the external device,
The mask register can be set to permit or prohibit the output of the interrupt signal for each of the plurality of interrupt factors.
The interrupt generation control unit can output an interrupt signal to the external device when the bit sequence indicating the interrupt condition stored in the interrupt register satisfies the interrupt condition according to the state of the mask register. microcomputer, characterized in that. In claim 1,
2. The microcomputer according to claim 1, wherein the access includes writing / reading / modifying an interrupt register and a mask register included in the interrupt condition logic unit. In claim 1 or 2,
The microcomputer, wherein the interrupt condition logic unit includes an interrupt condition logic circuit unit. In any one of Claim 1 to 3,
The microcomputer detects that the external device has read the contents of the interrupt register, and sets the interrupt register to an initial state or writes a data code that does not generate an interrupt to the interrupt register. Microcomputer.

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