JPH09167117A - Microcomputer and real time system using the microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To immediately detect the destruction of a stack area, to prevent secondary and ternary faults, to improve debugging efficiency and to reduce man-hour in the debugging of a real time system. SOLUTION: In the system being a single chip microcomputer, a central processing unit is provided with an instruction prefetch/decoding unit 1, a control unit 2, an arithmetic unit 3, a stack area abnormality detection unit having a stack area abnormality detection function and an input/output control unit 5. An address register for setting the highest address of an area becoming an object for destruction detection and a status register for reflecting the presence or absence of the occurrence of overflow from the setting address to an upper part are provided in the stack abnormality detection unit 4. When a stack pointer shows a value upper than the value of the address register, the status register is automatically set and the destruction of the stack area owing to overflow is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer technology, and a microcomputer suitable for preventing secondary and tertiary failures due to stack destruction in software development, especially debugging of a real-time multitasking system, and a microcomputer thereof. The present invention relates to a technique effectively applied to a real-time system using.

[0002]

2. Description of the Related Art For example, according to a study by the inventor, in a real-time multitasking OS (operating system) using a computer without a memory management unit, a stack area is used together with software or hardware interrupts. A technology that enables detection of stack area destruction due to the overflow of

A technique relating to such stack area destruction is, for example, January 20, 1987,
It is described in "Information Processing Examination Course Hardware Knowledge" published by Ohmsha Co., Ltd., such as the computer control methods of P65 to P110.

[0004]

By the way, in the above-mentioned real-time multitasking OS technology, detection of stack area destruction is not impossible, but discontinuous memory allocation is indispensable, and the target purpose is In most cases, unnecessary unrelated procedures are required, or even if they can be detected, they do not lead to the detection of a direct failure, which is considered unrealistic.

In the real-time multi-task system, destruction or overflow of a stack area of a task or an interrupt handler causes another task,
The stack area such as the interrupt handler is destroyed,
When the work area of the OS or the application is destroyed, the task or interrupt handler having the destroyed stack does not always operate immediately, and the failure due to the stack destruction cannot be found immediately.

Therefore, early detection of stack area destruction is difficult, and secondary and tertiary failures occur due to this failure, which leads to malfunction of the program. In addition, even in debugging, if a secondary or tertiary failure occurs, it may take a great deal of time to investigate the root cause.

That is, in software development, especially in debugging of a real-time multitasking system, destruction of the stack area or overflow of the stack area leads to secondary and tertiary failures, and a great deal of labor and cost are spent for investigating the cause of the failure. Can be considered.

Therefore, an object of the present invention is to easily solve the above problems, to immediately detect the destruction of the stack area in the debugging of a real-time system, and to prevent the secondary and tertiary failures caused thereby. Another object of the present invention is to provide a microcomputer capable of improving the debugging efficiency of the real-time system and reducing the number of steps, and a real-time system using the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the microcomputer of the present invention is applied to a microcomputer having a central processing unit and its peripheral devices, and the central processing unit determines whether the value of the stack pointer is compared with a predetermined address value. The stack area abnormality detecting means for detecting the overflow of the stack area is incorporated.

Specifically, as the control register of the stack area abnormality detecting means, a first register for setting the uppermost address of the area to be detected for destruction, and the presence / absence of overflow from the set address to the upper side are reflected. A second register is provided, and after detecting an overflow,
A third register for setting whether or not to generate an interrupt is provided.

Thus, for example, the value of the third register is set to "1" to enable the detection of the overflow of the stack area. At this time, when the stack pointer indicates the upper part of the content of the first register, The value of the register 2 can be automatically set to "1", and at the same time, an interrupt can be generated.

Further, the real-time system of the present invention is
The microcomputer is used, and the microcomputer is operated by using a system or application program, such as a real-time OS, in which processing time is important.

Therefore, in the debugging of the microcomputer and the real time system, the overflow of the stack area can be detected, and the secondary and tertiary failures due to the stack area destruction can be prevented. In addition, it is possible to improve the debugging efficiency of the real-time system by preventing the secondary and tertiary failures.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a microcomputer according to the first embodiment of the present invention, FIG. 2 is a block diagram showing a central processing unit in the first embodiment, and FIG. 3 is a stack abnormality. FIG. 4 is an explanatory view showing a control register in the detection unit, FIG. 4 is an explanatory view showing a memory arrangement of a task stack area, and FIG. 5 is a flowchart showing a judgment processing model by a register that reflects the presence or absence of overflow.

First, the configuration of the microcomputer according to the first embodiment will be described with reference to FIG.

The microcomputer of the first embodiment is a single chip microcomputer formed on one semiconductor substrate such as a silicon substrate by a well-known semiconductor manufacturing technique, for example, and is a central processing unit CP.
U, read only memory ROM, random access memory RAM, oscillator CPG, interrupt controller IR
C, bus state controller BSC, serial communication interface SCI, timer pulse unit TPU, analog / digital converter A / D, input / output port I / O and the like.

The central processing unit CPU has a stack area abnormality detection function and is a central part of a microcomputer including an instruction decoding section, an instruction executing section, an address generating section, etc. These peripheral circuits such as control instructions and input / output of data to the input / output ports are controlled and managed by the central processing unit CPU.

For example, the central processing unit CPU is configured as shown in FIG. 2, and has an instruction prefetch / decode unit 1 for prefetching and decoding instructions, a control unit 2 for controlling other units, and an arithmetic unit for arithmetic operation of data. 3, a stack error detection unit 4 having a stack area error detection function (stack area error detection means), an input / output control unit 5 for controlling input / output of instructions and operands
It is composed of

In the stack abnormality detecting unit 4, particularly as a control register, an address register ADR (first register) for setting an uppermost address of an area to be detected for destruction as shown in FIG. A status register STS (second register) that reflects the occurrence of overflow from the set address as shown in (b) is provided.

The read-only memory ROM is a read-only memory including memory cells and address decoders, and is a programmable read-only memory PROM whose stored contents can be freely determined after the product is completed.
Alternatively, a mask ROM whose storage content is determined by a mask used during product manufacturing is used, and a system or application program is stored.

The random access memory RAM is a memory that can be read from and written to at any time and is composed of a memory cell, an address decoder, etc., so that writing and reading of data can be performed to a memory cell of an arbitrary address at substantially the same access time. It has become.

The oscillator CPG is a part for generating a clock pulse, for example, a flip-flop, a counter,
It is composed of a frequency dividing circuit including a gate, a driver circuit, and the like, and clock pulses generated by the oscillator CPG are supplied to devices inside and outside the microcomputer.

The interrupt controller IRC is a part which determines the priority of interrupt factors and controls an interrupt request to the central processing unit CPU. For example, the bus state controller BS outside or inside the microcomputer.
In response to a processing request from C, the timer pulse unit TPU, etc., the program currently being executed by the central processing unit CPU is temporarily suspended, and the processing of the device to which the request is output is preferentially performed.

The bus state controller BSC is a part that divides the address space and outputs control signals according to various memories and peripheral circuits. For example, the bus state controller BSC is an internal bus of the microcomputer, that is, data. The right to use the bus is controlled.

The serial communication interface SCI is a part for communicating serial data.
For example, when transmitting / receiving data to / from a peripheral device, data having a bit length of 8 bits or the like is serially transferred for reasons such as preventing exclusive use of a bus line and reducing the number of input / output pins.

The timer pulse unit TPU is a part for controlling timer output and pulse output. For example, the timer pulse unit TPU is provided with a register that can be initialized and an incrementer (or decrementer), and an internal interrupt is generated when a carry (or borrow) occurs. It can be generated.

The analog / digital converter A / D is a part for converting analog data into digital data. For example, analog data input from a peripheral device is turned on / off by a switch circuit connected to a resistor network. It is converted into digital data, and digital control is performed inside the microcomputer.

The input / output port I / O is a part for inputting / outputting data, and for example, many have a function of latching data, and once data is input / output by an instruction, the next instruction is executed. The data is retained.

In the microcomputer configured as described above, the central processing unit CPU controls the operation of each constituent element of the microcomputer based on the system and application programs stored in the read-only memory ROM. You can do it.

Next, the operation of the first embodiment will be described with reference to FIG. 5, which shows a determination processing model of stack area destruction due to stack area overflow. In the first embodiment, the status register S shown in FIG.
By accessing the TS, early detection of stack area destruction can be realized.

Specifically, assuming that the task stack area is located below the data management area of the OS as shown in FIG. 4, the address register ADR shown in FIG.
In advance, the uppermost address of the task stack area is set (step 501).

Further, the stack pointer S is stored in the status register STS that reflects the presence or absence of overflow.
When P indicates the upper part of the contents of the address register ADR, "1" indicating the occurrence of overflow is automatically set by the control of the central processing unit CPU.

At this time, when control is passed from the task to the OS, the status register S that reflects the presence or absence of overflow before the OS accesses the data management area.
The TS is accessed to determine whether it is ON, that is, whether an overflow has occurred (step 502).

As a result of this judgment, the status register ST
If "1" indicating that an overflow has occurred is set in S and is ON, it is determined that an overflow has occurred in the task stack area and control is passed to an abnormal routine or the like (step 503).

On the other hand, in the status register STS,
If "0" is set and OFF, it can be determined that no overflow has occurred in the task stack area, and therefore normal processing is continued (step 504).

Accordingly, by monitoring the value of the status register STS shown in FIG. 3B before accessing the data management area, it is possible to detect the destruction of the stack area due to the occurrence of overflow.

Therefore, according to the microcomputer of the first embodiment, by providing the address register ADR and the status register STS as the control registers in the stack abnormality detection unit 4, the stack pointer SP is set to the value of the address register ADR. By indicating the upper part and automatically setting the value of the status register STS to "1" when an overflow occurs, the destruction of the stack area can be found immediately and the secondary and tertiary failures due to this can be prevented. You can

Further, since the destruction of the stack area can be found immediately and it is not necessary to spend a great deal of labor and cost for investigating the cause of the failure due to the secondary and tertiary failures as in the conventional case, the debugging efficiency of the microcomputer can be improved. Can be improved and the number of steps can be reduced.

(Second Embodiment) FIG. 6 is an explanatory view showing a control register in a stack abnormality detecting unit in a microcomputer according to a second embodiment of the present invention, and FIG. 7 is a flow chart showing a judgment processing model by interruption. is there.

The microcomputer of the second embodiment is a single-chip microcomputer formed on one semiconductor substrate such as a silicon substrate by the well-known semiconductor manufacturing technique as in the first embodiment.
The difference from the first embodiment is that the method of determining the stack area destruction due to the overflow of the stack area is different, it is possible to set the interrupt enable / disable after the overflow is detected, and the status register STS is accessed or an interrupt error occurs. By passing control to a termination routine, etc., it is possible to realize early detection of stack area destruction due to stack area overflow.

That is, in the second embodiment, the address register ADR for setting the uppermost address of the area to be the destruction detection target is set in the stack abnormality detection unit 4.
(First register), status register ST that reflects the occurrence of overflow from the set address to the upper part
In addition to S (second register), a flag register FLG (third register) for setting whether to generate an interrupt after detecting an overflow as shown in FIG. 6 is provided.

Therefore, in the second embodiment, when the memory arrangement is similar to that of the first embodiment, as shown in FIG. 7, the uppermost address of the task stack area is set in the address register ADR (step 701). ), And when the stack area overflows, the flag register FLG is set to the ON state by "1" indicating the interrupt permission (step 702).

At this time, normal processing is continued (step 703), but when an overflow of the stack area occurs, not only is it reflected in the status register STS, but a stack abnormal interrupt is generated (step 70).
4). If the stack abnormality routine is embedded in this interrupt vector, the control is automatically passed to the stack abnormality routine, and the processing at the time of the stack abnormality can be performed (step 705).

Thus, it is possible to detect the destruction of the stack area due to the overflow due to the value of the status register STS or the occurrence of the interrupt.

Therefore, according to the microcomputer of the second embodiment, the flag register FLG is added as a control register in the stack abnormality detection unit 4, so that the stack pointer SP is moved to the address register A.
When an overflow occurs above the value of DR and the overflow occurs, the value of the status register STS is automatically set to "1" and a stack abnormal interrupt is generated, so that the stack area is destroyed as in the first embodiment. Can be immediately detected, and secondary and tertiary failures due to this can be prevented, the debugging efficiency of the microcomputer can be improved, and the number of steps can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above-mentioned embodiment, the case of setting the uppermost address of the area to be detected for destruction is described, but the present invention is not limited to the above-mentioned embodiment, and the stack area It is also possible to set the bottom part to a different address register for monitoring,
In this case, the upper and lower parts of the stack area can be managed.

In addition, the bit no. Of the status register and the flag register. And the address register,
It is also possible to monitor the destruction of multiple task stack areas by installing multiple address registers.

Further, in the above-described embodiment, the case where the present invention is applied to a microcomputer alone has been described, but a real-time system using a microcomputer, that is, a system or application program in which processing time is important such as a real-time OS is used. The present invention is applied to various systems such as copiers, facsimiles, and telephones to be operated. As an example, a facsimile system will be described with reference to FIG.

In this facsimile system, for example, a microcomputer has a port for inputting / outputting encoded or decoded image data and a port for inputting / outputting a code.
There are two ports. Each port is connected to an image data bus and a system bus, an image scanner and a printer are connected to the image data bus, and a host CP for controlling a microcomputer is connected to the system bus.
A transmission line interface such as a U or a modem is connected. An image memory is connected to the image data bus, and this is a memory for buffering image data or codes.

Next, the general operation of this facsimile system will be described. First, when the image data is read by the image scanner and the encoded data is transmitted to the transmission line, the binary image data read by the image scanner is
It is stored in the temporary image memory by the DMA controller. Then, the microcomputer reads the data from the image memory and performs an encoding process.

Further, the coded data processed by the microcomputer is stored in the internal register of the microcomputer. Then, the microcomputer requests the host CPU to generate an interrupt signal and read the encoded data from the internal register.

Then, by the host CPU, I / O
The coded data is read by read or DMA transfer by the DMA controller of the system bus. The read data is temporarily buffered in the system memory and then output to the modem as a transmission line.

When the encoded data received from the transmission line is printed out, the above-mentioned image data is read by the image scanner and the encoded data is transmitted to the transmission line in the reverse manner. As a result, the encoded data sent from the transmitting side is decoded on the receiving side,
This decrypted data is printed out.

As described above, the present invention can be favorably applied to a system in which the processing time is important such as a real-time OS or a system operated by using an application program.

[0059]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). A stack area abnormality detecting means for detecting an overflow of the stack area, and a first register for setting an uppermost address of an area to be detected for destruction,
By providing the second register that reflects the occurrence of overflow from the set address to the upper part, the second register can be automatically set when the stack pointer indicates the upper part of the contents of the first register. By monitoring this second register, the stack area overflow can be detected.

(2). In addition to the first register for setting the uppermost address and the second register for reflecting the occurrence of overflow, the stack area abnormality detecting means for detecting overflow of the stack area detects overflow. By setting a third register for setting whether or not to generate an interrupt after that, the second register is set when the third pointer is set and the stack pointer indicates the upper part of the contents of the first register. Since an interrupt can be generated at the same time as the automatic setting, the overflow of the stack area can be detected by this interrupt.

(3) Because of the above (1) and (2), it is possible to realize early detection of stack area destruction by detecting overflow of the stack area, so that secondary and tertiary failures due to this stack area destruction can be prevented. It becomes possible to prevent it.

(4) By the above (3), secondary and tertiary failures due to stack area destruction can be prevented in advance, so that debugging efficiency can be improved.

(5) According to the above (1) to (4), in the debugging of the microcomputer and the real-time system using the microcomputer, it is possible to improve the performance of the multi-task real-time system and reduce the development man-hours.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a microcomputer that is Embodiment 1 of the present invention.

FIG. 2 is a block diagram showing a central processing unit in the first embodiment.

FIG. 3 is an explanatory diagram showing a control register in the stack abnormality detection unit according to the first embodiment.

FIG. 4 is an explanatory diagram showing a memory layout of a task stack area according to the first embodiment.

FIG. 5 is a flowchart showing a judgment processing model by a register that reflects the presence or absence of overflow in the first embodiment.

FIG. 6 is an explanatory diagram showing a control register in a stack abnormality detection unit in the microcomputer that is Embodiment 2 of the present invention.

FIG. 7 is a flowchart showing a judgment processing model by interruption in the second embodiment.

FIG. 8 is a block diagram showing a facsimile system using the microcomputer according to the embodiment.

[Explanation of symbols]

1 instruction prefetch / decode unit 2 control unit 3 arithmetic unit 4 stack abnormality detection unit (stack area abnormality detection means) 5 input / output control unit CPU central processing unit ROM read only memory RAM random access memory CPG oscillator IRC interrupt controller BSC bus state controller SCI serial communication interface TPU timer pulse unit A / D analog / digital converter I / O I / O port ADR address register (first register) STS status register (second register) FLG flag register (third register)

Claims (4)

[Claims] 1. A microcomputer having at least a central processing unit and its peripherals, wherein the central processing unit detects a stack area overflow based on a result of comparison between a stack pointer value and a predetermined address value. A microcomputer having a built-in abnormality detecting means. 2. The microcomputer according to claim 1, wherein a first register for setting an uppermost address of an area to be destroyed and detected is set as a control register of the stack area abnormality detecting means. A second register that reflects the presence or absence of overflow detection from the address. 3. The microcomputer according to claim 2, further comprising a third register for setting whether or not to generate an interrupt after detecting the overflow, and setting the third register to detect overflow. A microcomputer which is enabled and automatically sets the value of the second register and simultaneously generates an interrupt when the value of the stack pointer is higher than the value of the first register. . 4. A real-time system using the microcomputer according to claim 1, 2 or 3, wherein the microcomputer is operated using a system or application program such as a real-time operation system in which processing time is important. A real-time system characterized by that.