JPH0659921A - Microcomputer - Google Patents

Abstract

PURPOSE:To cope with the runaway of a microprogram without providing an exclusive terminal by providing a microcomputer with a means for selecting either one of system initialization or interruption in accordance with the overflow of a watch-dog timer circuit. CONSTITUTION:A time base counter 201 in the watch-dog timer(WDT) circuit 130 counts up clocks CLK 210 and outputs a specified WDT count lock 211 from its output tap. When a WDT clear signal(WDTCLR) 214 or a reset signal (RESET) 145 is inputted to an OR gate 205, a clear signal 216 is activated and a WDT 202 is initialized. If the WDT 202 continues counting-up operation without being initialized and generates overflow, a WDTOUT active timer 203 is started and a flip flop(FF) 204 is reset.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer equipped with a watchdog timer circuit (hereinafter referred to as "microcomputer").

[0002]

2. Description of the Related Art A conventional microcomputer uses a watchdog timer circuit to cope with program runaway.

FIG. 4 is a block diagram of a conventional microcomputer. As shown in FIG. 4, the conventional microcomputer 400 has a C
It includes a PU 401 and a peripheral circuit 404, and these are mutually connected by an internal bus 405. Moreover, CPU
Reference numeral 401 denotes a micro sequencer 402 and an arithmetic processing unit 40.
3, an instruction queue 420, and a program counter (hereinafter referred to as a PC) 421, which are connected by an internal bus 405. In addition, the peripheral circuit 404 includes circuits such as a watchdog timer 430 and INTC431. Further, the micro sequencer 402 in the CPU 401 is provided with the instruction decoder 410 and the MI.
R411 and micro program ROM (hereinafter referred to as μRO
412, a MSTL 413, a reset entry storage unit 414, and a selector 415.

First, the instruction code from the address indicated by the PC 421 is fetched into the instruction queue 420 and input to the instruction decoder 410. The instruction decoder 410 outputs the input instruction code in μR
It is converted into the start address (hereinafter referred to as an entry) of the execution procedure (microprogram) for each instruction stored in the OM 412. This entry is stored in MIR411 and
Designate the start address of the microprogram in M412. Then, the contents of the microprogram stored at this start address are stored in the MSTL 413. MSTL4
The contents stored in 13 include a control signal of each part of the microcomputer for executing the process and address information of the micro program to be executed next (hereinafter referred to as the next address).

Next, the arithmetic processing unit 403 performs processing based on the control signal output from the MSTL 413. Also, the MSTL 413 activates the END signal 446 in the final step of the microprogram. This END signal 4
When the reset request signal 443 is not input when 46 is off, the bus D is selected by the selector 415,
The next address output from MSTL413 is MIR.
Stored in 411, the processing of the next step of the instruction is performed. On the other hand, when the END signal 446 is on, the interrupt signal 444 is off, and the reset request signal 443 is not input, the bus B is selected by the selector 415, and the input of the next instruction decoder 410 is M.
It is stored in IR 411 and processing of the next instruction is started.

When the reset request signal 443 is input to the input terminal RESET 440, the selector 415 selects the bus C and the reset entry storage unit 414 is selected.
The reset instruction entry output from MIR411
And specifies the microprogram entry corresponding to the reset instruction in the μROM 412. And
The contents of the microprogram stored in this start address are stored in MSTL413. The arithmetic processing unit 403 is an MS
Based on the contents of the microprogram stored in the TL 413, the corresponding register in the arithmetic processing unit 403 is initialized and the reset program start address is stored in the PC 421 via the internal bus 405. At the same time, since the reset request signal 443 is also input to the peripheral circuit 404, each peripheral circuit is initialized.

Next, detection of interrupts in the microprogram is performed only in the final step of the microprogram of instructions. First, when an interrupt request from each peripheral circuit is generated, the INTC 431 selects the highest interrupt request by looking at its priority order and assigns the code to the CPU.
At the same time as the transfer to 401, the interrupt signal 444 is activated. That is, when the END signal 446 is on,
If the reset request signal 443 has not been input, the bus A is selected by the selector 415, and the interrupt entry is input to the MIR 411 to specify the start address of the microprogram. Therefore, the CPU 401 calculates and reads a vector address based on the code information sent from the INTC 431 in the interrupt microprogram, and stores it in the PC 421. With the above configuration, it is possible to shift to interrupt processing without disturbing the operation of the instruction microprogram.

FIG. 5 is a block diagram of the watchdog timer shown in FIG. As shown in FIG. 5, the watchdog timer 430 counts the internal system clock CLK510 and outputs the WDT count clock 511 13
Time base counter 501 which is a bit counter
And the WDT502, which is an 8-bit counter that counts the WDT count clock 511, and the WD
It is composed of a WDTOUT active timer 503, which is a 5-bit counter that detects the overflow of T502 and starts counting, a flip-flop 504, and an OR gate 505.

First, the time base counter 501 is CL
K510 is counted, and the designated WDT count clock 511 is output from the output tap. When the start signal (START) 514 is input to the WDT 502, W
The DT 502 starts the counting operation of the WDT count clock 511. On the other hand, the watchdog timer clear signal WDTCLR513 or the reset signal RESET443
Is input to the OR gate 505, the OR gate 505
Output becomes "1", the clear signal 515 is activated, and the WDT 502 is initialized.

Next, if the WDT 502 is not initialized and continues the count-up operation to cause an overflow, the WD
The TOUT start signal 445 is activated. This WD
When the TOUT start signal 445 is input to the INTC 431 (see FIG. 4), the interrupt operation is activated.

Therefore, when the runaway state of the program is detected by the overflow interrupt of the WDT 502, it is possible to check the runaway state of the program in the interrupt processing and perform the processing corresponding to that state. However, in this case, each peripheral circuit cannot be initialized to the state after the system reset. Therefore, the output terminal (WDTOU
T) 441 outputs the output signal 442 of the flip-flop 504.
Is output and is externally connected to the input terminal RESET 440 to reset the system.

The WDTOUT start signal 445 is input to the WDTOUT active timer 503 and the flip-flop 504. The WDTOUT start signal 445 sets the set / reset type flip-flop 504, and "1" is output from the output terminal WDTOUT441. Further, when the WDTOUT start signal 445 is input, the WDTOUT active timer 503 starts the count-up operation. WDTOU
When the T active timer 503 finishes counting for a certain period of time, it overflows and the overflow signal 51
2 is output. This overflow signal 512 resets the flip-flop 504, so that the output terminal WDT
“0” is output from OUT441. By the operation described above, the output terminal WDTOUT441 is set to "1" after a certain period from the detection of the overflow of the WDT502.
Is output. The WDTOUT signal 442 is input to the input terminal RESET440 and performs the above-described reset process.

[0013]

In the conventional microcomputer described above, when a program runaway or a system abnormality is detected, the watchdog timer overflow interrupt detects the program runaway state, and the program is executed in the interrupt process. After checking the runaway state of, the process corresponding to that state is performed. However, in this case, there is a drawback that each peripheral circuit cannot be initialized to a state after system reset.

Further, since the microprogram for each instruction is usually composed of the execution procedure of a plurality of steps, the runaway of the microprogram may occur depending on the hardware state. In such a case, detection of interrupt occurrence is executed only at the final step of the microprogram for each instruction. Therefore, if the microprogram causes a runaway that does not reach the final step, detect a watchdog timer interrupt. Cannot be performed, and is invalid for runaway at the microprogram level.
Therefore, the system reset is performed by providing a dedicated output terminal and externally connecting to the reset terminal. Therefore, this microcomputer requires a dedicated output terminal and has the disadvantage of increasing the number of pins.

Further, such a microcomputer cannot distinguish whether the system reset is caused by the input of the reset signal or the overflow of the watchdog timer.

An object of the present invention is to enable each peripheral circuit to be initialized to a state after a system reset, to cope with a runaway microprogram without providing a dedicated output terminal, and to perform a system reset. Another object of the present invention is to provide a microcomputer capable of distinguishing between the reset signal and the overflow signal.

[0017]

The microcomputer of the present invention comprises a watchdog timer circuit for detecting a program runaway or a system abnormality, and either system initialization or interrupt due to overflow of the watchdog timer circuit. And a output means for outputting the start address of the microprogram when the overflow of the watchdog timer circuit is detected.

[0018]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram of a microcomputer showing a first embodiment of the present invention. As shown in Figure 1,
The microcomputer 100 of this embodiment includes a CPU 10
1, peripheral circuit 104, OR gate 122, interrupt designating bit 123, inverter 124, and gate 1
25 and 126, and are connected by the internal bus 105. The interrupt designation bit 123 can be set through the internal bus 105.

First, the CPU 101 includes a micro sequencer 102, an arithmetic processing unit 103, an instruction queue 120,
The program counter 121 is included, and these are directly or indirectly connected to each other by the internal bus 105.
The micro sequencer 102 includes an instruction decoder 110 connected to the instruction queue 120 and an MIR1.
11, microprogram ROM 112, MSTL
113, a reset entry storage unit 114, a WDT entry storage unit 115, and a selector 116 that selectively supplies data to the MIR 111. Also,
The peripheral circuit 104 includes a watchdog timer 130 and an I
It is composed of the NTC 131 and other peripheral circuits (not shown).

In the CPU 101, the PC 121
The instruction code from the address indicated by is fetched into the instruction queue 120 and input to the instruction decoder 110. The instruction decoder 110 converts the input instruction code into a microprogram entry for each instruction stored in the μROM 112. This entry is stored in the MIR 111 and specifies the start address of the microprogram in the μROM 112. And
The contents of the microprogram stored at this start address are stored in the MSTL 113. The contents stored in the MSTL 113 include control signals for each part of the microcomputer for executing processing and the next address.
The processing is performed by the arithmetic processing unit 103 based on the control signal output from the controller 3. Further, the MSTL 113 activates the END signal 146 in the final step of the microprogram.

When the END signal 146 is off and the reset request signal 142 is not input, the selector 1
The bus D is selected by 16 and the next address output from the MSTL 113 is stored in the MIR 111, whereby the processing of the next step of the instruction is performed. Conversely, when the END signal 146 is on, the interrupt request signal 1
When 41 is off and the reset signal 145 is not input, the selector 116 selects the bus B and the input of the next instruction decoder is stored in the MIR 111, so that the processing of the next instruction is started.

On the other hand, since the reset request signal 142 input to the input terminal RESET140 is input to the reset entry storage section 114 and also to the OR gate 122, the output of the OR gate 122 becomes "1". That is, the RESET signal 145 is activated.
When the RESET signal 145 is activated, the bus C is selected by the selector 116 and the entry of the reset instruction output from the reset entry storage unit 114 is MI.
It is stored in R111. As a result, the start address of the microprogram corresponding to the reset instruction in the μROM 112 is designated, and the contents of the microprogram stored at this start address are stored in the MST 113. This MST
Based on the contents of the microprogram stored in L113, the arithmetic processing unit 103 initializes the corresponding internal register and stores the program start address after reset in the PC 121. At the same time, the RESET signal 145 is input to the peripheral circuit 104 and each peripheral circuit is also initialized.

Next, INTC1 in the peripheral circuit 104
Reference numeral 31 always samples the interrupt request signal from each peripheral. Therefore, when an interrupt request occurs,
The INTC 131 selects the highest interrupt request in view of its priority, transfers the code to the CPU 101, and at the same time activates the interrupt request signal 141. Here, when the END signal 146 from the MSTL 113 is on and the reset request signal 142 is not input,
The bus A is selected by the selector 116, the entry of the interrupt is stored in the MIR 111, and the start address of the microprogram is designated. Further, the vector address is calculated based on the code information sent from the INTC 131 in the interrupt microprogram, read out and stored in the PC 121.

As described above, since the microcomputer of this embodiment is configured, it is possible to shift to the interrupt processing without disturbing the operation of the instruction microprogram.

FIG. 2 is a block diagram of the watchdog timer shown in FIG. As shown in FIG. 2, the watchdog timer 130 counts the internal system clock CLK210 and outputs the WDT count clock 211 13
A bit time base counter 201, an WDT 202 that is an 8-bit counter that counts the WDT count clock 211, a WDTOUT active timer 203 that forms a 5-bit counter that detects overflow of the WDT 202 and starts counting, and WDT.
WDTO set by OUT start signal 212
While outputting the UT signal 143, the flip-flop 204 set by the overflow signal 213 of the WDT active timer 203, the watchdog timer clear (WDTCLR) signal 214 and the reset (RE
SET) signal 145 and an OR gate 205 that takes the logical sum of the signals.

The time base counter 201 in the watch dog timer 130 counts the CLK 210 and outputs the designated WDT count clock 211 from the output tap. When the start signal (START) 215 is input to the WDT 202, the WDT 202
Starts the counting operation of the WDT count clock 211. Further, when the watchdog timer clear signal (WDTCLR) 214 or the reset signal (RESET) 145 is input to the OR gate 205, the output becomes 1, so the clear signal 216 is activated and the WDT 202 is initialized. .

On the other hand, if the WDT 202 is not initialized and continues counting up to cause an overflow, W
The DTOUT start signal 212 is activated. This W
Since the DTOUT start signal 212 not only starts the WDTOUT active timer 203 but is also input to the flip-flop 204, the set-reset type flip-flop 204 is set and WDTOUT is set.
“1” is output as the signal 143. Further, the WDTOUT active timer 203 has a WDTOUT start signal 21.
When 2 is input, the count-up operation starts, and after counting for a certain period, overflow occurs,
The overflow signal 213 is output. The overflow signal 213 resets the flip-flop 204 and sets the WDTOUT signal 143 to "0".

Next, the interrupt designation bit 12 shown in FIG.
When 3 is “1”, the interrupt designation signal 144 is the gate 1
25, the WDTOUT signal 143 is stored in the WDT entry storage unit 115, and the OR gate 122 is opened.
, The output of the OR gate 122 becomes "1" and the RESET signal 145 is activated.
When the RESET signal 145 is activated, the selector 116 selects the bus C, and the entry output from the WDT entry storage unit 115 is stored in the MIR 111. That is, the start address of the microprogram in the μROM 112 is designated. Then, the contents of the microprogram stored in this start address are stored in the MSTL 113. Therefore, the arithmetic processing unit 103 uses the MSTL11
3, the corresponding registers in the arithmetic processing unit 103 are initialized based on the contents of the microprogram stored in
The program start address after processing is stored in 121. At this time, the start address stored in the PC 121 is different from the program start address after the reset processing by the reset request signal 142. At the same time, RE
Since the SET signal 145 is input to the peripheral circuit 104,
Each peripheral circuit is also initialized.

Next, the interrupt designation bit 123 is "0".
, The interrupt designating signal 144 is inverted by the inverter 124 to open the gate 126. Therefore, WDT
The OUT signal 143 is input to the INTC 131. When the WDTOUT signal 143 is input to the INTC 131, an interrupt is activated, the interrupt request signal 141 is activated, and interrupt processing is performed.

FIG. 3 is a block diagram of a microcomputer showing a second embodiment of the present invention. As shown in FIG. 3, this embodiment compares the CPU with the first embodiment described above.
301 is different, especially the micro sequencer 3 inside
The configuration of 02 is different, and the others are the same. The micro sequencer 302 has an entry generation unit 314 and a flip-flop 31 instead of the reset entry storage unit 114 and the WDT entry storage unit 115 in the first embodiment.
5 is used.

First, the operation when the reset request signal 142 is input will be described. When the reset request signal 142 is input to the RESET input terminal 140, the set-reset type flip-flop 315 is reset and the entry generation signal 347 becomes "0". This entry generation signal 347 is input to the entry generation unit 314, and the upper 1 bit of the entry generation unit 314 is set to “0”. The entry generation unit 314 selects the entry of the microprogram generated by the entry generation signal 347 from the selector 11
Then, the reset processing operation similar to that of the first embodiment is performed.

Next, the operation when the watchdog timer 130 overflows will be described. At this time, first, when the interrupt designation bit 123 is "1", the interrupt designation signal 144 opens the gate 125, and the WDTO
The UT signal 143 is input to the flip-flop 315.
As a result, the flip-flop 315 is set and the entry generation signal 347 is set to "1". The entry generation signal 347 is input to the entry generation unit 314 and sets the upper 1 bit of the entry generation unit 314 to “1”. The entry generation unit 314 outputs the microprogram entry generated by the entry generation signal 347. After that, the reset processing operation due to the overflow of the watchdog timer 130 is performed as in the first embodiment.

On the other hand, the interrupt designation bit 123 is "0".
In the case of, the same interrupt processing operation as in the first embodiment is performed.

As described above, in this embodiment, the watchdog timer 130 is controlled by the output of the flip-flop 315.
The microprogram entry is generated for the case of overflow of the
The case where one entry storage unit performs the same operation as that of the above embodiment is shown.

[0035]

As described above, when the microcomputer of the present invention detects a program runaway or a system abnormality, the microprogram entry is designated by the overflow of the watchdog timer, and the micro program processing routine is executed. Since it exists, there is an effect that it is possible to deal with a case where the microprogram causes a runaway that does not reach the final step. Further, the present invention has an effect that the number of pins can be reduced because it is not necessary to provide a dedicated output terminal. Further, according to the present invention, since the program start address immediately after the reset processing is changed depending on the processing by the input of the reset signal and the processing by the overflow of the watchdog timer, it is possible to distinguish which is the system reset. There is an effect.

[Brief description of drawings]

FIG. 1 is a block diagram of a microcomputer showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a watchdog timer shown in FIG.

FIG. 3 is a block diagram of a microcomputer showing a second embodiment of the present invention.

FIG. 4 is a block diagram of a microcomputer showing a conventional example.

5 is a configuration diagram of the watchdog timer shown in FIG. 4. FIG.

[Explanation of symbols]

 100,300 Microcomputer 101,301 CPU 102,302 Microsequencer 103 Arithmetic processing section 104 Peripheral circuit 110 Instruction decoder 111 MIR 112 Microprogram ROM 113 MSTL 114 Reset entry storage section 115 WDT entry storage section 116 Selector 120 Instruction queue 121 Program counter 122 OR gate 123 Interrupt designation bit 124 Inverter 125, 126 Gate 130 Watchdog timer 131 INTC 140 Input terminal RESET 201 Time base counter 202 WDT 203 WDTOUT active timer 204, 315 Flip-flop 205 OR gate 314 Entry generator

Claims (1)

[Claims] 1. A watchdog timer circuit for detecting a program runaway or a system abnormality, selection means for selecting either system initialization or interrupt due to overflow of the watchdog timer circuit, and the watchdog timer. A microcomputer having an output means for outputting a start address of a microprogram when a circuit overflow is detected.