JPH0816434A - Runaway detection device - Google Patents

Abstract

PURPOSE:To optionally set runaway state detection timing and prevent the load on a CPU from being increased by judging the match of an expected value of data outputted when a storage part is accessed and data outputted onto a data bus. CONSTITUTION:A program for initialization is stored in a memory 2, when a CPU 1 starts executing the program, an address to be noticed for runaway detection of the CPU 1 is stored in an address register 5 and the expected value expected to be outputted to a data signal line 10 when the address stored in the address register 5 is accessed is stored in the data register 6. Then a comparator 3 compares the address stored in the address register 5 with the address outputted onto the address signal line 9 and a comparator 4 compares the data read out of the memory to a data signal line 10 with the expected value stored in the data register 6, and a runaway processing part 8 performs runaway processing when the output of its output terminal is at H level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a runaway detection circuit for detecting runaway of a CPU of a single chip microcomputer.

[0002]

2. Description of the Related Art In a conventional microcomputer, sometimes a CPU malfunctions due to various factors and falls into a so-called runaway state in which the operation according to a program is not executed. FIG. 13 is a block diagram showing the configuration of a conventional runaway detection circuit. In the figure, 201 is a counter,
202 is a runaway processing circuit, 203 is a clock input signal line to which a clock signal is input, and 204 is a CP not shown.
A reset signal input line from which a reset signal is sent from U, and 205 is an overflow signal output line from which an overflow signal is output from the counter 201 to the runaway processing circuit 202.

Next, the operation will be described. In this runaway detection circuit, the counter 201 uses the clock input signal line 203
When the CPU is operating normally, the counter 201 is reset by the reset signal sent from the CPU via the reset signal input line 204 before it overflows.
Accordingly, the counter 201 counts the clock signal again from the beginning. That is, the counter 201 does not overflow as long as the CPU is operating normally.

On the other hand, when the CPU falls into a runaway state, the cycle of the reset signal sent becomes long, or the reset signal is not sent, the counter 201 overflows, and the overflow signal is input to the runaway processing circuit 202. This causes the runaway processing circuit 202 to generate a CPU reset signal or an interrupt signal.

[0005]

Since the conventional runaway detection circuit is configured as described above, the cycle of the reset signal for resetting the counter 201 by the runaway of the CPU is C
When the cycle becomes shorter than the normal operation cycle of the PU, the counter 201 is reset before overflow as in the normal operation of the CPU. As a result, the runaway state of the CPU cannot be detected. .

Further, the counter 2 can be operated depending on the runaway state of the CPU.
When the cycle of the reset signal for resetting 01 is long, in the worst case, there is a problem that the runaway state continues until the internal state value when the counter 201 is reset until it overflows.

If the cycle from the internal state value when the counter 201 is reset to the overflow is shortened, the repetition cycle of the reset signal for resetting the counter generated in accordance with the normal operation of the CPU must be shortened. However, a large number of clear instructions for outputting the reset signal are inserted in the original program, which causes a problem of increasing the load on the CPU.

The first aspect of the present invention has been made to solve the above problems, and provides a runaway detecting circuit which can set the timing for detecting the runaway state arbitrarily and does not increase the load on the CPU. The purpose is to get.

According to the second aspect of the present invention, the timing for detecting the runaway state can be arbitrarily set, the responsiveness in detecting the runaway state can be improved without imposing a load on the CPU, and the runaway state can be detected. The purpose is to obtain a runaway detection circuit with improved reliability.

According to the third aspect of the present invention, the timing for detecting the runaway state can be arbitrarily set, and the response at the time of detecting the runaway state and the accuracy of detecting the runaway state can be improved without imposing a burden on the CPU. The purpose is to obtain a runaway detection circuit that operates.

It is an object of the present invention to provide a runaway detection circuit capable of improving the responsiveness at the time of detecting the runaway state and the accuracy of detecting the runaway state without imposing a burden on the CPU.

It is an object of the present invention to provide a runaway detection circuit with improved setting accuracy when setting the timing for detecting a runaway state without imposing a burden on the CPU.

It is an object of the present invention to provide a runaway detection circuit capable of setting a timing for detecting a runaway state with a certain width without imposing a burden on the CPU.

[0014]

According to another aspect of the present invention, there is provided a runaway detection circuit for an arbitrary address of a storage unit accessed by a CPU and data output on a data bus when the address is accessed. The setting means for setting the expected value and the runaway of the CPU by judging the match between the data output on the data bus when the CPU accesses the address and the expected value set by the setting means And a runaway determination circuit for determining the state.

The runaway detection circuit according to the invention of claim 2 is C
It is provided with an arbitrary plurality of addresses of the storage unit accessed by the PU and a setting means for setting an expected value for the data output on the data bus when the respective addresses are accessed.

The runaway detection circuit according to the invention of claim 3 is C
The address setting means for setting an arbitrary plurality of addresses in the storage unit accessed by the PU, and the CPU by judging whether or not the addresses set by the address setting means are accessed in a predetermined order. And an order determination circuit for determining the runaway state of.

The runaway detection circuit according to the invention of claim 4 is C
Address setting means for setting an arbitrary address storing the instruction code of the storage unit accessed by the PU, and whether the data fetched by the CPU when the address set by the address setting means is the instruction code An instruction code judging circuit for judging the runaway state of the CPU by judging whether or not it is provided.

The runaway detection circuit according to the invention of claim 5 is C
Address range setting means for setting an arbitrary address range of the storage unit accessed by the PU, and data next to the instruction code included in the address range set by the address range setting means when the address range is accessed By determining the data value setting means for setting a value and determining whether the data value next to the instruction code fetched when the address range is accessed is the data value set by the data value setting means. A check data determination circuit for determining the runaway state of the CPU is provided.

The runaway detection circuit according to the invention of claim 6 is C
Address range setting means for setting an arbitrary address range of the storage unit accessed by the PU, and output or output on the data bus when the address range set by the address range setting means is accessed And an instruction code setting means for setting a range of instruction codes that does not exist, and C when the address range is accessed.
An instruction code range determination circuit for determining the runaway state of the CPU by determining whether the instruction code fetched by the PU is within the range set by the instruction code setting means. .

[0020]

According to the first aspect of the present invention, the runaway detection circuit has a CP
Since the data output on the data bus becomes abnormal if U runs out of control, the expected value for the arbitrary address accessed by the CPU and the data output on the data bus when that address is accessed is set in advance. Then, it is determined whether the data read from the address by the CPU and output on the data bus matches the set expected value. If they do not match, it is determined that the CPU is in a runaway state, and the CPU executes the program. It is possible to arbitrarily set the timing for detecting the runaway state without increasing the load on the CPU by directly monitoring.

The runaway detection circuit according to the invention of claim 2 is
By setting a plurality of addresses, providing a plurality of data that are expected values that should be read when the set addresses are accessed, and directly monitoring the execution operation of the program of the CPU, each of the set addresses is set. When data is accessed, it is determined whether the data actually read and the expected value match, and if they do not match, it is possible to set the timing for detecting the runaway state by determining the runaway state of the CPU, and The responsiveness when detecting a runaway state is improved without imposing a burden on the robot, and the reliability is improved when a runaway state is detected.

The runaway detection circuit according to the invention of claim 3 is
A plurality of arbitrary addresses to be accessed are set in advance, and it is judged whether the access to the set addresses is executed in a predetermined order by directly monitoring the operation of the CPU, and the runaway state is detected. It is possible to arbitrarily set the timing to perform, and it is possible to improve the responsiveness when detecting the runaway state and the accuracy of detecting the runaway state without imposing a burden on the CPU.

The runaway detection circuit in the invention of claim 4 is
An arbitrary address storing the instruction code is set in advance, and C when the set address is accessed
CP whether the data taken in by the PU is an instruction code
It is possible to improve the responsiveness at the time of detecting a runaway state and the accuracy of detecting the runaway state without imposing a burden on the CPU by making a judgment by directly monitoring the operation of U.

The runaway detecting circuit in the invention of claim 5 is
An instruction that sets an arbitrary address range to be accessed and a data value next to an instruction code included in the address range when the address range is accessed, and is fetched when the address range is actually accessed Setting accuracy when determining whether the data value next to the code is the set data value by directly monitoring the CPU operation, determining the runaway state, and setting the timing for detecting the runaway state Is achieved without imposing a burden on the CPU.

The runaway detection circuit in the invention of claim 6 is
An arbitrary address range to be accessed and a range of instruction codes output or not output on the data bus when the set address range is accessed are set in advance, and the address range is accessed. If the instruction code taken into the CPU is within the set range, it is determined by directly monitoring the operation of the CPU, and the instruction code taken into the CPU is within the set range. If it is not, or if it is an instruction code, it is possible to set the timing for detecting the runaway state within a certain width without imposing a burden on the CPU by determining that the CPU is running out of control.

[0026]

【Example】

Example 1. An embodiment of the invention of claim 1 will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the runaway detection circuit of this embodiment. In the figure, 1 is a CPU (setting means), 2 is a memory, and 3 is a comparator which compares the 16-bit address data output to the address signal line 9 with the address data stored in the address register 5 (setting means) ( When the comparison result of the 16-bit address data and the address data stored in the address register 5 indicates a match, the output of the comparison result output terminal Y becomes the “H” level. Reference numeral 4 compares the 8-bit data output to the data signal line 10 with the expected value data stored in the data register 6 (setting means) when the address stored in the address register 5 is accessed. It is a comparator (runaway judgment circuit), and when the comparison result of the 8-bit data output to the data signal line 10 and the data stored in the data register 6 indicates a match, the output of the comparison result output terminal YB is' It becomes L'level. 7
Is a 2-input AND circuit (runaway determination circuit) that performs a logical product operation of the comparison result output from the comparator 3 and the comparison result output from the comparator 4, and 8 is the output of the 2-input AND circuit 7 being “H”. It is a runaway processing unit that performs runaway processing when it reaches a level. Reference numeral 11 is a register control signal line for outputting a register control signal for writing an address to the address register 5 and writing data to the data register 6.

FIG. 2 is a logic circuit diagram showing the configuration of the comparator 4, 101a, 101b, 101c, 101d, 1
Reference numerals 01e, 101f, and 101g denote exOR circuits that detect a match between each bit of the data output to the data signal line 10 and each bit of the data stored in the data register 6,
Reference numeral 102 is an OR circuit that performs a logical sum operation on the outputs of the exOR circuits and outputs the operation result.

FIG. 3 is a block diagram showing the configuration of the comparator 3, which compares the lower 8-bit address data output to the address signal line 9 with the lower 8-bit address data stored in the address register 5. A comparator 3a for
Comparator 3b for comparing the upper 8-bit address data output to address signal line 9 with the upper 8-bit address data stored in address register 5, and comparator 3
NOR circuit 1 which inverts and outputs the logical sum operation result of the signal output from the comparison result output terminal YB of a and the comparator 3b
It is composed of 03. The configurations of the comparators 3a and 3b are similar to those of the comparator 4 shown in FIG.

FIG. 4 is a logic circuit diagram showing the structure of the data register 6, which is a D flip-flop 104a, 104b, 104c, which latches each bit of 8-bit data.
It is composed of 104d, 104e, 104f, 104g and 104h. Reference numeral 107 denotes a clock signal line for outputting a clock signal for latching each bit of 8-bit data.

Next, the operation will be described. A program executed by the CPU 1 is stored in the memory 2. Although this program is various programs created by the user, it is a CPU for detecting the runaway state of the CPU 1.
An initial setting program for transferring and storing the address accessed by the normal operation of No. 1 and the expected value for the data read when the address is accessed to the address register 5 and the data register 6 at the initial stage of program execution, respectively. It is inserted at the beginning of the program. Therefore, when the CPU starts executing the program, first the address register 5 stores the address to be noticed for the runaway detection of the CPU 1, and the data register 6 accesses the address stored in the address register 5. An expected value that is expected to be output to the data signal line 10 at times is stored.

As a result, when the execution operation of the program by the CPU 1 is started, the comparator 3 compares the address stored in the address register 5 with the address output on the address signal line 9, and when they do not match, When it matches, it outputs a signal of L level, or H level from the comparison result output terminal Y to one input terminal of the 2-input AND circuit 7. Further, at this time, the comparator 4 compares the data read from the memory output to the data signal line 10 or written in the memory with the expected value data stored in the data register 6 to determine that they do not match. Then, the signal of the “H” level and the signal of the “L” level when they match are output from the comparison result output terminal YB to the other input terminal of the 2-input AND circuit 7.

Therefore, the CPU 1 is out of control and the data originally intended to be read from the address indicated by the address register is not read to the data signal line 10, or the data to be written at the address indicated by the address register 6 is the data signal line 10. When the output is not output to the output terminal, the output of the comparison result output terminal Y of the comparator 4 becomes'H 'level, the output of the 2-input AND circuit 7 also becomes'H' level, and the runaway processing unit 8 performs runaway processing. .

As described above, the runaway detection circuit of this embodiment has C
The address output to the address signal line 9 and the data output to the data signal line 10 by the operation of the PU 1 are directly monitored based on the address data stored in the address register 5 and the expected value stored in the data register 6. However, since the runaway state of the CPU is detected, it is possible to arbitrarily set the timing for detecting the runaway. Compared to the case where a timer is used as in the past, a clear instruction of the timer in the original program etc. It is no longer necessary to place
The CPU can efficiently perform the original program execution operation without increasing the load on the PU.

Embodiment 2 FIG. An embodiment of the invention of claim 2 will be described below with reference to the drawings. FIG. 5 is a block diagram showing the configuration of the runaway detection circuit of this embodiment. In FIG.
The same or corresponding parts are designated by the same reference numerals and the description thereof will be omitted.

In the runaway detection circuit of the first embodiment, when one address is accessed, the data actually output on the data signal line 10 and the data that should be originally output, that is, the so-called expected value, are matched or mismatched. While the runaway state of the CPU is determined by the detection, the runaway detection circuit of this embodiment uses the same means as the means described in the first embodiment to access a plurality of addresses, respectively. The runaway state of the CPU is determined by detecting a match or a mismatch between the data that is actually output on 10 and the data that should be output, that is, an expected value.

In FIG. 5, the comparator (3-1) corresponds to the comparator 3 in FIG. 1, and the comparator (4-1) corresponds to the comparator 4. Also, the address register (5-1)
Corresponds to the address register 5 in FIG. 1, and the data register (6-1) corresponds to the data register 6.
The AND circuit (7-1) corresponds to the AND circuit 7 shown in FIG. Comparator (3-1), comparator (4-1), address register (5-1) and data register (6-
1) and the AND circuit (7-1) must access the first address stored in the address register (5-1) and the data actually output on the data signal line 10 when the first address is accessed. Data register (6-
The runaway state of the CPU is determined by detecting whether or not the data stored in 1) matches the so-called expected value.

Further, the comparator (3-1) and the comparator (4-
1), the address register (5-1), the data register (6-1), and the AND circuit (7-1), which are connected in the same manner as the comparator (3-2) and the comparator (4-).
2), the address register (5-2), the data register (6-2) and the AND circuit (7-2) access the second address stored in the address register (5-2). The runaway state of the CPU is determined by detecting a match or a mismatch between the data actually output on the data signal line 10 and the data stored in the data register (6-2) that should be originally output, a so-called expected value. To do.

The output of the AND circuit (7-1) and the output of the AND circuit (7-2) are input to the runaway processing unit 8 via the OR circuit 21 and stored in the address register (5-1). When the address 1 is accessed, the data actually output on the data signal line 10 does not match the expected value data stored in the data register (6-1) that should originally be output, or the address register When the second address stored in (5-2) is accessed, the data actually output on the data signal line 10 and the data register (6-
The runaway process is executed when any of the mismatches with the expected value data stored in 2) is detected.

Therefore, in this embodiment, a plurality of addresses in the original program and a plurality of data output on the data line 10 when these addresses are accessed are monitored for runaway states. , CPU
It is possible to improve the responsiveness when detecting a runaway state and the reliability when a runaway is detected without imposing a burden on the.

Example 3. An embodiment of the invention of claim 3 will be described below with reference to the drawings. FIG. 6 is a block diagram showing the configuration of the runaway detection circuit of this embodiment. In FIG.
The same or corresponding parts as those in FIG.
2), (3-3) and (3-4) have the same function and configuration as the comparator 3 in FIG. Further, the address registers (5-1), (5-2), (5-3), (5-
4) also has the same function and configuration as the address register 5 shown in FIG. 31 is a comparator (3-1), (3-
2), (3-3) and (3-4) respectively corresponding address registers (5-1), (5-2), (5-3) and (5-
The address data stored in 4) and the address data output on the address line 9 are comparator (3-1) → comparator (3-2) → comparator (3-3) → comparator (3 -4) An order determination circuit for determining whether or not they match in the order.
32 is a comparison result output signal line from which a signal indicating the comparison result of the comparator (3-1) is output; 33 is a comparison result output signal line from which a signal indicating the comparison result of the comparator (3-2) is output; Three
Reference numeral 4 is a comparison result output signal line from which a signal indicating the comparison result of the comparator (3-3) is output, and 35 is a comparison result output signal line from which a signal indicating the comparison result of the comparator (3-4) is output. is there.

FIG. 7 is a logic circuit diagram showing the configuration of the order determination circuit 31, and the same parts as those in FIG. 6 are designated by the same reference numerals and the description thereof will be omitted. In the figure, 31a, 31b,
Reference numerals 31c and 31d are RS flip-flops, and the RS flip-flop 31a is set by a signal indicating the coincidence comparison result output from the comparator (3-1).
It is reset when the flip-flop 31d is set. The RS flip-flop 31b has a comparator (3-
It is set when the signal indicating the coincidence comparison result is output from 2), and the set state is released by resetting the RS flip-flop 31a. The RS flip-flop 31c is set when the RS flip-flop 31b is set and a signal indicating the coincidence comparison result is output from the comparator (3-3), and is set by resetting the RS flip-flop 31a. Is released. The RS flip-flop 31d has a comparator (3-4) in a state where the RS flip-flop 31c is set.
Is set when a signal indicating the coincidence comparison result is output from, and the set state is released by resetting the RS flip-flop 31a.

31e, 31f, 31g, 31h, 31
i and 31j are 2-input AND circuits. 31k is a 2-input AND circuit 31h, a 2-input AND circuit 31i, and a 2-input A
It is a 3-input OR circuit that calculates and calculates the logical sum of the outputs of the ND circuit 31j.

The CPU 1 and the address registers (5-1), (5-2), (5-3), (5-4) shown in FIG.
Corresponds to the address setting means.

Next, the operation will be described focusing on the order determination circuit 31 shown in FIG. First, a case where the CPU 1 is operating normally will be described. The RS flip-flop 31a shown in FIG. 7 is assumed to be initially reset when the CPU 1 is initialized or the power is turned on. Further, the address registers (5-1), (5-2), (5-
Arbitrary address data to be accessed is stored in 3) and (5-4) by the initial setting operation of the CPU 1. In the present embodiment, the address value stored in the address register is “address value stored in address register (5-1)” → “address value stored in address register (5-2)” → “address register The address values are stored in the order of "address value stored in (5-3)"->"address value stored in address register (5-4)" from the address with the earliest access timing.

When the CPU 1 executes the normal operation and the operation of reading the program, the comparator (3-1) → comparator (3-2) → comparator (3-3) → comparator (3-4) in that order. An “H” level signal indicating the coincidence comparison result is output to the order determination circuit 31. As a result, the comparator (3-
The signal indicating the result of coincidence comparison output from 1)
The flip-flop 31a is set and the gate of the 2-input AND circuit 31e opens. In this state, the comparator (3
-2) outputs a signal indicating the match comparison result,
The RS flip-flop 31b is set by the signal indicating the result of the coincidence comparison. In this way, the RS flip-flops 31a to 31d are sequentially set. RS flip-flop 31d
Is set and the Q output goes to the “H” level, this “H” level signal is supplied to the reset terminal R of the RS flip-flop 31a, so that the RS flip-flop 31a returns from the set state to the reset state. And
The signal indicating the next coincidence comparison result is comparator (3-1) → comparator (3-2) → comparator (3-3) → comparator (3-4).
Wait for output in order. CPU in the process of these series
1 is operating normally, and a signal indicating the coincidence comparison result is output in the order of comparator (3-1) → comparator (3-2) → comparator (3-3) → comparator (3-4). As long as the two inputs AND circuits 31h, 31i, and 31j are not simultaneously set to the "H" level, the 3-input OR circuit 31k outputs the "H" level runaway detection signal. There is no such thing as a runaway process.

Next, a case where the CPU 1 falls into a runaway state will be described. If the CPU 1 runs out of control, the program reading operation of the CPU 1 will be confused, and the comparator (3-1) → comparator (3-2) → comparator (3-3) → comparator (3-4) The result of the coincidence comparison in order is the order determination circuit 31.
It is thought that it will not be output to. In this case, a comparator other than the comparator (3-1) outputs a signal indicating the coincidence comparison result first to the order determination circuit 31, or one of the signals indicating the coincidence comparison result that should be output in order. In such a state, the 2-input AN is output at the time when a signal indicating one of the coincidence comparison results is output.
Both of the input terminals of the D circuits 31h, 31i, and 31j are simultaneously set to the "H" level, and the "H" level runaway detection signal is output from the 3-input OR circuit 31k, and the runaway process is performed.

As described above, in this embodiment, the comparator (3-
1) → comparator (3-2) → comparator (3-3) → comparator (3-4) in this order, it is determined whether or not a signal indicating the matching comparison result is output to the order determination circuit 31. As a result, the runaway state of the CPU 1 is detected, and it is not necessary to place a clear instruction or the like in the original program as in the conventional case, and the timing for detecting the runaway state is not imposed on the CPU. It can be set arbitrarily, and it is possible to improve the responsiveness at the time of detecting the runaway state and the accuracy of detecting the runaway state.

Example 4. An embodiment of the invention of claim 4 will be described below with reference to the drawings. FIG. 8 is a block diagram showing the configuration of the runaway detection circuit of this embodiment. In FIG.
The same or corresponding parts are designated by the same reference numerals and the description thereof will be omitted. In the figure, 41 is a comparator (3-1),
It is a 4-input OR circuit that calculates the logical sum of the signals indicating the comparison results output from (3-2), (3-3), and (3-4), and outputs the calculation result. Reference numeral 42 is an instruction code identification signal line, and when the data that the CPU is going to fetch is an instruction code, the CPU 1 outputs an instruction code identification signal of the'L 'level to this instruction code identification signal line 42. Reference numeral 43 is a 2-input AND circuit that performs a logical product operation of the output of the 4-input OR circuit 41 and the instruction code identification signal output to the instruction code identification signal line 42. In this embodiment, the address registers (5-1), (5-2), (5-3),
The address data stored in (5-4) indicates the address of the storage area of the memory 1 in which the instruction code is stored, and is set by the initial setting operation executed at the beginning of the program operation of the CPU 1.

The comparators (3-1), (3-2),
The (3-3), (3-4), the 4-input OR circuit 41, and the 2-input AND circuit 43 correspond to the instruction code determination circuit.

Next, the operation will be described. When the CPU 1 is operating normally, the address register (5-
1), (5-2), (5-3), (5-4), when the address of the memory 2 indicated by the address data stored is accessed, the instruction code is a data signal from the storage area indicated by these addresses. Read out on line 10. CP at this time
U1 outputs the'L 'level instruction code identification signal to the instruction code identification signal line 42, and as a result, the 2-input AND circuit 43
Does not output an "H" level runaway detection signal.

When the CPU 1 runs out of control, the program operation of the CPU 1 is confused and an abnormal operation is performed, and the address registers (5-1), (5-2), (5-3),
Memory 2 indicated by the address data stored in (5-4)
Even if the address is accessed, the data output to the data signal line 10 at this time may be numeric data that is not an instruction code or meaningless data.
Therefore, the instruction code identification signal output from the CPU 1 to the instruction code identification signal line 42 becomes the “H” level, and the two-input AND circuit 43 outputs the “H” level runaway detection signal. The runaway process is performed by the unit 8.

As described above, according to this embodiment, it is determined whether or not the instruction code stored in the storage area of the memory 2 indicated by the plurality of addresses respectively set by the address register is normally read. By doing CPU1
Since the runaway state of the CPU is detected, it is not necessary to place a clear instruction in the original program as in the conventional case,
It is possible to arbitrarily set the timing for detecting the runaway state without imposing a burden on the CPU, and to improve the responsiveness at the time of detecting the runaway state and the accuracy of detecting the runaway state.

Example 5. An embodiment of the invention of claim 5 will be described below with reference to the drawings. FIG. 9 is a block diagram showing the configuration of the runaway detection circuit of this embodiment. In FIG. 9, FIG.
The same or corresponding parts are designated by the same reference numerals and the description thereof will be omitted. In the figure, 51 and 52 are comparators,
The comparator 51 compares the address data A output to the address signal line 9 with the address data B stored in the address register 53. When address data A> address data B, the comparison result output terminal Y0 is'H '. A level signal is output, and when address data A <address data B, an'H 'level signal is output to the comparison result output terminal Y1. The comparator 52 also has a similar function. Reference numeral 55 is a two-input AND circuit that calculates the logical product of the signals output from the comparator 51 and the comparator 52 and outputs the calculation result. The output of the 2-input AND circuit 55 is 3
It is configured to be supplied to one of the input terminals of the input AND circuit 57 and also supplied to the CPU 1.

Reference numeral 56 is a comparison data register, which stores an expected value for determining whether or not the data value output on the data signal line 10 in the comparator 58 is an expected data value. In this embodiment, this expected value is "F
It is set to "F". Further, the comparator 58 has the same function as the comparator 4 shown in FIG. Reference numeral 59 is a data check signal line from which a data check signal is output from the CPU 1, and when the CPU 1 knows that it is an area for performing data check from the signal output from the 2-input AND circuit 55, the instruction code in this area When the next data is taken in, an'H 'level data check signal indicating that the data is to be checked is output to the data check signal line 59.

The address data stored in the address registers 53 and 54 and the expected value stored in the comparison data register 56 are set by the initial setting operation executed at the beginning of the program operation of the CPU 1.

FIG. 10 is a block diagram showing the configuration of the comparator 51. 51a, 51b, 51c, 51d and 51e are address data A output on the address signal line 9 and address data stored in the address register 53. It is a 1-bit comparator that compares each bit of B. 51f and 51g are inverter circuits.

FIG. 11 shows the 1-bit comparator shown in FIG.
For example, it is a logic circuit diagram showing a configuration of a 1-bit comparator 51a. The other 1-bit comparators have the same circuit configuration. In the figure, reference numeral 61 is a comparison result signal line for outputting the comparison result (address data A> address data B) regarding the 1-bit magnitude relationship between the address data A and the address data B of the upper 1-bit comparator, and 62 is the same. Is a comparison result signal line for outputting the comparison result (A <B), and 63 is a comparison result signal line for similarly outputting the comparison result (A = B). Reference numeral 64 is a comparison address data bit signal line for outputting 1-bit data of the address data A, and 65 is a comparison address data bit signal for outputting 1-bit data of the address data B having the same digit as the address data A. It is a line.

Reference numeral 66 designates an exNOR circuit which inverts and outputs the coincidence operation result of the address data A and address data B, 67 an inverter circuit which inverts the address data B, 68 an inverter circuit which inverts the address data A, and 69 70 is a 3-input AND circuit, 71 is a 2-input AN
D circuit, 72 is a comparison result (A> B) of the upper comparator and 3
A 2-input OR circuit which performs a logical sum operation with the output of the input AND circuit 69 and outputs the operation result, and 73 is a logic between the comparison result (A <B) of the upper comparator and the output of the 3-input AND circuit 70. A two-input OR circuit that performs a sum operation and outputs the operation result. 74 is a comparison result output signal line for outputting the operation result of the 2-input OR circuit 72 to the comparison result output terminal (A> BOUT), and 75 is the operation result of the 2-input OR circuit 73 to the comparison result output terminal (A <BOUT). A comparison result output signal line for outputting, and a comparison result output signal line for outputting the operation result of the 2-input AND circuit 71 to the comparison result output terminal (A = BOUT).

The address register 5 shown in FIG.
Reference numerals 3 and 54 correspond to the address range setting means, and the comparison data register 56 corresponds to the data value setting means.
The D circuit 57 and the comparator 58 correspond to the check data judging circuit, and the CPU 1 corresponds to the address range setting means and the data value setting means.

Next, the operation will be described. When the CPU 1 is operating normally, the address value output to the address signal line 9 is included in the range between the value of the address data stored in the address register 53 and the value of the address data stored in the address register 54. 2 inputs A only if
The output of the ND circuit 55 becomes'H 'level. Since the output of the 2-input AND circuit 55 is at the "H" level, the CPU 1 knows the area for data check, and that data is the data to be checked when fetching the data next to the instruction code in this area. An “H” level data check signal indicating that is output to the data check signal line 59. Further, the comparator 58 includes the comparison data register 5
The expected value stored in 6 is compared with the data output on the data signal line 10, and if they match, a signal of'L 'level is output from the comparison result output terminal YB to the 3-input AND circuit 57.

Therefore, it is expected that the CPU 1 is operating normally and the data next to the instruction code within the address range defined by the value of the address data stored in the address registers 53 and 54 is stored in the comparison data register 56. As long as it matches the value, the output of the 3-input AND circuit 57 does not become the “H” level, and the runaway process is not performed.

When the CPU 1 goes into a runaway state, the CPU
The program operation of No. 1 is confused and causes an abnormal operation, and the data next to the instruction code within the range defined by the value of the address data stored in the address registers 53 and 54 is stored in the comparison data register 56. It is thought that it will not match the expected value. Therefore, in this state, the output of the 3-input AND circuit 57 becomes the "H" level at the timing when the "H" level data check signal is output, and the runaway process is performed.

As described above, according to the present embodiment, the data next to the instruction code within the address range defined by the values of the address data stored in the address registers 53 and 54 is expected to be stored in the comparison data register 56. Since it determines whether or not it matches the value and detects the runaway state of the CPU 1, it has a significant influence on the setting accuracy when arbitrarily setting the timing for detecting the runaway state and on the occurrence of a part of the data. It is possible to improve the detection accuracy for a slight runaway without a load on the CPU.

Example 6. An embodiment of the invention of claim 6 will be described below with reference to the drawings. FIG. 12 is a block diagram showing the configuration of the runaway detection circuit of this embodiment. 12, parts that are the same as or correspond to those in FIG. 9 are assigned the same reference numerals and explanations thereof are omitted. In the figure, 81 is the data signal line 10.
This is a comparator that compares the 8-bit instruction code data output above and the instruction code stored in the comparison instruction code setting register 83, and is configured similarly to the comparators 51 and 52. 82 is output to the data signal line 10
The comparator is a comparator that compares the instruction code data of bits and the instruction code stored in the comparison instruction code setting register 84, and is configured similarly to the comparators 51 and 52. In this embodiment, the comparison instruction code setting register 83 stores the instruction code “F0”, the comparison instruction code setting register 84 stores the instruction code “10”, and these instruction codes and the address registers 53 and 54. The stored address data is written and stored by the initial setting operation executed at the initial stage of the program operation of the CPU 1. Further, the comparison instruction code setting registers 83 and 84
The range defined by the instruction code written in the CPU is the CPU when the address range defined by the value of the address data of the address registers 53 and 54 is accessed.
1 shows a range of instruction codes that are never used by normal operation.

Reference numeral 85 is a 2-input O which performs a logical sum operation of the comparison results of the comparator 81 and the comparator 82 and outputs the operation result.
The R circuit 86 is an instruction code identification signal line through which an instruction code identification signal of the'L 'level is output when the CPU 1 fetches the instruction code. 87 is an inverter circuit that inverts the instruction code identification signal, 88 is the output of the 2-input AND circuit 55, the output of the 2-input OR circuit 85, and the inverter circuit 87.
ANDs the output of and outputs the operation result 3
It is an input AND circuit.

The CPU 1 and the comparison instruction code setting registers 83 and 84 correspond to the instruction code setting means, and the comparators 81 and 82 and the 3-input AND circuit 88 correspond to the instruction code range determination circuit.

Next, the operation will be described. When the CPU 1 is operating normally, the address registers 53, 5
The instruction code in the address range defined by the value of the address data of 4, that is, the comparison instruction code setting register 8
Since the instruction code in the range defined by the instruction code written in 3, 84 is not used, the address data in the range defined by the value of the address data in the address registers 53, 54 is placed on the address signal line 9. The instruction code output on the data signal line 10 at the time of output does not include the instruction code in the range defined by the instruction codes written in the comparison instruction code setting registers 83 and 84. Since the comparison result output terminal Y0 of the comparator 81 does not output an "H" level signal, and the comparison result output terminal Y1 of the comparator 82 does not output an "H" level signal, the output of the 2-input OR circuit 85 is output. Becomes "L" level, the output of the 3-input AND circuit 88 does not become "H" level, and the runaway process is not executed.

On the other hand, when the CPU 1 goes into a runaway state, it is defined by the instruction code in the address range defined by the value of the address data of the address registers 53, 54, that is, the instruction code written in the comparison instruction code setting registers 83, 84. It is conceivable that an instruction code in the range specified may be output on the data signal line. Therefore,
It is determined that the CPU has runaway by detecting this state. That is, the CPU 1 falls into a runaway state and the instruction code in the address range defined by the value of the address data in the address registers 53, 54, that is, the instruction in the range defined by the instruction code written in the comparison instruction code setting registers 83, 84. When the code is read from the memory 2, this instruction code is output to the data signal line 10. The instruction code output to the data signal line 10, which should not be used originally, is detected by comparing the instruction code stored in the comparison instruction code setting registers 83 and 84 by the comparator 81 and the comparator 82 with each other. Is'H '
The level signal is output to the 2-input OR circuit 85. At this time, the CPU 1 outputs an “L” level instruction code identification signal, which is inverted by the inverter circuit 87 and used as a “H” level instruction code identification signal by a 3-input AND.
It is output to the circuit 88. As a result, the 3-input AND circuit 8
A runaway detection signal of'H 'level is output from 8 and the runaway process is executed.

As described above, according to the present embodiment, the CPU 1 falls into the runaway state and the instruction code in the address range defined by the value of the address data of the address registers 53 and 54, that is, the comparison instruction code setting registers 83 and 84, is stored. By determining whether or not the instruction code within the range defined by the written instruction code is read, the CPU 1
Since the runaway state is detected, it is possible to set the timing of detecting the runaway state for the instruction code with a range without burdening the CPU.

In the embodiment described above, the range defined by the instruction codes written in the comparison instruction code setting registers 83, 84 is the address registers 53, 54.
When the address range defined by the value of the address data is accessed, the instruction code range that is never used by the normal operation of the CPU 1 is shown.
The range defined by the instruction code written in is the range of the instruction code that must be used by the normal operation of the CPU 1 when the address range defined by the address data values of the address registers 53 and 54 is accessed. May be configured as follows.

[0071]

As described above, according to the first aspect of the invention, an expected value for an arbitrary address of a storage unit accessed by the CPU and data output on the data bus when the address is accessed. And a runaway of the CPU by determining a match between data actually output on the data bus when the CPU accesses the address and an expected value set by the setting means. Since the state is determined, the timing for detecting the runaway state can be arbitrarily set, and a runaway detection circuit that does not increase the load on the CPU can be obtained.

According to the second aspect of the present invention, a plurality of arbitrary addresses of the storage unit accessed by the CPU and the data respectively output on the data bus when the plurality of addresses are accessed and the corresponding data The CPU is configured to detect the runaway state by directly monitoring the CPU operation based on the expected value, so the timing to detect the runaway state can be set arbitrarily and the responsiveness when detecting the runaway state is improved. Thus, there is an effect that a runaway detection circuit with improved reliability in detecting a runaway state can be obtained.

According to the third aspect of the present invention, the address setting means for setting a plurality of arbitrary addresses of the storage unit accessed by the CPU, and the addresses set by the address setting means are accessed in a predetermined order. Since it is configured to include an order determination circuit that determines the runaway state of the CPU by determining whether or not the runaway state is detected, the timing for detecting the runaway state can be set arbitrarily, and
There is an effect that a runaway detection circuit that can improve the response at the time of detecting the runaway state and the accuracy of detecting the runaway state can be obtained.

According to the fourth aspect of the present invention, the address setting means for setting an arbitrary address storing the instruction code of the storage unit accessed by the CPU, and the address set by the address setting means are accessed. An instruction code determination circuit for determining the runaway state of the CPU by determining whether or not the data taken in by the CPU is an instruction code, and is configured to detect the runaway state by directly monitoring the operation of the CPU. Therefore, there is an effect that a runaway detection circuit capable of improving the responsiveness at the time of detecting the runaway state and the detection accuracy of the runaway state can be obtained.

According to the invention of claim 5, an address range setting means for setting an arbitrary address range of the storage unit accessed by the CPU, and an address range setting means for accessing the address range set by the address range setting means Data value setting means for setting the next data value of the instruction code included in the address range, and data set by the data value setting means for the next data value of the instruction code fetched when the address range is accessed. Since it has a check data judging circuit for judging the runaway state of the CPU by judging whether it is a value or not, and is configured to detect the runaway state by directly monitoring the operation of the CPU,
There is an effect that a runaway detection circuit that can improve the setting accuracy when setting the timing for detecting the runaway state without imposing a load on the CPU is obtained.

According to the invention of claim 6, address range setting means for setting an arbitrary address range of the storage section accessed by the CPU, and data when the address range set by the address range setting means is accessed. The instruction code setting means for setting the range of the instruction code output on the bus or not output, and the instruction code fetched by the CPU when the address range is accessed by the instruction code setting means. An instruction code range determination circuit for determining the runaway state of the CPU by determining whether or not the instruction code is within a set range, and is configured to detect the runaway state by directly monitoring the operation of the CPU. Therefore, there is an effect that a runaway detection circuit can be obtained which has a certain width and can set the timing when the runaway state is detected. That.

[Brief description of drawings]

FIG. 1 is a block diagram showing a runaway detection circuit according to an embodiment of the present invention.

FIG. 2 is a logic circuit diagram showing a configuration of a comparator for comparing 8-bit data output on a data signal line of a runaway detection circuit according to an embodiment of the invention of claim 1;

FIG. 3 is a logic circuit diagram showing a configuration of a comparator for comparing 16-bit address data output on the address signal line of the runaway detection circuit according to the first embodiment of the invention.

FIG. 4 is a logic circuit diagram showing a configuration of a data register used for comparing 8-bit data output on a data signal line of the runaway detection circuit according to the embodiment of the invention of claim 1;

FIG. 5 is a block diagram showing a runaway detection circuit according to an embodiment of the invention of claim 2;

FIG. 6 is a block diagram showing a runaway detection circuit according to an embodiment of the present invention.

FIG. 7 is a logic circuit diagram showing an order determination circuit of a runaway detection circuit according to an embodiment of the invention of claim 3;

FIG. 8 is a block diagram showing a runaway detection circuit according to an embodiment of the invention of claim 4;

FIG. 9 is a block diagram showing a runaway detection circuit according to an embodiment of the invention of claim 5;

FIG. 10 is a block diagram showing a comparator for comparing address data output on an address signal line of a runaway detection circuit according to an embodiment of the invention of claim 5;

FIG. 11 is a logic circuit diagram showing a 1-bit comparator which constitutes a comparator for comparing address data output on the address signal line of the runaway detection circuit according to the embodiment of the invention of claim 5;

FIG. 12 is a block diagram showing a runaway detection circuit according to an embodiment of the present invention.

FIG. 13 is a block diagram showing a conventional runaway detection circuit.

[Explanation of symbols]

1 CPU (setting means, address setting means, address range setting means, data value setting means, instruction code setting means) 2 memory (storage unit), 3-1, 3-2, 3-
3, 3-4 Comparator, 41 4 input OR circuit, 43 2
Input AND circuit (instruction code judgment circuit), 3, 4 comparator, 7 2-input AND circuit (runaway judgment circuit), 5 address register, 6 data register (setting means), 5-
1, 5-2, 5-3, 5-4 address register (address setting means), 9 address signal line (address bus), 10 data signal line (data bus), 31 sequence determination circuit, 53, 54 address register ( Address range setting means), 56 comparison data register (data value setting means), 57 3 input AND circuit, 58 comparator (check data determination circuit), 83, 84 comparison instruction code setting register (instruction code setting means), 81, 82 comparator, 88 3 input AND circuit (instruction code range determination circuit).

Claims (6)

[Claims] 1. A runaway state that does not follow a program of a single-chip microcomputer including at least a CPU, a storage unit, and a data bus and an address bus connecting the CPU and the storage unit on the same semiconductor substrate is detected. In the runaway detection circuit, an arbitrary address of the storage unit accessed by the CPU and setting means for setting an expected value for data output on the data bus when the address is accessed; And a runaway determination circuit for determining the runaway state of the CPU by determining whether the data output on the data bus when the address is accessed matches the expected value set by the setting means. Characteristic runaway detection circuit. 2. The setting means sets an expected value for an arbitrary plurality of addresses of a storage unit accessed by a CPU and data output on a data bus when the plurality of addresses are accessed. The runaway detection circuit according to claim 1, wherein: 3. A runaway state that does not follow a program of a single-chip microcomputer including at least a CPU, a storage unit, and a data bus and an address bus connecting the CPU and the storage unit on the same semiconductor substrate is detected. In the runaway detection circuit, the address setting means for setting an arbitrary plurality of addresses of the storage section accessed by the CPU and whether or not the addresses set by the address setting means are accessed in a predetermined order. And a sequence determination circuit that determines the runaway state of the CPU by determining the runaway detection circuit. 4. A runaway state that does not follow a program of a single-chip microcomputer including at least a CPU, a storage unit, and a data bus and an address bus connecting the CPU and the storage unit on the same semiconductor substrate is detected. In the runaway detection circuit, an address setting means for setting an arbitrary address storing the instruction code of the storage section accessed by the CPU, and the CPU when the address set by the address setting means is accessed A runaway detection circuit, comprising: an instruction code determination circuit for determining the runaway state of the CPU by determining whether or not the data is an instruction code. 5. A runaway state that does not follow a program of a single-chip microcomputer including at least a CPU, a storage unit, and a data bus and an address bus connecting the CPU and the storage unit on the same semiconductor substrate is detected. In the runaway detection circuit, address range setting means for setting an arbitrary address range of the storage section accessed by the CPU, and the address range set by the address range setting means is included in the address range when accessed. Data value setting means for setting the next data value of the instruction code to be read, and whether the data value next to the instruction code fetched when the address range is accessed is the data value set by the data value setting means. Check day to judge the runaway state of the CPU by judging whether or not A runaway detection circuit comprising a data determination circuit. 6. A runaway state that does not follow a program of a single-chip microcomputer including at least a CPU, a storage unit, and a data bus and an address bus connecting the CPU and the storage unit on the same semiconductor substrate is detected. In the runaway detection circuit, an address range setting means for setting an arbitrary address range of the storage section accessed by the CPU and the data bus when the address range set by the address range setting means are accessed. Instruction code setting means for setting a range of instruction codes that are output or not output,
An instruction code for determining the runaway state of the CPU by determining whether the instruction code fetched by the CPU when the address range is accessed is within the range set by the instruction code setting means. A runaway detection circuit comprising a range determination circuit.