JPH11143732A - Microcomputer and emulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency of debugging. SOLUTION: This device is provided with a first means 321 for generating identification information for identifying the destination of restoration after the interrupting processing according to whether interruption is generated in a user mode or a debug mode, and second means 322 for determining the destination of restoration after the end of the interruption processing based on the identification information. Thus, the proper destination of restoration can be determined based on the identification information Thus, it is possible to attain the acceptation of the interruption in the debug mode, and to achieve the improvement of the efficiency of debugging.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an emulation technique for supporting the development of software operating on a user system, a microcomputer enabling the emulation, and an emulator including the microcomputer.

[0002]

2. Description of the Related Art In the development of microcomputer application equipment, an emulator is used for debugging an application system (user system) and performing detailed evaluation of the system. The emulator is connected to the user system under development and supports detailed system debugging.

In debugging a user system, a function of stopping (breaking) the execution of a program when a predetermined condition is satisfied is one of the basic functions of the emulator.

When a break instruction or a break signal is input to the microcomputer during execution of the user program, the mode is changed from the user program mode to the debug mode. Using this function, a break function of the user program is realized. When an instruction at a specific address of the user program is replaced with a break instruction, or when a break signal is generated due to a condition of an address bus or a data bus matching a specific condition, control is returned from the user mode to the debugger ( (“ASE”) mode. When the control is shifted to the ASE mode, the debugger program is operated to display the contents of the registers and the memory. At this time, the execution of the user program has been stopped.

As an example of a document describing an emulator, “Everything about microcomputer development (pages 78 to 9)” issued by Denpa Shimbun on June 20, 1989.
5)).

[0006]

However, according to the above-mentioned break function, it is necessary to accept the transition to the ASE mode even when the user program is processing the highest-priority interrupt. Also need to be high. Therefore, when the execution of the user program is stopped (during debug mode)
In order to accept an interrupt under a certain condition, it is necessary to return control to the user program once. FIG. 7 shows a state of the control. If an interrupt occurs during the execution of the user program, the mode transits to the ASE mode and the debugger program is started. The debugger program then displays the register at the time of the break and changes the contents of the memory in response to a new request. Here, the user program is in a waiting state for re-execution. In order to receive the interrupt processing in this state, it is necessary to shift to the user program mode. However, since the currently stopped user program cannot be executed, the interrupt processing cannot be basically received.

Therefore, an infinite loop program irrelevant to the stopped user program is executed in the user space, and an interrupt is accepted during the execution of the infinite loop. However, in this method, the operation of the debugger program must be performed before the infinite loop is executed after the break occurs, and an interrupt cannot be accepted in real time because there is an interrupt disabled period. Therefore, when a program different from the stopped program performs data transmission / reception processing by an interrupt, and when the interrupt occurs during the interrupt disabled period in FIG. Therefore, data transfer errors may occur, or in the case of a system for controlling equipment such as a motor, the rotation control of the motor may become abnormal and the user system may be damaged, resulting in a significant decrease in debugging efficiency. Can be considered.

An object of the present invention is to provide a technique for accepting an interrupt in real time.

Another object of the present invention is to improve debugging efficiency.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a first mode in which a debugger program is executed and a second mode in which a user program is executed
A first means for generating identification information capable of identifying a return destination after the interrupt processing in accordance with whether an interrupt has occurred in the first mode or in the second mode. 321) and a second means (322) for determining a return destination after the end of the interrupt processing based on the identification information.

According to the above means, the second means can determine an appropriate return destination based on the identification information. That is, when the processing of the interrupt accepted in the first mode is completed, the mode can return to the first mode, and after the processing of the interrupt accepted in the second mode is completed, the mode returns to the second mode. You can return. Therefore, as compared with the case where a program of an infinite loop irrelevant to the user program stopped by the break is executed in the user space and an interrupt is received during the execution of the infinite loop (see FIG. 7),
Interrupts can be accepted immediately after a break, which achieves improved debugging efficiency.

Further, by providing a register dedicated to the first mode that can be used only in the first mode, separately from the register used in the second mode, information already written in the second mode can be stored in the first mode. Can be prevented from being destroyed.

Further, when a system including the microcomputer having the above configuration is not provided with a sufficient function for debugging the system, an emulator including the microcomputer and an emulator main body coupled to the microcomputer is installed. It is good to configure.

[0015]

FIG. 1 shows a configuration example of an emulator according to the present invention.

The emulator shown in FIG. 1 is not particularly limited, but includes a microcomputer 301 mounted on the user system 30 and this microcomputer 30.
1 and an emulator main body 20 coupled to the main body 1.

The microcomputer 301 has a debug interface 314 that enables input / output of data in a serial format. The microcomputer 301 is not specifically developed for emulation but is a so-called real chip. At the edge of the board in the user system 30, the debug interface 3 of the microcomputer 301 is provided.
14 and an external terminal 300 for enabling signal exchange between the emulator main body 20 disposed outside the user system 30 and a cable 9.
The emulator main body 20 is connected to the external terminal 300 via the terminal.

The emulator main body 20 is configured as follows.

A read only memory (ROM) 202 in which a control program and the like are stored in advance, the ROM 202
A microprocessor 203 that enables emulation by executing a program in the internal memory, and a dual-port random access memory (DPRAM) 20 that enables exchange of various data with the outside.
4. A static random access memory (SRAM) 205 serving as a work area for processing in the microprocessor 203, a first-in first-out random access memory capable of temporarily storing data in a first-in first-out format ( FIFO / RAM) 21
1. Controller 21 for controlling data input / output
0 are communicably connected to each other via a bus BUS. Controller 210 and external terminal 2
A signal level interface 209 is provided between the emulator 20 and the signal level 08 for matching the signal level used in the user system 30 with the signal level used in the emulator main body 20. The emulator main body 20 is provided with a host interface 201 for enabling a signal to be exchanged with the host system 10 arranged outside, and the host system 10 is connected via the host interface 201. Have been. A personal computer can be applied to the host system 10.

The setting of emulation conditions for the microcomputer 301 can be performed from the host system 101. Information regarding the execution of the user program by the microcomputer 301 is taken in the emulator main body 20 in a serial format via the cable 9 and transferred to the host system 10 as necessary.

FIG. 2 shows the microcomputer 301
Is shown.

The microcomputer 30 shown in FIG.
Although not particularly limited, 1 is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

CPU for executing a predetermined program
(Central processing unit) 302, FP for floating point operation
A U (coprocessor) 304 is provided. CPU3
02 and the FPU 304, an MMU (memory management unit) and a cache memory unit 305 are coupled. The MMU and cache memory unit 305 includes an instruction cache 306 for caching instructions fetched from outside, an operand cache 308 for caching operands, and an MMU 307 for performing conversion between physical addresses and logical addresses. . An instruction signal (32 bits) and load data (32 bits) are sent from the MMU and cache memory unit 305 to the CPU 302.
Is transmitted and processed by the CPU 302. Also, C
The next instruction address (32 bits), operand address (32 bits), and store data (32 bits) are output from the PU 302 to the MMU and the cache memory 305. Load data (lower 32 bits) and store data (32 bits) are also transmitted to the FPU 304.

A bus state controller 315 is provided. Under the control of the bus state controller 315, the MMU and cache memory unit 305 and a direct memory access controller (DMAC) 317 are provided.
, An external bus interface 316 and a peripheral circuit 319
Bus state control is performed in data transfer between the device and the like. A physical address (29 bits) and data (32 bits) are sent from the MMU and cache memory unit 305 and DMAC 317 to the bus state controller 315.
Bit) is input. External bus interface 316
, And an input / output of data (64 bits) becomes possible.

The peripheral circuit 319 includes an emulation unit (EMU) 30 that enables emulation.
9. A clock generation circuit (CPG) 310 for forming a clock signal of a predetermined frequency, an interrupt controller (INTC) 311 for performing interrupt control, a serial communication interface (SCI) 312 for enabling data exchange in a serial format And a timer unit (TMU) 313 for measuring various times.

The emulation unit 309 includes:
In debugging the user system 30, serial data can be exchanged with the emulator main body 20 via the debug interface 314.

In debugging a user system, a break controller (AB) for stopping (breaking) a user program when a break condition is satisfied.
C) 303 is built in.

FIG. 3 shows an example of the configuration of the CPU 302.

As shown in FIG. 3, this CPU 302
Includes an ASE control logic 321 for controlling operation in the ASE mode, an instruction processing unit 322 for decoding a fetched instruction, and an arithmetic processing unit 323 for performing a predetermined arithmetic processing based on a decoded output of the instruction. And a register section 324 including a plurality of registers. The instruction signal (32 bits) is input to the instruction processing device 322, where it is decoded. The load data (32 bits) is input to the arithmetic processing unit 323, and the instruction processing unit 322
Is provided to the arithmetic processing based on the result of decoding. Various registers in the register unit 324 are used in this arithmetic processing. The arithmetic processing unit 323 outputs the following instruction address (32 bits), operand address (32 bits), and store data (32 bits) as the arithmetic processing result there.
Bit) is output.

The register section 324 has four types of registers, MISC, R0U to R15U, R0P to R7P, and R0.
A to RA7. R0U to R15U, R0P to R7P
Are general-purpose registers used during normal processing in the CPU 302, R0A to R7A are general-purpose registers dedicated to the ASE mode, and MISK is another register. General purpose registers R0A to R7A dedicated to ASE mode
Can be accessed only in the ASE mode, and cannot be used in the user mode or the privileged mode. As described above, the general-purpose register dedicated to debugging (R0A
-R7A) is provided in order to avoid referring to the registers respectively damaged in the ASE mode or the interrupt processing.

The register MISK includes an emulation program counter EPC used to save the value of the program counter when an ASE exception or an interrupt occurs.
An emulation status register used to save the value of the status register when an ASE exception or an interrupt occurs, and an emulation base register EBR used to save the value of the base register when an ASE exception or an interrupt occurs are included.

FIG. 4A shows the ASE mode control logic 32.
FIG. 4B shows a specific signal exchanged between the ASE mode control logic 321 and the instruction processing device 322.

As shown in FIG. 4B, the instruction processing unit 322 generates an RTE instruction establishment signal, an RTB instruction establishment signal, an ASE exception establishment signal, an exception processing establishment signal other than ASE, and the like. Mode control logic 32
When input to 1, the logic of the ASE mode signal or the ASE-R mode signal is determined by the combinational logic in the logic circuits 101 and 102.

Here, the RTE instruction and the RTB instruction are both return instructions. The former means return from the privileged mode to the user mode or ASE mode, whereas the latter means return from the ASE mode to the user mode. Is different. The ASE mode signal is a signal indicating whether the current mode is the user mode or the ASE mode. A high-level signal is denoted by A1, and a low-level signal is denoted by A0. The ASE-R mode signal is a signal indicating a return destination by a return instruction when an interrupt is accepted in the ASE mode. R1 when the signal is at a high level and R0 when the signal is at a low level.

As shown in FIG. 4A, the ASE mode control logic 321 determines the logic of the next state according to the logic state of the input signal and the previous state.
02. The next output state of the logic circuits 101 and 102 (referred to as “next state”) is output to the instruction processing device 322 via the flip-flops FF1 and FF2 at the subsequent stages. The flip-flops FF1 and FF2 are interposed so that the ASE mode signal, unless the next state is changed,
And the logic state of the ASE-R signal. In the control logic 101, an ASE exception processing establishment signal, an exception establishment signal other than ASE, an RTE instruction establishment signal,
The next state of the ASE mode signal is determined based on the ASE-R mode signal, the RTB command establishment signal, and the previous state of the control circuit 101.

The control logic 101 will be described.

When the ASE exception processing establishment signal is at the high level (indicated by the logical value "1"), the next state becomes the logical value "1" regardless of the logical states of the other signals, which is the flip-flop FF1. Is output via.

When the ASE exception processing signal is at a low level (indicated by a logical value "0") and an exception establishment signal other than ASE is at a high level, the next signal is applied regardless of the logic state of other signals. The state is set to low level.

ASE exception processing signal is low level, ASE
If the exception establishment signal is a low level, the RTE instruction establishment signal is a high level, and the ASE-R mode signal is a low level, the next state is a low level, and the ASE-R
When the R mode signal is at a high level, the next state is at a high level.

When the ASE exception processing signal is low level, ASE
If the exception establishment signal other than the above is low level and the RTE instruction establishment signal is low level and the RTB instruction establishment signal is high level, the next state is low level.

ASE exception processing signal is low level, ASE
If the exception establishment signal is a low level, the RTE instruction establishment signal is low level, the RTB instruction establishment signal is low level, and the previous state of the ASE mode signal is low level (A0), The state is also low level, and when the ASE mode signal is high level (A1), the next state is also high level.

The control logic 102 will be described.

When the ASE exception establishment signal is at a high level,
Regardless of the logic state of the other signals, the next state of the ASE-R mode signal is at the high level.

When the ASE exception establishment signal is at a low level and the RTB instruction establishment signal is at a high level,
The next state is a low level.

When the ASE exception establishment signal and the RTB instruction establishment signal are at a low level, and the previous state of the ASE-R mode signal is at a low level, the next state is at low level, and the ASE-R mode signal Is high, the next state is high.

FIG. 5 shows control logic 10 as described above.
The microcomputer 3 when the logic of the ASE mode signal and the logic of the ASE-R mode signal are determined
01 state transition is shown.

In FIG. 5, A0 and A1 denote AS, respectively.
The logic of the E mode signal is shown, A0 indicates that the logic of the signal is at a low level, and A1 indicates that the logic of the signal is at a high level. R0 and R1 indicate the logic of the ASE-R mode signal, respectively.
0 indicates that the logic of the signal is low, and R
1 indicates that the logic of the signal is at a high level.

A0 indicates a user program mode, and A1 indicates an ASE mode. Also, R0
Indicates that the interrupt has occurred in the user program mode, and R1 indicates that the interrupt has occurred in the ASE mode. This example shows a case where the user program mode includes a user mode and a privileged mode.

A0 and R0 are set by a power-on reset, a manual reset, and a TLB (showing the table of the MMU 307) multiple hits.

The mode shifts from the user mode to the privileged mode when an interrupt occurs, and shifts to the mode when the interrupt occurs when an interrupt return instruction (RTE) occurs. In other words, when the interrupt occurs, in the case of the user mode, the mode returns to the user mode, and in the privilege mode, the mode returns to the privilege mode of that level. Normally, the user program operates on A0 and R0. When an interrupt occurs in this state, the mode transits to the privilege mode of the user program.
At this time, they are A0 and R1. When the RTE instruction is executed in this state, the mode returns to the ASE mode instead of the user mode. The return address is an address stored using the stack or the ASE dedicated registers (R0A to R7A) as in the normal interrupt processing. As described above, since the return destination is determined based on the ASE mode signal and the ASE-R mode signal, the interruption in the ASE mode can be accepted without any trouble.

FIG. 6 shows the relationship between the ASE mode signal, the ASE-R mode signal, and the exception processing.

According to the logic of the ASE-R mode signal and the ASE mode signal, the ASE exception processing and the RTB instruction paired therewith, the general exception processing and the RT paired therewith
An E instruction is generated.

Here, consider the case where the same general-purpose register is used in both the ASE mode and the user mode as shown in FIG. In this case, the registers that have been destroyed in the ASE mode or interrupt processing are referred to. That is, if the same register is used in the ASE mode and the user mode, the ASE mode
When the mode is shifted to the user mode for interrupt processing, the existing register value is destroyed, and an undesired register value is referred to in this interrupt processing. Also, even after returning to the ASE mode by the interrupt return instruction, the destroyed register value is referred to. To prevent this, it is necessary to save the register value before the emulator program allows the interrupt and return it to the register referenced by the user program. If such a process is added, the interrupt cannot be accepted at an arbitrary timing, and the acceptance of the interrupt process is delayed.

On the other hand, as in the above example, the AS
General-purpose registers (R0A to R7) available only in E mode
By providing A), it is possible to avoid referring to registers that have been destroyed in the ASE mode or interrupt processing. That is, if different general-purpose registers are used in the user mode and the ASE mode, destruction of the register value can be avoided.

According to the above embodiment, the following functions and effects can be obtained.

(1) As described above, when an infinite loop program unrelated to the stopped user program is executed in the user space and an interrupt is accepted during the execution of the infinite loop, it is necessary to wait until the interrupt is accepted. Since the operation of the debugger program is required, interrupts cannot be accepted in real time. For this reason, when a program other than the stopped program performs data transmission / reception processing by interruption, a data transfer error occurs there, or in the case of a system for controlling equipment such as a motor, motor rotation control is performed. There is a possibility that the user system may be damaged due to an abnormality, and the debugging efficiency may be significantly reduced. However, according to the microcomputer 301, when the processing of the interrupt accepted in the ASE mode is ended, the microcomputer 301 can return to the ASE mode, and the processing of the interrupt accepted in the user mode is ended. Thereafter, the mode can return to the user mode. For this reason, as compared with the case where the infinite loop program unrelated to the user program stopped by the break is executed in the user space and the interrupt is accepted during the execution of the infinite loop as described above, the program is executed after the break. Since the interrupt can be immediately accepted, it is possible to avoid an abnormality in the rotation control of the motor in the control of the motor and the like, and to improve the efficiency of debugging. Debugging efficiency can be improved.

(2) In addition to the registers used in the user mode, by providing general-purpose registers that can be used only in the ASE mode, the destruction of register information can be avoided even when interrupt processing is performed.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, by providing a register for masking an interrupt in the ASE mode, the interrupt in the ASE mode can be suppressed.

Further, nesting of interrupts can be supported by stacking A0, A1, R0, and R1, which are the states of the ASE mode signal and the ASE-R signal, in the memory.

FIG. 8 shows a case where interrupt nesting is supported.

Each time an interrupt occurs, A
Stack x, Rx (x is 0 or 1). The mode returned when the RTE instruction is executed follows the latest stacked Ax, R (x means 0 or 1).

In the above description, the case where the invention made by the present inventor is applied to an emulator, which is the field of application as the background, has been mainly described. However, the present invention is not limited to this. The present invention can be applied to a case where a debugging function is provided.

The present invention can be applied on the condition that it has at least a first mode in which a debugger program is executed and a second mode in which a user program is executed.

[0065]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the first means (and the interrupt processing means for generating identification information capable of identifying the return destination after the interrupt processing according to whether the interrupt has occurred in the first mode or the second mode) By providing the second means for determining the return destination after the termination based on the identification information, it is possible to determine an appropriate return destination based on the identification information. When the processing of the interrupt that has been terminated is completed, the mode can return to the first mode, and after the processing of the interrupt accepted in the second mode is completed, the mode can return to the second mode. Thus, an interrupt can be accepted immediately after a break, thereby improving debugging efficiency.

By providing a register dedicated to the first mode that can be used only in the first mode, separately from the register used in the second mode, information already written in the second mode can be stored in the first mode. Can be prevented from being destroyed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an emulator according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a microcomputer included in the emulator.

FIG. 3 is a block diagram illustrating a configuration example of a CPU included in the microcomputer.

FIG. 4 is a block diagram illustrating a configuration example of a main part of the CPU.

FIG. 5 is an explanatory diagram of state transition of the microcomputer.

FIG. 6 is an explanatory diagram showing a relationship between exception processing and a return instruction in the microcomputer.

FIG. 7 is an explanatory diagram of a system that enables acceptance of an interrupt by executing an infinite loop.

FIG. 8 is an explanatory diagram of a state when interrupt nesting is supported.

FIG. 9 is an explanatory diagram of register destruction in debugging.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Host system 20 Emulator main body 30 User system 301 Microcomputer 302 CPU 303 Break controller 304 FPU 306 Instruction cache 307 MMU 308 Operand cache 314 Debug interface 321 ASE mode control logic 322 Instruction processing unit 324 Register processing unit 323 Arithmetic processing unit

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Osamu Nishii 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. Central Research Laboratory

Claims (3)

[Claims] A first program for executing a debugger program;
A microcomputer having a mode and a second mode in which a user program is executed, wherein a return destination after the interrupt processing is identified depending on whether an interrupt has occurred in the first mode or in the second mode. A microcomputer comprising: first means for generating possible identification information; and second means for determining a return destination after completion of the interrupt processing based on the identification information. 2. A register dedicated to a first mode, which can be used only in the first mode, separately from a register used in the second mode, and the register dedicated to the first mode is a general-purpose register in the first mode. The microcomputer according to claim 1, which is used as a microcomputer. 3. An emulator comprising: the microcomputer according to claim 1; and an emulator main body coupled to the microcomputer and capable of debugging a system including the microcomputer.