JPH05158872A - Data processor - Google Patents

Abstract

PURPOSE:To easily attain a debug by clarifying the discrimination of a stage requesting an activated bus access. CONSTITUTION:An encoder 9 encodes bus access permission signals 5a and 5c-5e outputted by the bus access adjustment of a bus interface part 3. Then, the input of the bus access permission signal 5a for an IF stage '00', the input of the bus access permission signal 5c for an A stage 2c '01', the input of the bus access permission signal 5d for an F stage 2d '10', and the input of the bus access permission signal 5e for an E stage 2e '11' are outputted as a BAS signal 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device having a plurality of means for performing bus access and means for arbitrating the bus access of each means and performing data processing by pipeline processing.

[0002]

2. Description of the Related Art Generally, each instruction is executed by fetching an instruction, decoding an instruction, calculating an operand address, fetching operand data, executing an operation, writing a result, etc.
The operation is completed after several cycles of sequential operation. In order to achieve high-speed processing, some data processing apparatuses have conventionally performed these operations in a divided and streamlined manner.
There is a pipeline processing mechanism that executes a plurality of instructions simultaneously at the same time and ideally obtains the execution result of one instruction for each cycle (execution time of one sequential operation).

FIG. 5 is a functional block diagram of a data processing device having a conventional pipeline processing mechanism. In FIG. 5, reference numeral 1c denotes this conventional data processing device, which has the respective components described below. 2a fetches an instruction, that is, an IF stage as a first requesting means for requesting bus access for instruction fetch, and 2b decodes an instruction received from the IF stage 2a, that is, generates an instruction code and an address calculation information code. Instruction decode stage (hereinafter referred to as D stage) 2c as means for performing operand address calculation by the address calculation information code generated in D stage 2b, and if necessary, bus access for operand address information fetch (other than instruction fetch) Operand access calculation stage (hereinafter referred to as A stage) 2d as a second requesting means for requesting the bus access)
Operand fetch stage (hereinafter referred to as F stage) as a second request means for fetching from the effective address of the operand calculated in the stage 2c, that is, requesting bus access for operand fetch, 2e is an operand fetch or instruction as required. This is an instruction execution stage (hereinafter referred to as E stage) for executing an instruction as a second requesting means for requesting a bus access for storing an execution result in an operand address. Reference numeral 3 denotes a bus access request for an instruction fetch generated from the IF stage 2a, a bus access request for an operand address information fetch generated from the A stage 2c, a bus access request for an operand data fetch generated from the F stage 2d, and an operand data fetch generated from an E stage 2e. And a bus interface unit as an arbitration unit that arbitrates the bus access request of the operand data store. Of the bus access requests from the stages 2a and 2c to 2e, the E stage 2e has the highest priority, and then the F stage 2
The priority decreases in the order of d, A stage 2c, and IF stage 2a. The bus interface unit 3 also performs bus access according to the arbitration result.

Next, the operation will be described. Each stage 2
a and 2c to 2e, when performing bus access, the IF stage 2a sends the bus access request signal 4a to the A stage 2
c inputs the bus access request signal 4c, the F stage 2d inputs the bus access request signal 4d, and the E stage 2e inputs the bus access request signal 4e to the bus interface unit 3. The bus interface unit 3 arbitrates the bus access request of each of the stages 2a and 2c to 2e, and selects the bus access request of one stage based on the above priority order. When the IF stage 2a is selected, the bus access permission signal 5a is sent to the IF stage 2a, and when the A stage 2c is selected, the bus access permission signal 5c is sent to the A stage 2
When the F stage 2d is selected for c, the bus access permission signal 5d is set to the F stage 2d, and when the E stage 2e is selected, the bus access permission signal 5e is set to the E stage 2e.
Input each. Bus access permission signals 5a and 5c
The stage that receives ~ 5e is the bus interface unit 3
Fetch or store by bus access activated by. Reference numeral 7 is a read / write signal (indicated as R / W (inversion) in the figure) indicating the input / output of the bus access,
It goes high when input (read) and goes low when output (write). Reference numeral 6 is a bus access type signal (hereinafter referred to as BAT signal) indicating whether or not the bus access is an instruction fetch.
It becomes low level when accessing data.

FIG. 6 is a diagram showing an example of the flow of instruction processing and bus cycles in each stage when the conventional data processing device 1c shown in FIG. 5 performs pipeline processing. In the first cycle, the IF stage 2a inputs the bus access request signal 4a to the bus interface unit 3, and the bus interface unit 3 sends the bus access permission signal 5a to I.
The F stage 2a receives the instruction A, and the IF stage 2a fetches the instruction A via the bus interface unit 3. In the second cycle, instruction A is sent to D stage 2b,
Is decoded. In the second cycle, at the same time, the IF stage 2a inputs the bus access request signal 4a to the bus interface unit 3, the bus interface unit 3 inputs the bus access permission signal 5a to the IF stage 2a, and the IF stage 2a outputs the instruction B. It is fetched via the interface unit 3. In the third cycle, the processing of instruction A is A
Proceeding to stage 2c, processing of instruction B proceeds to D stage 2b. Bus access request signal 4a from IF stage 2a
However, the bus access request signal 4c is input from the A stage 2c to the bus interface unit 3, respectively. The bus interface unit 3 selects the A stage 2c as a result of the arbitration, inputs the bus access permission signal 5c to the A stage 2c, and the A stage 2c fetches the operand address information of the instruction A via the bus interface unit 3. There is. Fourth
In the cycle, the operand address of the instruction A is calculated in the A stage 2c, and the processing of the instruction B is performed in the A stage 2
Since c is not empty, it is waiting on the D stage 2b. The bus access request of the IF stage 2a waiting in the third cycle is accepted by the bus interface unit 3, the bus access permission signal 5a is input to the IF stage 2a, and the IF stage 2a operates in the bus interface unit 3
The instruction C is fetched via. In the fifth cycle, each processing of the instruction A, the instruction B, and the instruction C proceeds to the F stage 2d, the A stage 2c, and the D stage 2b, respectively. Bus access request signal 4a from IF stage 2a
However, the bus access request signal 4d is input from the F stage 2d to the bus interface unit 3. The bus interface unit 3 selects the F stage 2d as a result of arbitration, inputs the bus access permission signal 5d to the F stage 2d, and the F stage 2d fetches the operand data of the instruction A via the bus interface unit 3. .

In this way, the processing of each of the stages 2a to 2e is performed for each cycle, and when the bus access requests overlap with each other, they are arbitrated according to the priority, and the bus access requests of low priority are made to wait. .. Further, even if the next stage is not available, the processing is waited.

In the first to seventh cycles and the ninth cycle, the bus access is a read operation, so the read / write signal 7 is at a high level, and in the eighth cycle, the bus access is a write operation. Therefore, the read / write signal 7 is at low level. In the first cycle, the second cycle, the fourth cycle, and the seventh cycle, the bus access is an instruction fetch,
The BAT signal 6 is at the high level, and the third cycle, the fifth cycle, the sixth cycle, the eighth cycle, the ninth cycle.
In the cycle, the BAT signal 6 is at the low level because the bus access is not the instruction fetch but the bus access for the operand.

Therefore, in debugging, if the read / write signal 7 and the BAT signal 6 are monitored for bus access, it is possible to distinguish between the read operation and the write operation and whether or not the instruction is fetched.

[0009]

However, in the conventional data processing apparatus for performing the bipline processing as described above, there is a time lag between the fetching of an instruction and the completion of the processing, and a plurality of instructions are simultaneously processed. To process,
The order of bus access is very complicated. Therefore, when performing debugging, regarding the bus access, even if the read operation and the write operation are distinguished and whether the instruction is fetched or not, the stage that requested the bus access cannot be distinguished, and the instruction processing in the bipline is not recognized. There is a problem that it is difficult to judge the flow and it is difficult to debug.

The present invention has been made in order to solve the above-mentioned problems, and makes clear the distinction of the request means (stage) that has requested the bus access regarding the activated bus access, and the flow of instruction processing during the bipline. It is an object of the present invention to provide a data processing device that facilitates debugging by facilitating the above determination.

[0011]

A data processing apparatus according to the invention of claim 1 is an arbitration means (bus interface section 3).
The requesting means (IF stage 2a, A stage 2) requesting the bus access selected by
c, F stage 2d, E stage 2e) is further provided with type output means (encoder 9) for outputting a signal indicating the type to the outside.

A data processing apparatus according to a second aspect of the invention is
When the type specifying means (register 13) for specifying the type of each requesting means for requesting bus access and the bus access request of the requesting means specified by this type specifying means are selected by the arbitration means (bus interface unit 3) Break means for breaking data processing (comparator 1
1) and are further provided.

[0013]

According to the first aspect of the invention, the requesting means (IF stage 2a, A stage) that has requested the bus access to the bus access selected by the arbitration means (bus interface unit 3), that is, the activated bus access. Two
Since the signal (bus access stage signal 8) indicating the type of c, F stage 2d, E stage 2e) is output from the type output means (encoder 9), the bus access operation can be performed by monitoring the signal. The distinction between the requesting means that has requested is clarified.

In the second aspect of the invention, when the bus access request of the requesting means designated by the type designating means (register 13) is selected by the arbitration means (bus interface unit 3), the data processing break means (comparator). 1
Since the break is caused by 1), it becomes possible to set a break point with respect to the activation of the bus access by the request of any requesting means.

[0015]

【Example】

Example 1. FIG. 1 is a functional block diagram of a data processing device having a pipeline processing mechanism according to an embodiment of the present invention. In FIG. 1, components corresponding to those shown in FIG. 5 are designated by the same reference numerals, and their description will be omitted. In FIG. 1, reference numeral 9 denotes a type of requesting means that has requested the bus access for the bus access selected by the bus interface unit 3, that is, a bus indicating the distinction between the IF stage 2a, the A stage 2c, the F stage 2d, and the E stage 2e. This is an encoder as a type output means for outputting the access stage signal 8 to the outside. The bus access stage signal (hereinafter referred to as BAS signal) 8 is composed of 2 bits in this embodiment.

Next, the operation will be described. Here, the description of the operation which is the same as the conventional one is omitted, and the characteristic operation of this embodiment will be described. When the IF stage 2a is selected by the bus access arbitration of the bus interface unit 3, the bus interface unit 3 outputs the bus access permission signal 5
a to the IF stage 2a and encoder 9
To enter. When the A stage 2c is selected by the bus access arbitration of the bus interface unit 3, the bus interface unit 3 inputs the bus access permission signal 5c to the A stage 2c and the encoder 9. When the F stage 2d is selected by the bus access arbitration of the bus interface unit 3, the bus interface unit 3 inputs the bus access permission signal 5d to the F stage 2d and the encoder 9. When the E stage 2e is selected by the bus access arbitration of the bus interface unit 3, the bus interface unit 3 inputs the bus access permission signal 5e to the E stage 2e and the encoder 9. The encoder 9 encodes the bus access permission signals 5a and 5c to 5e, and outputs "00" when the bus access permission signal 5a is input and "01" when the bus access permission signal 5c is input. "10" is output as the BAS signal 8 when the signal 5d is input, and "11" when the bus access permission signal 5e is input. Therefore, when performing the bus access requested by the IF stage 2a, the BAS signal 8 is set to "0".
When the bus access requested by the A stage 2c to "0" is performed, the BAS signal 8 is "01", and when the bus access requested by the F stage 2d is performed, the BAS signal 8 is "1".
When the bus access requested by the E stage 2e is made to "0", the BAS signal 8 becomes "11".

FIG. 2 is a diagram showing an example of the flow of instruction processing and bus cycle in each stage of the data processing apparatus of the embodiment of FIG. Except for the flow of changes in the BAS signal 8 in the embodiment shown in FIG. 2, this is the same as the conventional example shown in FIG. In FIG. 2, in the first cycle, the second cycle, the fourth cycle, and the seventh cycle, since the bus access is the instruction fetch by the IF stage 2a, the BAS signal 8 is "00".
In the third cycle and the sixth cycle, since the bus access is the fetch of the operand address information by the A stage 2c, the BAS signal 8 is "01". Fifth
In the cycle and the ninth cycle, since the bus access is the fetch of the operand data by the F stage 2d,
The BAS signal 8 is “10”. In the eighth cycle, the bus access is a write of the execution result by the E stage 2e, so the BAS signal 8 is "11".

In the data processing device 1a having the pipeline processing mechanism configured as described above, the bus access started by monitoring the BAS signal 8 is clearly discriminated from the stage requesting the bus access. it can.

Example 2. FIG. 3 is a functional block diagram of a data processing device having a pipeline processing mechanism according to an embodiment of the present invention. In FIG. 3, components corresponding to those shown in FIG. 1 are designated by the same reference numerals, and their description will be omitted. In FIG. 3, 10 is a data processing device 1b.
A control unit (not shown in FIGS. 1 and 5) for controlling the whole, 13 is a 2-bit register as a type designating unit for designating the type of each requesting unit requesting bus access, 11 is a register 13 This is a comparator as a break means for breaking the data processing when the bus access request of the request means specified by is selected by the bus interface unit 3.

Next, the operation will be described. This Example 2
In, the operation related to the generation of the BAS signal 8 is the same as the operation shown in the first embodiment. Break "00" when a break occurs when a bus access occurs in the IF stage 2a, "01" when a break occurs when a bus access occurs in the A stage 2c, and break when a bus access occurs in the F stage 2d. When calling "1
"0" is written to the register 13 from the outside when a break is applied when the bus access of the E stage 2e occurs. The comparator 11 uses the BAS signal 8 and the register 1
The contents of 3 are compared, and if they match, the hit signal 12 is input to the control unit 10. Upon receiving the hit signal 12, the control unit 10 controls the data processing device 1b to perform break processing.

FIG. 4 is a diagram showing an example of the flow of instruction processing and bus cycle in each stage of the data processing apparatus 1b according to the embodiment shown in FIG. Figure 4 shows register 1
The operation when “10” is written in No. 3 is shown. The operation from the first cycle to the fifth cycle is the same as that of the first embodiment shown in FIG. In the first cycle and the second cycle, since the BAS signal 8 is "00", the comparator 11 does not output the hit signal 12. Third
In the cycle, since the BAS signal 8 is “01”, the comparator 11 does not output the hit signal 12. In the fourth cycle, since the BAS signal 8 is “00”, the comparator 11
Does not output the hit signal 12. In the fifth cycle, the BAS signal 8 becomes "10", so the comparator 11
Inputs the hit signal 12 to the control unit 10. Control unit 10
Since the hit signal 12 is received, the control is performed so that the break processing is performed, and after the sixth cycle, the data processing device 1
b performs break processing.

In the data processing device 1b having the pipeline processing mechanism configured as described above, it is possible to set a breakpoint for the activation of the bus access by the request of an arbitrary stage.

Example 3. In the first embodiment, the encoder 9 encodes the bus access permission signals 5a and 5c to 5e and outputs the BAS signal 8. However, the encoder 9 is not used, but the bus access permission signals 5a and 5c to 5e.
The same effect can be obtained by outputting e to the external terminal. Therefore, the concept of the type output means referred to in claim 1 is not limited to the encoder, and it is sufficient if the signal indicating the type of the requesting means that has requested the bus access is output to the outside. In this case, the external terminal outputs the type. You can think of it as a means.

In the second embodiment, the 2-bit register 1
3, the encoder 9 provides a bus access permission signal 5
Although the BAS signal 8 is generated by encoding a and 5c to 5e, the bus access permission signals 5a and 5c to 5e and 4 are provided without using the encoder 9.
Similar effects can be obtained by comparing the contents of the bit registers.

In the second embodiment described above, the writing of the register 13 is performed from the outside, but the data processing device 1
Even if the register 13 is written by the instruction processed by b, the same effect can be obtained.

In the above-described first and second embodiments, the case where the pipeline mechanism of five stages is provided and four stages request the bus access is shown, but the number of stages of the pipeline and the stages requesting the bus access are shown. It goes without saying that there is no limit to the number of bits, and it is obvious that this can be dealt with by increasing or decreasing the number of bits of the BAS signal 8 and the number of bits of the register 13.

[0027]

As described above, according to the invention of claim 1,
The bus access selected for the bus access selected by the arbitration means is provided with the type output means for outputting the signal indicating the type of the requesting means to the outside. Therefore, the bus access is requested for the activated bus access. It is possible to clearly distinguish the required requesting means, easily determine the flow of instruction processing in the pipeline, and therefore, to easily and efficiently perform debugging.

Further, according to the invention of claim 2, the break means is provided for breaking the data processing when the bus access request of the request means designated by the type designation means is selected by the arbitration means. A breakpoint can be set for the activation of the bus access by the request of the arbitrary requesting means, and therefore, the effect that the debugging can be performed easily and efficiently is obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing functional blocks of a data processing device having a pipeline processing mechanism according to an embodiment of the invention of claim 1;

FIG. 2 is a diagram showing an example of a flow of instruction processing and a bus cycle in each stage of a data processing device having a pipeline processing mechanism according to an embodiment of the invention of claim 1;

FIG. 3 is a diagram showing functional blocks of a data processing device having a pipeline processing mechanism according to an embodiment of the invention of claim 2;

FIG. 4 is a diagram showing an example of a flow of instruction processing and a bus cycle in each stage of a data processing device having a pipeline processing mechanism according to an embodiment of the invention of claim 2;

FIG. 5 is a diagram showing an example of functional blocks of a data processing device having a conventional pipeline processing mechanism.

FIG. 6 is a diagram showing an example of a flow of instruction processing and a bus cycle in each stage when a conventional data processing device performs pipeline processing.

[Explanation of symbols]

 1a, 1b Data Processing Device 2a IF Stage (First Requesting Means) 2c A Stage (Second Requesting Means) 2d F Stage (Second Requesting Means) 2e E Stage (Second Requesting Means) 3 Bus Interface Unit (Arbitration means) 9 Encoder (type output means) 11 Comparator (break means) 13 Register (type designation means)

Claims (2)

[Claims] 1. A data processing device for processing data by pipeline processing, comprising: first requesting means for requesting bus access for instruction fetch; and a plurality of second requesting means for requesting bus access other than instruction fetch. And an arbitration unit that arbitrates the bus access requests of the first request unit and the second request unit, and further indicates the type of request unit that has requested the bus access for the bus access selected by the arbitration unit. A data processing device comprising a type output means for outputting a signal to the outside. 2. A data processing device for processing data by pipeline processing, comprising first request means for requesting bus access for instruction fetch, and a plurality of second request means for requesting bus access other than instruction fetch. A arbitration unit that arbitrates the bus access requests of the first request unit and the second request unit, and further, a type designation unit that designates the type of each request unit that requests the bus access, and the type designation unit. And a break means for breaking the data processing when the bus access request of the request means designated by the arbitration means is selected by the arbitration means.