JP2990800B2 - Interrupt processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing method, and particularly to an interrupt processing method by an interrupt controller and a central processing unit when an incomplete interrupt occurs.

[Conventional technology]

In an information processing system, a central processing unit (hereinafter abbreviated as a processor) needs to exchange information with some input / output devices (hereinafter abbreviated as I / O) in addition to a memory. To improve system throughput,
Service to O is provided by an interrupt. An I / O requiring service from the processor activates an interrupt request signal to the processor. When the processor in the interrupt enabled state recognizes the occurrence of the interrupt by the interrupt request signal, it suspends the execution of the previous program and transfers control to the interrupt processing program (interrupt service routine). I do.

If there are many I / Os in the information processing system,
Uses an interrupt controller that arbitrates interrupt requests from each I / O according to priority and transmits them to the processor.
The interrupt controller receives interrupt request signals from several I / Os and notifies the processor of the presence or absence of an interrupt request. This notification signal is called an INT signal. The processor inputs IN from outside the processor until the execution of one instruction is completed and the execution of the next instruction is started.
When the T signal is sampled and the INT signal is active and the processor is in the interrupt accepting state, the processor starts an internal interrupt accepting process and first outputs an interrupt accepting signal. Upon receiving the interrupt acceptance signal, the interrupt controller generates a vector containing information that can identify the interrupt request source that has issued the highest priority interrupt request among the active interrupt request signals at that moment. Return to processor. The processor branches to the service routine corresponding to the interrupt request source by analyzing the vector obtained from the interrupt controller.

FIG. 14 is a block diagram of an information processing system including a processor and an interrupt controller. Ten
1 is a processor, 1002 is an interrupt controller capable of processing eight interrupt requests, 103 is one I / O, 104
Is an interrupt request signal from the I / O 103, 105 is the INT signal from the interrupt controller 102, 106 is an interrupt acceptance signal from the processor 101, and 107 is a data bus of the information processing system.

Hereinafter, a case is considered where the processor 101 is in a state in which an interrupt can be accepted, and only one interrupt request 104 from one I / O 103 is active in the interrupt controller 1002. When the interrupt request 104 from the I / O 103 becomes active, the INT signal 105 from the interrupt controller 1002 becomes active and notifies the processor 101 that an interrupt request has occurred.

As shown in FIG. 15, after the processor 101 samples the INT signal at 1101 and detects that the INT signal is active, the I / O 10 until the interrupt acceptance signal 106 is output.
When the interrupt request 104 from 3 is active, the following normal interrupt processing is performed. Processor
When the 101 accepts an interrupt, the interrupt accept bus
Two cycles are started continuously. In each interrupt acceptance bus cycle, processor 101 outputs interrupt acceptance signal 106 to interrupt controller 1002. In the first interrupt acceptance bus cycle, the interrupt controller 1002 determines to request the processor 101 to service the interrupt request input having the highest priority level among the active interrupt request inputs. In this example, since only one interrupt request 104 is active, the interrupt controller 1002 determines to request the service for the interrupt request 104 from the processor 101 in the first interrupt acceptance bus cycle. In the second interrupt acceptance bus cycle, the interrupt controller 1002 sets the data bus 10
7 outputs a vector including the priority of the interrupt request 104, and the processor 101 receives the vector. Processor 1
In step 01, the information indicating the running state of the program interrupted by the program counter and the interrupt is saved on the stack, and then the process branches to the interrupt service routine for the I / O 103 by the vector.

The vector passed from the interrupt controller 1002 to the processor 101 has the format shown in FIG. 1201 is from interrupt controller 1002 to processor 10
This is the 8-bit wide vector passed to 1. Reference numeral 1202 denotes a 5-bit portion corresponding to an address in the vector 1201.
Set for 2 Reference numeral 1203 denotes a portion obtained by encoding the priority level of the interrupt request in the vector 1201 into 3 bits. The interrupt controller 1002 assigns eight levels of priority to the eight interrupt requests, and encodes the priority level of the interrupt request to be serviced in the eight interrupt requests into three bits when the processor 101 receives the interrupt. And the vector 1 to the processor 101
Shown at 1203 in 201. In this example, for example, I / O103
When an interrupt request 104 is to be connected to the interrupt request input pin corresponding to the priority three levels of interrupt controller from, 011 ₂ binary enters the 1203 in the vector 1201 against interrupt request 104.

The processor 101 generates a 16-bit address 1204 using the vector 1201 obtained from the interrupt controller 1002. The address 1204 indicates the position of the entry corresponding to the priority level of the interrupt request 104 in the vector table prepared in the memory. In this example, each entry in the vector table indicates the position of the entry. In this example, it is assumed that each entry in the vector table stores information on the start address of the service routine of the interrupt of the priority level indicated by the entry. First processor 10
1 accesses the entry specified by the vector in the vector table to obtain information on the start address of the interrupt service routine. Next, control is transferred to the start address of the interrupt service routine based on the information.

FIG. 18 is a diagram showing a flow of a conventional interrupt process. Each time the processor 101 completes execution of one instruction, the processor 101 determines whether or not the INT signal from the interrupt controller 1002 is active.
1 starts the interrupt acceptance bus cycle twice in succession, and fetches the vector from the interrupt controller 1002 in the second interrupt acceptance bus cycle. Processor 10
1 accesses the entry of the service routine for the interrupt in the vector table using the vector, and obtains information on the start address of the service routine for the interrupt. Next, the processor 101 saves the program counter and the stack indicating the running state of the program interrupted by the interrupt, and then transfers the control to the start address of the service routine corresponding to the interrupt.
When the processing for the interrupt in the service routine is completed, the information such as the program counter saved on the stack is restored from the stack by executing a return instruction from the interrupt written at the end of the service routine. Control is returned to the program interrupted by the interrupt.

As shown in FIG. 17, at 1301, the processor 101
When the signal 105 was sampled, the interrupt request 104 from the I / O 103 was active, but when the processor 101 output the interrupt acceptance signal, the interrupt request 104 from the I / O 103 was inactive. Sometimes, the interrupt controller 1002 outputs a vector indicating the source of the interrupt request to the processor in response to the input of the interrupt acceptance signal 106.
Cannot return to 101. An interrupt input at the timing shown in FIG. 17 is called an incomplete interrupt. An incomplete interrupt occurs when an I / O independently generates or deletes an interrupt request.

In the conventional interrupt processing method, when an incomplete interrupt occurs, the interrupt controller 1002 gives the processor 101 to the processor 101 during the interrupt acceptance bus cycle a priority level determined to be used when the incomplete interrupt occurs (for example, level 7). Output the interrupt vector corresponding to
The processor 101 receives the interrupt vector without knowing that the interrupt is an incomplete interrupt, and directly performs the incomplete interrupt process as one of the normal interrupt processes described in FIG.

In other words, due to an incomplete interrupt generated by erasing the interrupt request issued by the interrupt request source I / O 103 itself, the processor 101 suspends the execution of the program up to that point at the point where the incomplete interrupt is received. Then, the information such as the program counter is saved on the stack, the incomplete interrupt vector is analyzed, the information of the start address of the incomplete interrupt processing routine is obtained from the vector table, and the control is transferred to the incomplete interrupt processing routine.

[Problems to be solved by the invention]

In the conventional interrupt processing method, the interrupt controller can detect that an incomplete interrupt has occurred.
Since the processor cannot identify the interrupt level at which the interrupt request has occurred, there is no particular processing to be performed in the incomplete interrupt processing routine. In an application field that requires immediacy and timeliness for I / O processing, it is necessary to specify at which interrupt level an interrupt request was generated when an incomplete interrupt occurred. In the conventional interrupt processing method, each I / O that issues an interrupt request is polled one by one in the incomplete interrupt processing routine.
Has to be checked, and the immediacy and timeliness of I / O processing are significantly impaired.

In a conventional interrupt controller, an interrupt request input terminal corresponding to a priority level determined to be used when an incomplete interrupt occurs (level 7 in the above-described conventional example) is substantially connected to an I / O in the system. And the like.

[Means for solving the problem]

An interrupt processing device according to the present invention includes a central processing unit, an interrupt controller, and a plurality of input / output devices, wherein an interrupt request from the input / output device is input to the interrupt controller, and the interrupt controller is configured to control the plurality of input / output devices. Arbitrates an interrupt request from a device and outputs an interrupt request signal to the central processing unit. When the central processing unit receives the interrupt from the interrupt controller, the central processing unit starts an interrupt receiving bus cycle for the interrupt controller, and In the information processing system, the control outputs an interrupt vector to the central processing unit during the interrupt receiving bus cycle. In the information processing system, a register 1 inside the interrupt controller, to which a value is set from the central processing unit, and a content of the register 1 Means 2 for outputting a value different from Selecting means 3 which receives the outputs of the register 1 and the means 2 as inputs, and means 4 for determining the priority of active interrupt requests from the plurality of input / output devices and outputting the value of the highest priority interrupt request level. Means 5 for holding information on the presence / absence of an interrupt request from the input / output device; means 6 for receiving the output of the holding means 5 to determine the priority and outputting the value of the highest priority interrupt request level; Selecting means 7 for inputting the output of the means 4, inputting the means 6 and the output, and means 8 for detecting that there is no interrupt request from the input / output device inside the interrupt controller. After the central processing unit receives an interrupt request from the interrupt controller, the detecting means 8 controls the selecting means 3 and the selecting means 7 simultaneously with respect to the interrupt receiving bus cycle. It is in, and selects whether to generate an interrupt vector should be generated from the output of register 1 contents and means 4, or from the output of the output means 6 of the device 2.

Further, the interrupt processing device has a register 9 inside the interrupt controller for setting a value from the central processing unit, and determines the priority of an interrupt request from the input / output device based on the contents of the register 9. Control means, means for masking an interrupt request from the input / output device based on the contents of a register 9 and inputting the interrupt request to the detecting means 8, and masking the output of the holding means 5 based on the contents of the register 9 Means for inputting to the means 6.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a connection method between a processor, an interrupt controller, and an I / O according to a first embodiment of the present invention, which is similar to the connection method of the conventional example.

101 is a processor, and 102 is an interrupt controller improved in this embodiment. 103 is an I / O for issuing an interrupt request to the interrupt controller 102, 104 is an interrupt request signal from the I / O 103 to the interrupt controller 102, and 105 is an INT signal from the interrupt controller 102 to the processor 101. 106
Is an interrupt acceptance signal from the processor 101 to the interrupt controller 102. An external bus 107 connects the processor 101, the interrupt controller 102, and the I / O 103.

The hardware inside the interrupt controller 102 will be described. 108 is an 8 from the outside of the interrupt controller 102
This circuit detects that all the interrupt request signals are inactive. When all eight interrupt request signals are inactive, the output signal 110 becomes "1". Reference numeral 108 denotes an 8-input NOR circuit, for example. Used to detect incomplete interrupts. A circuit 109 inverts only the least significant bit in the 5-bit output of the register 111. 110 is an output signal of the detection circuit 108. A register 111 stores 5-bit address information set by the processor 101. Usually, the processor 101 connects to the external data bus 107 and the interrupt controller 1 before accepting an interrupt from the interrupt controller 102.
The 5-bit address information is stored in the register 111 via the internal data bus 02. 112 is a selector and a register
The output of 111 and the output of 109 are input, the signal 108 is used as a selection signal, and when the signal 108 is '1', the output of 109 is selected.
When 108 is '0', select 111 output and use internal data bus
Output to 118 bits 3,4,5,6,7. Reference numeral 113 denotes a priority determination circuit which receives eight interrupt request signals from the outside of the interrupt controller 102. A priority determination circuit which detects the highest priority interrupt request among the active interrupt requests among the eight interrupt request signals to be input and encodes it into 3 bits. Reference numeral 114 denotes a priority determination circuit. 113 3-bit output. An 8-bit register 115 holds the state of each of the eight interrupt request signals from the outside of the interrupt controller 102. Each bit of the 8-bit register is set to 1 at the rising edge of each interrupt request signal. The processor 101 is reset by the falling edge of the second active pulse of the interrupt reception signal 106 which becomes active twice following the second interrupt reception bus cycle of the two consecutive interrupt reception bus cycles activated by the processor 101. You. Reference numeral 116 denotes a priority encoder which receives the output of the 8-register 115 as an input, and detects the position of the bit having the highest priority among the bits set to "1" in the output of the 8-bit register 115. Encode to 3 bits and output.

A selector 117 receives the 3-bit outputs 114 and 116 of the priority determining circuit 113 and the 3-bit output of the input 116, uses the signal 108 as a selection signal, and sets the priority when the signal 108 is "1".
The output of the encoder 116 is selected, and when the signal 108 is “0”, the 3-bit output 114 of the priority determination circuit 113 is selected and output to the bits 0, 1, and 2 of the internal data bus 118. An internal bus 118 of the interrupt controller 102 is an 8-bit bus.

When the interrupt controller 102 is notified by the INT signal 105 that an interrupt has occurred to the processor 101 in this embodiment, the processor 101 starts the interrupt receiving bus cycle twice in succession. Like the conventional interrupt controller, the interrupt controller 102 uses the interrupt acceptance signal 106 output accompanying the first interrupt acceptance bus cycle only for determining the priority of the interrupt inside the interrupt controller, and is used twice. The vector is fetched into the processor 101 via the external bus 107 in the interrupt receiving bus cycle. The format of the vector is the same as the format 1204 of the vector output in the conventional interrupt acceptance bus cycle.

In the present embodiment, 11100 is stored in the register 111 for the following description.
It is assumed that ₂ is preset. 109 is register 11
Output 109 for inverting only the least significant bits in the 5-bit output of 1 has a 11101 _2. The interrupt controller 102 receives an interrupt request from only one I / O 103, and the interrupt request signal 104 of the I / O 103
It is assumed that it is connected to the 02 interrupt priority level 3.

For normal interrupts other than incomplete interrupts, the interrupt controller 102 issues the following 8-bit vector to the processor 101 via the external bus 107. In the case of a normal interrupt, that is, when the processor 101 starts the first interrupt receiving bus cycle of the two interrupt receiving bus cycles after sampling the INT signal, even if there is one interrupt request signal to the interrupt controller 102, If active, 110 becomes '0', so selector 112
(In this example, 11100 ₂ ) is selected. Also selector 11
7 selects the output 114 of the priority determination circuit 113. In this example, the interrupt request signal 104 of the I / O 103 is the interrupt controller 102
Because it is connected to the interrupt priority level 3 is output 114 of the priority order determination circuit 113 has a 011 _2.

In FIG. 3, a vector 301 is a vector issued for a (second) interrupt receiving bus cycle of a normal interrupt. The part 1202 in the vector 301 is processor 1
5-bit address information (11100 _{2 in} this example) preset from 01. 1203 of the vector 301 corresponds to a 3-bit priority level (0111 _{2 in} this example).

One of two interrupt acceptance bus cycles when an incomplete interrupt occurs, that is, due to the processor 101 sampling the active INT signal 105 at the timing 201 as shown in the timing chart of FIG. When all the interrupt request inputs to the interrupt controller 102 are inactive when the interrupt acceptance bus cycle is started, the interrupt controller 102 issues the following 8-bit vector to the processor 101: . After the processor 101 samples the INT signal at timing 201, one of two interrupt acceptance bus cycles
If all the interrupt request signals to the interrupt controller 102 are inactive at the timing 202 before the start of the second interrupt acceptance bus cycle, 1
10 becomes '1'. In this embodiment, I / O103 interrupt request signal 104 is up timing 202 because it is connected to the interrupt priority level 3 interrupt controller 102 the priority decision circuit 113 outputs the 011 _second timing 202
Thereafter, an undefined value is output. Register 115
Shows the interrupt request signal connected to priority level 3.
Only the bit 3 is set by the rising edge of 104, and even after the interrupt request signal 104 connected to the priority level 3 becomes inactive at the timing 202, the interrupt request signal connected to the priority level 3 becomes inactive.
Since that had 104 rising edge bit 3 of register 115 is storing, priority encoder 116 until the falling edge of the second interrupt acceptance signal rising edge after the interrupt request signal 104 011 ₂ Is output. Since the timing 110 is “1” after the timing 202, the selector 112 selects the contents of the register 109 (11101 _{2 in} this example). Selector 117 is priority encoder 116
Output (in this example 011 ₂₎ Select. In FIG. 3, a vector 302 is a vector issued for a (second) interrupt receiving bus cycle of a normal interrupt.

As shown in FIG. 4, the vector address 1204 for a normal interrupt in this embodiment is 03800H based on FIG.
The vector address 1204 for incomplete interrupts is in the range 03A00H to 03BC0H. In the present embodiment, the processor 101 uses the conventional interrupt control method, and when the incomplete interrupt occurs or the normal interrupt occurs, the processor 101 outputs the INT signal according to the flow shown in FIG. After sampling, the acceptance bus cycle is started by two interrupts, and the vector table is accessed based on the vector fetched in the second interrupt acceptance bus cycle to branch to the target vector address. It is possible. Especially when an incomplete interrupt occurs,
In the second interrupt acceptance bus cycle, the vector for the incomplete interrupt is issued from the interrupt controller 102, and the corresponding interrupt request level in the incomplete interrupt vector table shown in FIG. Access the entry you want. The corresponding entry in the incomplete interrupt vector table stores the start address of the incomplete interrupt processing routine of each interrupt level.

FIG. 5 is a view showing a second embodiment of the present invention. In the second embodiment, the register 509 that determines the entry of the vector table for the incomplete interrupt can set the value from the processor 101. This makes it possible to place the vector table at any location in the memory, increasing the flexibility in constructing the system.

 FIG. 6 shows a third embodiment of the present invention.

100 is a memory, 101 is a processor, and 102 is an interrupt controller improved in this embodiment. 103-1 and 103-2 issue an interrupt request to the interrupt controller 102
/ O, 104-1 and 104-2 are interrupt request signals from the I / Os 103-1 and 103-2 to the interrupt controller 102, respectively, and 105 is an INT signal from the interrupt controller 102 to the processor 101. 106 is the interrupt controller 102 from the processor 101
107 is an external bus connecting the processor 101, the interrupt controller 102, and the I / O 103.

The hardware inside the interrupt controller 102 will be described.

Reference numeral 119 denotes an interrupt request mask register. The contents of the register 119 are written from the processor 101 via the external data bus 107 and the internal data bus 118 by a program.
For example, as shown in FIG. 5, if bit 3 of register 119 is '0', it is connected to interrupt priority level 3.
The interrupt request 104-1 from the I / O 103-1 is masked. 108 is an incomplete interrupt detection which receives eight interrupt request signals from outside the interrupt controller 102 and an 8-bit output 120 of the mask register 119 as inputs. Circuit. FIG. 11 shows the internal configuration of the incomplete interrupt detection circuit 108. For example, 601-3
Is a logical AND gate, and the level 3 interrupt request signals 104-1 and 1
20-3 inputs the bit 3 of the output of the mask register 119. As shown in FIG. 10, if the bit 3 of the register 119 is “0”, the interrupt request 104-1 is sent to the AND gate 601-3.
Is masked by Similarly, each AND gate in FIG. 11 masks an individual interrupt request signal input thereto by each bit of the mask register 119. 602 is
The NOR gate detects that all interrupt request signals that are not masked by the information stored in the mask register 119 are inactive, that is, that the inputs of the NOR gate 602 are all '0', and the output signal 110 becomes '0'.

A circuit 109 inverts only the least significant bit in the 5-bit output of the register 111. 110 is an output signal of the detection circuit 108. A register 111 stores 5-bit address information set by the processor 101. Usually, the processor 101 is connected to the external data bus 107 and the interrupt controller 102 before accepting an interrupt from the interrupt controller 102.
The 5-bit address information is stored in the register 111 via the internal data bus 118. Reference numeral 112 denotes a selector which receives the output of the register 111 and the output of 109 as input and selects the signal 108 as a selection signal.
When 108 is '0', select 111 output and use internal data bus
Output to 118 bits 3,4,5,6,7.

Reference numeral 113 denotes a priority determining circuit which receives eight interrupt request signals from the outside of the interrupt controller 102 and an 8-bit output 120 of the mask register 119 as inputs. A function 113 activates the INT signal 105 by detecting that an interrupt request that is not masked by information stored in the mask register 119 becomes active among eight input interrupt request signals, and It has the function of not activating the INT signal 105 even when an interrupt request masked by the information stored in the mask register 119 becomes active. Further, it has a function of detecting an interrupt request having the highest priority among interrupt requests not masked by the contents of the mask register 119 among eight input interrupt request signals and encoding the interrupt request into three bits. 11
Reference numeral 4 denotes a 3-bit output of the priority determination circuit 113.

Reference numeral 115 denotes an 8-bit register for holding the state of each of eight interrupt request signals from the outside of the interrupt controller 102 and peripheral circuits. Each bit of the 8-bit register is set to 1 at the rising edge of each interrupt request signal, and is set to 2 in conjunction with the second interrupt acceptance bus cycle of two consecutive interrupt acceptance bus cycles activated by the processor 101. It is reset at the falling edge of the second active pulse of the interrupt acceptance signal 106 which becomes active twice. FIG. 12 is a diagram showing only the bit 3 portion of the 8-bit register 115, and other bit configurations are also shown in FIG.
This is the same as the configuration in FIG. 701 is a set / reset flip-flop (hereinafter abbreviated as RS-FF), and I / O103-1
Is set at the rising edge of the interrupt request signal 104-1, and reset at the falling edge of the second active pulse of the interrupt receiving signal 106. Reference numeral 120-3 denotes bit 3 of the output of the mask register 119, and reference numeral 702 denotes an AND gate for inputting the output of 120-3 and the output of the RS-FF701. If bit 3 of the register 119 is “0” (120-3 is “0”) as shown in FIG. 10, the logical product gate 702 outputs the data from the I / O 103-1 connected to the interrupt priority level 3. That the interrupt request 104-1 is active is masked.

Reference numeral 116 denotes a priority encoder to which the output of the 8-bit register 115 is input, and detects the position of the bit having the highest priority among the bits which are "1" in the output of the register 115, Encode to bits and output.

A selector 117 receives the 3-bit outputs 114 and 116 of the priority determination circuit 113 as inputs, selects the signal 108 as a selection signal, and selects the output of the priority encoder 116 when the signal 108 is "1". When the signal 108 is "0", the 3-bit output 114 of the priority determination circuit 113 is selected and output to the bits 0, 1, and 2 of the internal data bus 118. An internal bus 118 of the interrupt controller 102 is an 8-bit bus.

In this embodiment, when the interrupt controller 102 is notified by the INT signal 105 to the processor 101 that an interrupt has occurred, the processor 101 starts the interrupt receiving bus cycle twice consecutively. Like the conventional interrupt controller, the interrupt controller 102 uses the interrupt accept signal 106 output accompanying the first interrupt accept bus cycle only for determining the interrupt priority inside the interrupt controller, and The vector is taken into the processor 101 via the external bus 107 in the second interrupt acceptance bus cycle. The format of the vector is the same as the format 1204 of the vector output in the conventional interrupt acceptance bus cycle.

In the present embodiment, 11100 is stored in the register 111 for the following description.
It is assumed that ₂ is preset. 109 is register 11
For reversing only the least significant bits in the 5-bit output of 1, the output of 109 is a 11101 _2. Further, interrupt requests 104-1 and 104-2 from the two I / Os 103-1 and 103-2 are input to the interrupt controller 102, and an interrupt request signal
104-1 is connected to the interrupt priority level 3 of the interrupt controller 102, and the interrupt request signal 104-2 is connected to the interrupt priority level 4.

If the mask register 119 11111111 ₂ is preset, i.e. all when an interrupt request signal is not masked, the interrupt controller 102 normal interrupt except incomplete Interrupt 8 bits as the next interrupt controller 102 Is issued to the processor 101 via the external bus 107. I / O103 for normal interrupt
When the interrupt request 104-1 from -1 becomes active,
The interrupt controller 102 activates the INT signal 105. When the processor 101 starts the first interrupt receiving bus cycle of the two interrupt receiving bus cycles after sampling the INT signal, the interrupt controller 102
110 if at least one interrupt request signal is active
Becomes '0', the selector 112 selects the contents of the register 111 (11100 _{2 in} this example). The selector 117 selects the output 114 of the priority determination circuit 113. In this example, I / O1
Since the interrupt request signal 104-1 of 03-1 is connected to the interrupt priority level 3, the output 1 of the priority determination circuit 113
14 and has a 011 _2.

In FIG. 8, a vector 301 is a vector issued for a (second) interrupt receiving bus cycle of a normal interrupt. The part 1202 in the vector 301 is processor 1
5-bit address information (11100 _{2 in} this example) preset from 01. 1203 of the vector 301 corresponds to a 3-bit priority level (0111 _{2 in} this example).

It described when the incomplete interrupt occurs when the mask register 119 11111111 ₂ are preset. Here, the interrupt request signal 104-1 of the I / O 103-1 generates an incomplete interrupt, and the interrupt request signal 104-1 of the I / O 103-2.
The case of -2 is described as inactive.
As shown in the timing chart of FIG.
An interrupt request input to the interrupt controller 102 when the first interrupt receiving bus cycle of the two interrupt receiving bus cycles is activated due to 101 sampling the active INT signal 105 at timing 201 If all were inactive, the interrupt controller
102 issues the following 8-bit vector to the processor 101. All the interrupt request signals to the interrupt controller 102 are inactive at timing 202 before the first interrupt receiving bus cycle of the two interrupt receiving bus cycles is started after the processor 101 samples the INT signal at timing 201. If so, timing 202
Thereafter, 110 becomes '1'. In this embodiment, the I / O 103
-1 interrupt request signal 104-1 is the interrupt controller 102
Is until the timing 202 because it is connected to the interrupt priority level 3 priority determination circuit 113 011 ₂ output to have but a timing 202 after the output values of the indefinite. On the other hand, in the register 115, only the bit 3 is set by the rising edge of the interrupt request signal 104-1 connected to the priority level 3, and at the timing 202, the interrupt request signal 104-1 connected to the priority level 3 is set. Even after 1 becomes inactive, bit 3 of register 115 stores that the rising edge of interrupt request signal 104-1 connected to priority level 3 has occurred. to the fall edge of the first rising edge after the second interrupt acceptance signal priority encoder 116 outputs 011 _2. Timing 202
Thereafter, since the value 110 is “1”, the selector 112
(In this example, 11101 ₂ ) is selected. The selector 117 outputs the output of the priority encoder 116 (011 in this example).
₂ ) Select In FIG. 8, a vector 302 is a vector issued for a (second) interrupt acceptance bus cycle of a normal interrupt.

As shown in FIG. 9, based on FIG. 8, the vector address 1204 for a normal interrupt in this embodiment is 03800H.
The vector address 1204 for incomplete interrupts is in the range 03A00H to 03BC0H.

If the mask register 119 11110111 ₂ is preset, that it is an interrupt request signal from an I / O103-1 104-
The operation when only 1 is masked will be described.
1 when interrupt request signal 104-2 is inactive
When a “short” pulse is generated only in the block 04-1, the interrupt request 104-1 is masked by the mask register 119, so that the INT signal is not generated, so that the incomplete interrupt does not occur.

If a “short” pulse is generated in the interrupt request signals 104-1 and 104-2 at the same time, the “short” pulse generated in the 104-1 is masked by the mask register 119 as described above. It is not detected in 108,115. 104
Since "-2" is not masked, the "short" pulse generated at 104-2 is detected at 108 and 115, and the above-mentioned incomplete interrupt processing is performed for the interrupt level 4 to which 104-2 is connected. That is, the INT signal 105 is activated by the “short” pulse generated in 104-2, and the processor 101
, The interrupt acceptance signal 106 of two pulses is issued, the vector for the incomplete interrupt of the interrupt level 4 connected to 104-2 is issued for the second interrupt acceptance bus cycle.

Interrupt level 3 masked during normal interrupt processing
Is incomplete, the malfunction of the priority encoding of 116, in this example, the fact that the interrupt request signal 104-2 connected to the interrupt level 4 was an incomplete interrupt, This prevents the connected interrupt request signal 104-1 from being hidden by the occurrence of an incomplete interrupt.

In the present embodiment, the processor 101 uses the conventional interrupt control method, and even if an incomplete interrupt or a normal interrupt occurs, the processor 101 executes the INT signal according to the flow shown in FIG. After the sample has been sampled, two interrupt acceptance bus cycles can be started, and the vector table can be accessed based on the vector fetched in the second interrupt acceptance bus cycle to branch to the target vector address. It is possible. In particular, when an incomplete interrupt occurs, a vector for the incomplete interrupt is issued from the interrupt controller 102 in the second interrupt acceptance bus cycle, and the interrupt request level that caused the incomplete interrupt is discriminated. Access the corresponding entry in the incomplete interrupt vector table. The corresponding entry in the incomplete interrupt vector table stores the start address of the incomplete interrupt processing routine of each interrupt level.

FIG. 13 is a view showing a fourth embodiment of the present invention. In the fourth embodiment, the register 801 that determines the entry of the vector table for the incomplete interrupt can set a value from the processor 101. This makes it possible to place the vector table at any location in the memory, increasing the flexibility in constructing the system.

〔The invention's effect〕

As explained above, according to the present invention, the vector obtained from the interrupt controller by activating the interrupt acceptance bus cycle in order for the processor to accept the interrupt
The processor can determine whether the interrupt is an incomplete interrupt. Further, it is possible to recognize at what level the incomplete interrupt has occurred at the same vector fetch timing as in the conventional interrupt processing method. Therefore, the processor can perform the incomplete interrupt processing to the interrupt request source that generated the incomplete interrupt while maintaining the processing and timing of the interrupt response from the acceptance of the interrupt to the branch to the interrupt processing routine as in the conventional method. it can.

Also, since the interrupt controller of the conventional interrupt processing method has determined that the service routine of the priority level corresponding to one specific interrupt request input terminal is to be used when an incomplete interrupt occurs, the interrupt request input terminal is substantially Although the interrupt request signal from the I / O etc. in the system could not be connected, the present invention requires connecting the interrupt request signal from the I / O etc. in the system to all the interrupt request input terminals of the interrupt controller. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a diagram showing a connection relationship between I / O and an interrupt controller and a processor according to a first embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the present embodiment, and FIG. When an interrupt occurs in the processor 101
FIG. 4 is a diagram showing the format of two vectors output by the interrupt controller 102 during two consecutive interrupt receiving bus cycles in which the CPU starts, FIG. 4 is an interrupt vector table used in this embodiment, and FIG. FIG. 6 is a diagram for explaining a second embodiment of the present invention, FIG. 6 is a diagram showing a third embodiment of the present invention, FIG. 7 is a timing chart for explaining the operation of the present embodiment, and FIG. FIG. 9 is a diagram showing a format of two vectors output by the interrupt controller 102 during two consecutive interrupt receiving bus cycles in which the processor 101 is activated when an interrupt occurs in the example. FIG. 9 shows an interrupt used in the present embodiment. Vector table, number
FIG. 10 is a diagram showing an example of the contents of the mask register 119, FIG. 11 is a diagram showing the internal configuration of the incomplete interrupt detection circuit 108, and FIG.
FIG. 13 is a diagram showing the structure of one bit (bit 3) inside the register 115, FIG. 13 is a diagram for explaining the fourth embodiment of the present invention, and FIGS. FIG.

Claims (2)

(57) [Claims] An interrupt request from the input / output device is input to the interrupt controller, and the interrupt controller receives a request from the plurality of input / output devices. An interrupt request is arbitrated and an interrupt request signal is output to the central processing unit. When the central processing unit receives the interrupt from the interrupt controller, the central processing unit activates an interrupt receiving bus cycle for the interrupt controller. In an information processing system for outputting an interrupt vector to the central processing unit during an interrupt acceptance bus cycle, a register in the interrupt controller, the value of which is set by the central processing unit, and a value different from the contents of the register. First means for outputting, First selecting means for inputting the output of the first means and the output of the first means, and determining the priority of active interrupt requests from the plurality of input / output devices and outputting the highest priority interrupt request level value. A second means;
Holding means for holding information on the presence / absence of an interrupt request from the input / output device; and third means for inputting an output of the holding means, determining a priority, and outputting a value of the highest priority interrupt request level. A second selection unit that receives the outputs of the second and third units as input, and a detection unit that is inside the interrupt controller and detects that there is no interrupt request from the input / output device. Having an interrupt receiving bus cycle after the central processing unit receives an interrupt request from the interrupt controller;
The detecting means controls the first and second selecting means simultaneously to generate an interrupt vector from the contents of the register and the output of the second means 4 or to generate an interrupt vector from the first and third means. An interrupt processing device for selecting whether to generate from an output. 2. An interrupt processing apparatus according to claim 1, further comprising: an additional register inside said interrupt controller for setting a value from said central processing unit, and an interrupt from said input / output device based on the contents of said additional register. Means for controlling the determination of the priority of the request, means for masking an interrupt request from the input / output device based on the content of the additional register and inputting the interrupt request to the detecting means, and means for holding the content based on the content of the additional register. Means for masking the output and inputting the output to the third means.