JPH04209058A - Interruption processor - Google Patents

Abstract

PURPOSE:To decide whether an interruption is incomplete or not by actuating an interruption acceptance bus cycle where a processor is about to accept an interruption and obtaining a vector from an interruption controller. CONSTITUTION:The processor 101 when informed by the interruption controller 102 with an INT signal 105 that the interruption is caused actuates the interruption acceptance bus cycle twice continuously. The interruption controller 102 uses an interruption acceptance signal 106 outputted accompanying the 1st interruption acceptance bus cycle only to determine the interruption priority order in the interruption controller and the processor 101 fetches the vector through an external bus 107 in the 2nd interruption acceptance bus cycle to judge whether the interruption is incomplete or not.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt processing method, and more particularly to an interrupt processing method by an interrupt controller and a central processing unit when an incomplete interrupt occurs.

[Conventional technology]

In an information processing system, a central processing unit (hereinafter abbreviated as a processor) needs to exchange information with several input/output devices (hereinafter abbreviated as I10) in addition to memory. To improve system throughput, I
Service to lo is done by interrupt. Ilo that requires service from the processor activates an interrupt request signal to the processor. When a processor in an interrupt enabled state recognizes the occurrence of an interrupt by an interrupt request signal, it interrupts the execution of the program up to that point, transfers control to the interrupt processing program (interrupt service routine), and services Ilo with the interrupt processing program. .

If there are many Ilo's in the information processing system,
An interrupt controller is used that arbitrates interrupt requests from each Ilo according to priority and transmits them to the processor. The interrupt controller receives interrupt request signals from several Ilo's and notifies the processor of the presence or absence of an interrupt request. This notification signal will be referred to as an INT signal. The processor samples the INT signal input from outside the processor between the end of execution of one instruction and the start of execution of the next instruction.If the INT signal is active and the processor is not enabled to accept interrupts, If there,
The processor starts processing when an interrupt is accepted internally, and first outputs a signal when the interrupt is accepted. When the interrupt controller receives an interrupt reception signal, it includes information that allows it to identify the interrupt request source that has issued the interrupt request with the highest priority among the interrupt request signals that are active at that moment. The vector is returned to the processor. The processor branches to a service routine corresponding to the interrupt request source by analyzing the vector obtained from the interrupt controller.

FIG. 14 is a block diagram of an information processing system composed of a processor and an interrupt controller. 1
01 is a processor, 1002 is an interrupt controller that can process 8 interrupt requests, 103 is one Ilo, 104 is an interrupt request signal from l10103,
105 is the INT signal from the interrupt controller 102, 106 is a signal for accepting an interrupt from the processor 101, and 107 is a data bus of the information processing system.

Below, the processor 101 is in a state where it can accept interrupts, and the interrupt controller 1002 has one l10103.
Consider the case where only one interrupt request 104 from . Interrupt request 1 from said l10103
When 04 becomes active, the interrupt controller 1002
The INT signal 105 from the INT signal 105 becomes active and notifies the processor 101 that an interrupt request has occurred.

As shown in FIG. 15, after the processor 101 samples the INT signal at 1101 and detects that the INT signal is active, the interrupt request 104 from the l10103 remains active until the signal 106 is output. At some point, the following normal interrupt processing is performed. When processor 101 accepts an interrupt, the interrupt acceptance activates two consecutive bus cycles. For each side interrupt reception, the processor 101 outputs a signal 106 to the interrupt controller 1002 in a bus cycle. In the first interrupt acceptance, in the bus cycle, the interrupt controller 1002 decides to request the processor 101 to service the interrupt request input with the highest priority level among the active interrupt request inputs. In this example, only one interrupt request 104 is active, so the first interrupt is accepted by the bus.
During the cycle, interrupt controller 1002 decides to request processor 101 to service interrupt request 104 .

In the second interrupt acceptance, in the bus cycle, the interrupt controller 1002 outputs a vector containing the priority of the interrupt request 104 to the data bus 107, and the processor 101 accepts or accepts the vector. After the processor 101 saves the program counter and information indicating the running state of the program interrupted by the interrupt into the stack, the processor 101 branches to the interrupt service routine for l10103 using the vector.

The vector passed from the interrupt controller 1002 to the processor 101 has the format shown in FIG. 1201 is the 8-bit wide vector passed from the interrupt controller 1002 to the processor 101. 1202 is a 5-bit portion corresponding to an address in the vector 1201, and is
1 for the interrupt controller 1002. 1203 is a portion of the vector 1201 in which the priority level of the interrupt request is encoded into 3 bits. The interrupt controller 1002 assigns 8 interrupt requests to 8 levels of priority and sends them to the processor 101.
When the processor 101 accepts an interrupt, it encodes the priority level of the interrupt request to be serviced among the eight interrupt requests into 3 bits and sends it to the processor 101 in a vector 12.
It is shown in 1203 in 01. In this example, for example l
Assuming that the interrupt request 104 from 10103 is connected to the interrupt request input terminal corresponding to the third priority level of the interrupt controller, 1203 in the vector 1201 for the interrupt request 104 contains a binary number 011□.

The processor 101 uses the vector 1201 obtained from the interrupt controller 1002 to write the 16-bit address 12.
Generate 04. Address 1204 is the interrupt request 104 in the vector table prepared in memory.
indicates the position of the entry corresponding to the priority level. In this example, each entry in the vector table indicates the position of that entry. In this example, it is assumed that each entry in the vector table stores information regarding the start address of the interrupt service routine of the priority level indicated by that entry.

First, processor 101 accesses the entry specified by the vector in the vector table to obtain information regarding the start address of the interrupt service routine. Next, control is transferred to the start address of the interrupt service routine based on this information.

FIG. 18 is a diagram showing the flow of conventional interrupt processing. Every time the processor 101 finishes executing an l instruction, it determines whether or not the INT signal from the interrupt controller 1002 is active, and if it is active, the processor 101 accepts the interrupt in consecutive bus cycles. The second interrupt reception takes in a vector from the interrupt controller 1002 in a bus cycle.

Using the vector, the processor 101 accesses the entry of the service routine for the interrupt in the vector file and obtains information regarding the start address of the service routine for the interrupt. Next, processor 101
is saved to the program counter and the stack that indicates the status of the program that was interrupted by the interrupt, and then
Control is transferred to the start address of the service routine for the interrupt. When the service routine finishes processing the interrupt, the information such as the program counter that was saved to the stack is restored from the stack by executing the return-from-interrupt instruction written at the end of the service routine. to return control to the program that was interrupted by the interrupt.

As shown in FIG.
1 samples the INT signal 105, l101
Although the interrupt request 104 from 10103 was active, when the processor 101 outputs the interrupt acceptance signal, the interrupt request 104 from 10103 becomes inactive, the interrupt controller 1002 does not accept the interrupt. A vector indicating the interrupt request source cannot be returned to the processor 101 in response to the input of the signal 106. An interrupt input at the timing shown in FIG. 17 will be referred to as an incomplete interrupt. Incomplete interrupts occur when Ilo independently generates and erases interrupt requests.

In the conventional interrupt processing method, when an incomplete interrupt occurs, the interrupt controller 1002 requests the processor 101 during the bus cycle to accept the interrupt at a priority level determined to be used when an incomplete interrupt occurs (for example, level 7). ), the processor 101 accepts the interrupt vector without knowing that it is an incomplete interrupt, and continues processing the incomplete interrupt as one of the normal interrupt processings explained in FIG. I was going.

In other words, due to the incomplete interrupt that was generated when the interrupt request source processor 10103 erased the interrupt request that had already been issued, the processor 101 resumes the execution of the program up to that point at the point where the incomplete interrupt was accepted. interrupted,
Information such as the program counter is saved to the stack, the incomplete interrupt vector is analyzed, information on the start address of the incomplete interrupt processing routine is obtained from the vector table, and control is transferred to the incomplete interrupt processing routine.

[Problem to be solved by the invention]

In conventional interrupt processing methods, the interrupt controller can detect when an incomplete interrupt has occurred, but the processor cannot specify at which interrupt level the interrupt request has occurred, so the incomplete interrupt processing routine There is no special action to be taken. In application fields where immediacy and timeliness are required in I10 processing, it is necessary to specify at which interrupt level the interrupt request has occurred when an incomplete interrupt occurs. In the conventional interrupt processing method, it is necessary to check the status of each Ilo by polling each Ilo that issues an interrupt request one by one in the incomplete interrupt processing routine. This had the disadvantage that timeliness was significantly impaired.

In addition, in conventional interrupt controllers, the interrupt request input terminal corresponding to the priority level determined to be used when an incomplete interrupt occurs (level 7 in the conventional example above) is essentially connected to an input terminal such as Ilo in the system. This had the disadvantage that it was not possible to connect the interrupt request signal.

[Means to solve the problem]

An interrupt processing device according to the present invention has a central processing unit, an interrupt controller, and a plurality of input/output devices, and an interrupt request from the input/output device is input to the interrupt controller, and the interrupt controller controls the input/output of the plurality of input/output devices. Interrupt requests from devices are arbitrated and an interrupt request signal is output to the central processing unit, and when the central processing unit accepts the interrupt from the interrupt controller, the interrupt acceptance starts a bus cycle for the interrupt controller, and Interrupt control is an information processing system in which the interrupt reception outputs an interrupt vector to the central processing unit during a bus cycle. means 2 for outputting a value different from the contents of , selection means 3 for inputting the outputs of register 1 and means 2, and determining the priority order of active interrupt requests from the plurality of input/output devices and determining the highest priority level. means 4 for outputting the value of the interrupt request level of the input/output device, means 5 for holding information on the presence or absence of an interrupt request from the input/output device, and determining the priority level by inputting the output of the holding means 5, means 6 for outputting the value of the priority interrupt request level; selection means 7 for inputting the output of means 4 and the output of means 6; and a means 8 for detecting that there is no interrupt, and after the central processing unit accepts an interrupt request from the interrupt controller, the interrupt reception is performed by the detecting means 8 to select the selecting means 3 and the selecting means with respect to the bus cycle. 7 are controlled simultaneously to select whether to generate an interrupt vector from the contents of the register 1 and the output of the means 4 or from the output of the means 2 and the output of the means 6.

The interrupt processing device further includes a register 9 located inside the interrupt controller and to which a value is set by the central processing unit, and determines the priority of interrupt requests from the input/output device based on the contents of the register 9. means for controlling the interrupt request from the input/output device according to the contents of the register 9 and inputting it to the detecting means 8; and means for controlling the interrupt request from the input/output device according to the contents of the register 9;
It is characterized by having means for mask-controlling the output of and inputting it to the means 6.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a diagram showing a connection method between a processor, an interrupt controller, and Ilo in a first embodiment of the present invention, and is similar to the connection method in the conventional example.

101 is a processor, and 102 is an interrupt controller improved in this embodiment. 103 is an Ilo that issues an interrupt request to the interrupt controller 102; 104 is an interrupt request signal from the Ilo 103 to the interrupt controller 102; and 105 is an INT signal from the interrupt controller 102 to the processor 101. 106 is processor 1. ．． 01 to the interrupt controller 102 is a signal. 107 is an external bus connecting the processor 101, interrupt controller 102, and l10103.

The internal hardware of the interrupt controller I (12) will be explained. 108 is a circuit that detects that all eight interrupt request signals from outside the interrupt controller 102 are inactive; When , the output signal 110 becomes 1°.

108 is, for example, an eight-man powered NOR circuit. Used to detect incomplete interrupts. 109 is a circuit that inverts only the least significant bit of the register 11105 bit output.

110 is an output signal of the detection circuit 108.

Ill is a register that stores 5-bit address information set by the processor 101.

Typically, before accepting an interrupt from the interrupt controller 102, the processor 101 stores 5-bit address information in the register 111 via the external data bus 107 and the internal data bus of the interrupt controller 102. 1
12 is a selector which inputs the output of register 111 and the output of register 109, uses signal 108 as a selection signal, and outputs signal 108.
When is 1', output 109 is selected and signal 9 108 is 0.
When the output of 111 is selected and the internal data bus 11
Output to hits 3, 4, 5, 6.7 of 8. Reference numeral 113 denotes a priority determination circuit which receives eight interrupt request signals from outside the interrupt controller 102 as input. 8 to be input
This is a priority determination circuit that detects the interrupt request with the highest priority among the active interrupt requests among the main interrupt request signals and encodes it into 3 bits.
14 is a 3-bit output of the priority determining circuit 113.

Reference numeral 115 is an 8-bit register that holds the state of each of the eight interrupt request signals from outside the interrupt controller 102, and each bit of the 8-bit register is set to 1 at the rising edge of each interrupt request signal. The two successive interrupt receptions when the processor lot is activated are the bus cycles.The second interrupt reception is accompanied by the bus cycle.
The interrupt acceptance signal becomes active once. ．． It is reset at the falling edge of the 602nd Acquire pulse. 116 is a priority encoder that receives the output of the 8-bit register 115 as input;
The position of the bit with the highest priority among the bits designated as Ill among the outputs of 15 is detected, encoded into 3 bits, and output.

117 is a selector which inputs the 3-bit output 114 of the priority determining circuit 113 and the 3-bit output of 116, uses the signal 108 as a selection signal, and selects the output of the priority encoder 116 when the signal 108 is 1'; When the signal 108 is "0", the 3-bit output 114 of the priority determining circuit 113 is selected and output to bits 0 and 1.2 of the internal data bus 118. 118 is the 8-bit internal bus of the interrupt controller 102.・It's a bus.

When the interrupt controller 102 in this embodiment notifies the processor 101 of the occurrence of an interrupt using the INT signal 105, the processor 101 activates two consecutive bus cycles to accept the interrupt. The interrupt controller 10 is similar to the conventional interrupt controller.
In 2, the first interrupt reception is output along with the bus cycle, and the signal 106 is used only to determine the interrupt priority within the interrupt controller, and the second interrupt reception is output according to the bus cycle. A vector is loaded into the processor 101 via the external bus 107 in a cycle.

The format of this vector is the format of a vector in which a conventional interrupt reception is output in a bus cycle.
04 Same 4'.

For the following explanation, in this embodiment, the register 111 is set to 11.
It is assumed that 1002 is preset. Since 109 inverts only the least significant bit of the 5-bit output of register 111, the output of 109 is 11101z. Also, the interrupt controller 102 has one l101.
It is assumed that only 03 requests an interrupt, and the interrupt request signal 104 of 110103 is connected to interrupt priority level 3 of the interrupt controller 102.

For normal interrupts other than incomplete interrupts, the interrupt controller 102 issues the following 8-bit vector to the processor 101 via the external hash 107. In the case of a normal interrupt, two interrupt receptions after the processor 101 samples the INT signal occur in one bus cycle.
For the second interrupt reception, if at least one interrupt request signal to the interrupt controller 102 is active when the bus cycle is started, 110 becomes 0', so the selector 112 selects the contents of the register 111 (111002 in this example).
). Further, the selector 117 selects the output 114 of the priority order determining circuit 113. In this example l10103
Since the interrupt request signal 104 is connected to interrupt priority level 3 of the interrupt controller 102, the output 114 of the priority determination circuit 113 is 0112.

In FIG. 3, a vector 301 is a vector issued for a bus cycle when a normal interrupt (second time) is accepted. A portion 1202 in the vector 301 is 5-bit address information (111002 in this example) preset from the processor 101. Vector 301
1.203 is the 3-bit priority level (0 in this example).
112).

When an incomplete interrupt occurs, that is, the processor 101 samples the active INT signal 105 at timing 201 as shown in the timing chart of FIG. If all interrupt request inputs to the interrupt controller 102 are inactive when the bus cycle is started, the interrupt controller 102 sends the following 8-bit vector to the processor 1.
Issued for 01. The two interrupt receptions after the processor 101 samples the INT signal at timing 201 are the first interrupt reception of the bus cycle, and the interrupt request signal to the interrupt controller 102 is received at timing 202 before starting the bus cycle. If all are inactive, 110 becomes "1°" after timing 202. In this embodiment, the interrupt request signal 104 of l10103 is connected to interrupt priority level 3 of the interrupt controller 1020, so it is given priority until timing 202. The priority determining circuit 113 outputs 0112, but outputs an undefined value after timing 202.On the other hand, in the register 115, only bit 3 is output due to the rising edge of the interrupt request signal 104 connected to priority level 3. is set, and even after the interrupt request signal 104 connected to priority level 3 becomes inactive at timing 202, a rising edge of the interrupt request signal 104 connected to priority level 3 is detected. Since bit 3 of the register 115 is stored, the priority encoder 116 outputs 0112 for the second interrupt reception after the rising edge of the interrupt request signal 104 until the falling edge of the signal.After timing 202, the priority encoder 116 outputs 110. is 1°, so the selector 112
selects the contents of register 109 (11101□ in this example). Selector 117 selects the output of priority encoder 116 (0112 in this example). Third
In the figure, vector 302 indicates the (second) normal interrupt.
Interrupt acceptance is a vector issued for each bus cycle.

As shown in FIG. 4, based on FIG. 3, the vector address 1204 for a normal interrupt in this embodiment is 03.
It is in the range 800H to 039COH, and the vector address 1204 for incomplete interrupts is 03A00H to 0.
It is within the range of 3BCOH. In this embodiment, the processor 101 uses the conventional interrupt control method, and regardless of whether an incomplete interrupt occurs or a normal interrupt occurs, the processor 101 uses the flow shown in FIG.
After sampling the T signal, two interrupts cause the bus to receive the signal.
When a cycle is started and the second interrupt is received, it is possible to access the vector table based on the vector taken in in the bus cycle and branch to the target vector address. In particular, when an incomplete interrupt occurs, for the second interrupt acceptance, the interrupt controller 102 issues a vector for incomplete interrupt in the bus cycle, distinguishes the interrupt request level that caused the incomplete interrupt, and then accepts the fourth interrupt. Access the corresponding entry in the incomplete interrupt vector table shown in the figure. The corresponding entry in the incomplete interrupt vector table stores the start address of the incomplete interrupt processing routine for each side-interrupt level.

FIG. 5 is a diagram showing a second embodiment of the present invention.

In the second embodiment, a value can be set by the processor 101 in the register 509 that determines the entry of the vector table for incomplete interrupts. This allows the vector table to be placed anywhere in memory, increasing flexibility when building the system.

FIG. 6 shows a third embodiment of the present invention.

100 is a memory, 101 is a processor, and 102 is an interrupt controller improved in this embodiment. 103-1
, 103-2 is Ilo that issues an interrupt request to the interrupt controller 102, 104-1 and 104-2 are interrupt request signals from l10103-1 and 103-2 to the interrupt controller 102, and 105 is an interrupt request signal from the interrupt controller 102. This is the INT signal to processor 101. 106 is a signal for accepting an interrupt from the processor 101 to the interrupt controller 102; 107 is a signal for receiving an interrupt from the processor 101. Interrupt controller 102, l10103
This is an external bus to be connected.

The internal hardware of the interrupt controller 102 will be explained.

119 is an interrupt request mask register; register 119
The contents of are written by the program from the processor 101 via the external data bus 107 and the internal data bus 118. For example, as shown in FIG.
If bit 3 is 0°, interrupt request 104 from l10103-1 connected to interrupt priority level 3
-1 is masked; 108 is an incomplete interrupt detection circuit which receives eight interrupt request signals from outside the interrupt controller 102 and an 8-bit output 120 of the mask register 119; FIG. 11 shows the internal configuration of the incomplete interrupt detection circuit 108. For example, 601-3 is an AND gate, and level 30 interrupt request signals 104-1 and 120-3 are mask register 1.
Bit 3 of the output of No. 19 is input. As shown in FIG. 10, if bit 3 of register 119 is 0', interrupt request 104-1 is masked by AND gate 601-3. Similarly, each AND gate in FIG. 11 masks each interrupt request signal input thereto by each bit of mask register 119. 602 is NOR
At the gate, all interrupt request signals that are not masked by the information stored in the mask register 119 are inactive, that is, all inputs of the NOR gate 602 are 0.
degree is detected, and at this time the output signal 110 is 0 degree.
become.

A circuit 109 inverts only the least significant bit of the 5-bit output of the register 111. 110 is the detection circuit 10
This is the output signal of 8. A register 111 stores 5-bit address information set by the processor 101. Typically, the processor 101 is an interrupt controller 1
External data bus 10 before accepting interrupts from 02
7. Interrupt controller 102 internal data bus 1.
18, the 5-bit address information is sent to the register 11.
Store in 1. 112 is the output of register 111 and 109
A selector which takes the output of 109 as an input and the signal 108 as a selection signal selects the output of 109 when the signal 108 is "1",
When Shingo 108 is "0", the output of 111 is selected and output to bits 3, 4, 5, 6.7 of internal data bus 118.

Reference numeral 113 denotes a priority determining circuit which receives eight interrupt request signals from outside the interrupt controller 102 and an 8-bit output 120 of the mask register 119. 113
detects that an interrupt request that is not masked has become active among the 8 input interrupt request signals according to the information stored in the mask register 119, and outputs the IN signal.
A function that makes the T signal 105 active, and even if an interrupt request masked by the information stored in the mask register 119 becomes active, the INT signal 10 remains active.
It has a function of not activating 5. Also, among the 8 input interrupt request signals, mask register 1
It has a function of detecting the interrupt request with the highest priority among the interrupt requests not masked by the contents of No. 19 and encoding it into 3 bits. 114 is a 3-bit output of the priority determining circuit 1130.

Reference numeral 115 denotes an 8-bit register and peripheral circuits that hold the state of each of the eight interrupt request signals from outside the interrupt controller 102. Each bit of the 8-bit register is set to 1 at the rising edge of each side-in request signal, and when the processor 101 starts up two consecutive interrupt receptions, the second interrupt reception is associated with the bus cycle. The interrupt reception that becomes active twice is signal 1.
It is reset on the falling edge of the second active pulse of 06. Figure 12 shows 8-bit register 11.
12 shows only bit 3 of bit 5, and the configuration of other bits is also the same as the configuration of FIG. 12. 701 is a set/reset flip-flop (hereinafter abbreviated as R3-FF), which receives the interrupt request signal 104 from l10103-1.
It is set at the rising edge of -1, and interrupt acceptance is signal 106.
It is reset on the falling edge of the second active pulse. 120-3 is the output of mask register 119, bit 3.702 is an AND gate, 12.0-3
and input the output of R8-F'F701. As shown in Figure 1O, bit 3 of register 119 is '0' (12
If 0-3 is '0', then l101 is connected to interrupt priority level 3 by AND gate 702.
The fact that interrupt request 104-1 from 03-1 was active is masked.

116 is a priority encoder that receives the output of the 8-bit register 115 as an input, and detects the position of the bit with the highest priority among the bits set to 1' in the output of the register 115, and outputs the 3-bit bit. Encode and output.

117 is a selector which inputs the output 114 of the priority determination circuit 11303 and the 3-bit output of 116, uses the signal 108 as a selection signal, and selects the output of the priority encoder 116 when the signal 108 is "l";
3 of the priority determination circuit 113 when the signal 108 is “0°”
Select bit output 114 to connect internal data bus 118
output to 0, 1.2. Reference numeral 118 denotes an internal bus of the interrupt controller 102, which is an 8-bit bus.

In this embodiment, when the interrupt controller 102 notifies the processor 101 that an interrupt has occurred using the INT signal 105, the processor 101 activates two consecutive bus cycles to accept the interrupt. An interrupt controller 102 similar to a conventional interrupt controller
In the case of the first interrupt reception, the signal 106 outputted along with the bus cycle is used only for determining the interrupt priority within the interrupt controller.
In the second interrupt reception, the vector is taken into the processor 101 via the external bus 107 in a bus cycle. The format of this vector is the same as the format 1204 of a vector output in a bus cycle in conventional interrupt reception.

For the following explanation, in this embodiment, the register 111 is set to 11.
It is assumed that 1002 is preset. Since 109 inverts only the least significant bit of the 5-bit output of register 111, the output of 109 is 111012. In addition, the interrupt controller 102 has two l10
Interrupt request 104- from 103-1 and 103-2
1, 104-2 is input, and the interrupt request signal 104-1
is the interrupt priority level 3 of the interrupt controller 102
Assume that the interrupt request signal 104-2 is connected to interrupt priority level 4.

When 111111112 is preset in the mask register 119, that is, when all interrupt request signals of the interrupt controller 102 are not masked, the interrupt controller 102 uses the following 8-bit interrupt for normal interrupts other than incomplete interrupts. It is issued to the processor 101 via the vector external bus 107. In case of normal interrupt, interrupt request 104 from l10103-1
-1 becomes active, interrupt controller 102
makes the INT signal 105 active.

After the processor 101 samples the INT signal, two interrupts are accepted in the bus cycle, and the first interrupt is accepted by the interrupt controller 1 when the bus cycle is started.
If even one interrupt request signal to 02 is active, 110 becomes 0', so selector 112 selects register 1.
11 (in this example, 111002) is selected. The selector 117 also outputs the output 114 of the priority order determining circuit 113.
Select. In this example, the interrupt request signal 104-1 of l10103-1 is connected to interrupt priority level 3, so the output 114 of the priority determination circuit 113 is 0112.
It becomes.

In FIG. 8, a vector 301 is a vector that is issued for a normal interrupt (second) interrupt reception in a bus cycle. A portion 1202 in the vector 301 is 5-bit address information (11100□ in this example) preset by the processor 101. Vector 301
1203 is a 3-bit priority level (01 in this example).
12).

A case where an incomplete interrupt occurs when 1llllllllz is preset in the mask register 119 will be described. Here, the interrupt request signal 104-1 of l10103-1 generates an incomplete interrupt, and l10103-1 generates an incomplete interrupt.
A case will be described in which the interrupt request signal 104-2 of No. 2 is inactive. As shown in the timing chart of FIG. 7, because the processor 101 samples the active INT signal 105 at timing 201, two interrupt receptions occur during the bus cycle, and the first interrupt reception occurs during the bus cycle. If all interrupt request inputs to the interrupt controller 102 are inactive when the interrupt controller 102 is activated, the interrupt controller 102 issues the following 8-bit vector to the processor 101.

After the processor 101 samples the INT signal at timing 201, two interrupts are accepted in 1 bus cycle.
If all interrupt request signals to the interrupt controller 102 are inactive at timing 202 before starting the bus cycle, the second interrupt is accepted at timing 202.
From 2 onwards, 110 becomes 1'. In this example, l
Since the interrupt request signal 104-1 of the interrupt controller 10103-1 is connected to the interrupt priority level 3 of the interrupt controller 1020, the interrupt request signal 104-1 of the interrupt controller 1020 is connected to the priority determination circuit 1 until timing 202.
13 outputs 0112, but after timing 202 it outputs an undefined value. On the other hand, in register 115, interrupt request signal 1 is connected to priority level 3.
Only bit 3 is set by the rising edge of 04-1, and even after the interrupt request signal 104-1 connected to priority level 3 becomes inactive at timing 202, it remains connected to priority level 3. Since bit 3 of the register 115 remembers that there was a rising edge of the interrupt request signal 104-1, the second interrupt reception after the rising edge of the interrupt request signal 104-1 will not be accepted until the falling edge of the signal. The priority feeder 116 outputs 0112. timing 20
Since 110 is 1' from 2 onwards, the selector 112 selects the contents of the register 109 (111012 in this example). The selector 117 is the priority encoder 11
6 output (011□ in this example) is selected. In FIG. 8, a vector 302 is a vector issued for a bus cycle when a normal interrupt (second time) is accepted.

As shown in FIG. 9, based on FIG. 8, the vector address 1204 for a normal interrupt in this embodiment is 03.
It is in the range 800H to 039COH, and the vector address 1204 for incomplete interrupts is 03AOOH to 0.
It is within the range of 3BCOH.

The operation when 111101112 is preset in the mask register 119, that is, when only the interrupt request signal 104-1 from l10103-1 is masked will be described. If a "short" pulse occurs only in interrupt request signal 104-1 while interrupt request signal 104-2 is inactive, no INT signal is generated because interrupt request 104-1 is masked by mask register 119. , no incomplete interrupt occurs.

If "short pulses" occur in the interrupt request signals 104-1 and 104-2 at the same time, since signal 104-1 is masked by the mask register 119, the "short pulses" generated in interrupt request signals 104-1 and 104-2 will be ignored. Pulse is 108,115
is not detected.

Since 104-2 is not masked, a 'short' pulse occurring at 104-2 will be detected at 108.115 and
The incomplete interrupt processing described above is performed for interrupt level 4 to which 04-2 is connected.

In other words, due to the "short" pulse generated at 104-2, the IN
When the T signal 105 becomes active and the signal 106 is issued to accept two pulses of interrupt from the processor 101, the second interrupt acceptance occurs when the connected interrupt level 4 of 104-2 is activated for the bus cycle. A vector for a complete interrupt is issued.

116 priority encoding malfunctions due to incomplete interrupt level 3 that is masked during normal interrupt processing; in this example, interrupt request signal 104-2 connected to interrupt level 4 is an incomplete interrupt. This prevents this from being hidden due to the occurrence of an incomplete interrupt of the interrupt request signal 104-1 connected to interrupt level 3, which has a higher priority.

In this embodiment, the processor 101 uses the conventional interrupt control method, and regardless of whether an incomplete interrupt occurs or a normal interrupt occurs, the processor 101 receives the INT signal according to the flow shown in FIG. After sampling, two interrupt receptions start a bus cycle, and the second interrupt reception accesses the vector table based on the vector fetched in the bus cycle and branches to the target vector address. things are possible. In particular, when an incomplete interrupt occurs, for the second interrupt acceptance, the interrupt controller 102 issues a vector for incomplete interrupt in the bus cycle, distinguishes the interrupt request level that caused the incomplete interrupt, and then accepts the fourth interrupt. Access the corresponding entry in the incomplete interrupt vector table shown in the figure. The corresponding entry in the vector table for incomplete interrupts contains:
The start address of the incomplete interrupt processing routine for each interrupt level is stored.

FIG. 13 is a diagram showing a fourth embodiment of the present invention. In the fourth embodiment, a register 801 that determines the entry of the vector table for incomplete interrupts is stored in the processor 1.
It is possible to set the value from 01. This allows the vector table to be placed anywhere in memory, increasing flexibility when building the system.

〔Effect of the invention〕

As explained above, according to the present invention, when the processor attempts to accept an interrupt, the interrupt reception starts a bus cycle, and based on the vector obtained from the interrupt controller, the processor determines whether or not the interrupt is an incomplete interrupt. can do. Furthermore, it is possible to recognize at what level an incomplete interrupt has occurred at the same vector capture timing as in conventional interrupt processing systems. Therefore, the processor can perform incomplete interrupt processing for the interrupt request source that caused the incomplete interrupt, while the processing and timing of the interrupt response from interrupt acceptance to branching to the interrupt processing routine remains the same as in the conventional system. can.

Also, the interrupt controller of the conventional interrupt processing method corresponds to one specific interrupt request input terminal! Since it was decided that the service routine at the priority level would be used when an incomplete interrupt occurred, it was virtually impossible to connect the interrupt request signal from Ilo, etc. in the system to the interrupt request input terminal. This has the advantage that interrupt request signals from Ilo, etc. in the system can be connected to all interrupt request input terminals of the interrupt controller.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the connection relationship between Ilo, an interrupt controller and a processor according to a first practical example of the present invention, FIG. 2 is a timing chart explaining the operation of this embodiment, and FIG. Processor 1 when an interrupt occurs
The two consecutive interrupt receptions activated by 01 are diagrams showing the formats of two vectors output by the interrupt controller 102 during the bus cycle. FIG. 4 is the interrupt vector table used in this embodiment, and FIG. 5 is a diagram explaining the second embodiment of the present invention, FIG. 6 is a diagram showing the third embodiment of the present invention, FIG. 7 is a timing chart explaining the operation of this embodiment, and FIG. 8 is a diagram showing the third embodiment of the present invention. In this embodiment, two successive interrupt receptions activated by the processor 101 when an interrupt occurs are shown in a diagram showing the format of two vectors output by the interrupt controller 102 during a bus cycle. Interrupt vector table to be used, FIG. 10 shows an example of the contents of the mask register 119, FIG. 11 shows the internal configuration of the incomplete interrupt detection circuit 108, and FIG. 12 shows one bit inside the register 115. FIG. 13 is a diagram for explaining the fourth embodiment of the present invention, and FIGS. 14 to 18 are diagrams for explaining conventional examples, respectively. Agent Patent Attorney Uchi Hara Oto

Claims (2)

[Claims] (1) It has a central processing unit, an interrupt controller, and a plurality of input/output biases, an interrupt request from the input/output device is input to the interrupt controller, and the interrupt controller receives the interrupt request from the plurality of input/output devices. and outputs an interrupt request signal to the central processing unit, and when the central processing unit accepts the interrupt from the interrupt controller, it activates an interrupt acceptance bus cycle for the interrupt controller, and the interrupt controller accepts the interrupt. In an information processing system that outputs an interrupt vector to the central processing unit during a bus cycle, a register located inside the interrupt controller and to which a value is set by the central processing unit;
a first means for outputting a value different from the contents of the register; a first selection means for inputting the outputs of the register and the first means; and a first selection means for inputting the outputs of the register and the first means; a second means for determining the priority and outputting the value of the highest priority interrupt request level; a holding means for holding information on the presence or absence of an interrupt request from the input/output device; and a second means for inputting the output of the holding means. a third means for determining the priority order and outputting the value of the highest priority interrupt request level; a second selection means for receiving the outputs of the second and third means; and detecting means for detecting that there is no interrupt request from the input/output device, and after the central processing unit accepts the interrupt request from the interrupt controller, , the first and second selection means are simultaneously controlled by the detection means to generate an interrupt vector from the contents of the register and the output of the second means 4, or the first and third selection means An interrupt processing device characterized in that the interrupt processing device selects whether to generate the output from the output of the interrupt processing device. (2) The interrupt processing device according to claim 1, further comprising an additional register located inside the interrupt controller and having a value set by the central processing unit, and according to the contents of the additional register, an interrupt request from the input/output device is processed. means for controlling the determination of priorities of the input/output device according to the contents of the additional register; means for masking and controlling interrupt requests from the input/output device according to the contents of the additional register and inputting the same to the detecting means; and means controlling the output of the holding means according to the contents of the additional register and means for mask-controlling and inputting the masked information to the third means.