JPH05224969A - Fault information processing system - Google Patents

Abstract

PURPOSE:To obtain a fault information processing system which can set various pseudo faults by providing a fault information bus independently of a processor bus and a fault control circuit which controls the conflicts of the fault information bus, sets a pseudo fault code, and performs other jobs. CONSTITUTION:A fault information processing system includes a processor bus 1, a bus contention control circuit 2 which controls the contention of the bus 1, a processor 3 which is connected to the bus 1 and carries out the main processing like the execution of instructions, etc., a main memory 4 which stores the instruction codes and the data, an input/output controller 5 which controls the external input/output devices, a cross control circuit 6 which secures the connection between the systems, a fault information bus 8, and a fault control circuit 9 which controls the contention of the bus 8. Then the fault codes and the pseudo fault codes are transmitted among the processors which are connected to the processor 3, the memory 4, the controller 5, etc., via the bus 8 set independently of the bus 1. Then the circuit 9 controls the conflicts of the bus 8 and sets the pseudo fault codes, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault information processing system in a processor system.

[0002]

2. Description of the Related Art A failure is unavoidable in a processor system. Therefore, when a failure occurs, appropriate processing is performed to minimize the influence on the system. In addition, in order to test the operation at the time of failure in advance, a function of generating a pseudo failure may be added.

FIG. 4 shows an example of the configuration of a conventional processor system. The processor 3, main memory 4,
The input / output control device 5 and the cross control circuit 6 are processor buses 1
And a bus contention organizing circuit 2 for organizing the contention of the processor bus 1. The processor bus 1 accommodates an address bus, a data bus, a control line, and an error reporting line, and each device drives as needed.

Further, the cross control circuit 6 is connected to a processor bus of another system via a cross control circuit of another system. Although the configuration of the other system is omitted, it has almost the same configuration and operates as a sub system for a failure.

When a device connected to the processor bus 1 uses the processor bus 1, a request line (not shown) attached to the processor bus 1 requests the bus use right to the bus contention control circuit 2 and the bus right is granted. Access will be started later.

At this time, when the device, for example, the input / output control device 5 detects the occurrence of a failure, if the error is in synchronization with the bus access, the processor 3 is notified as a bus access error signal on the processor bus 1. To report.

In the case of an error which is not synchronized with the bus access, the occurrence of the failure cannot be immediately notified by the processor bus 1. Therefore, the failure notification individual line 7 reports the fact to the processor 3.

The processor 3, which has received the report of the failure, transfers control to a predetermined failure processing routine and executes predetermined processing.

On the other hand, although not shown, in order to generate a pseudo fault, an individual line is provided between the processor 3 and another device, and the pseudo fault is generated according to an instruction from the processor 3.

[0010]

As described above, in the conventional processor system, the fault is reported by the processor bus or the fault notification individual line, and the pseudo fault is generated by the individual line. It was pointed out that such a defect.

The bus access error signal of the processor bus that reports a failure synchronized with the bus access may report information about where the bus access error occurred, because the number of signal lines is small and the amount of information is not sufficient. No, you cannot do fine-grained fault handling.

A fault notification individual line for reporting a fault that is not synchronized with bus access must be provided for each fault location and type, which is a mounting problem.

The individual line for setting the pseudo fault also has to be provided for each type of pseudo fault, which causes a problem in mounting.

The present invention has been proposed in view of the above points, and an object thereof is to provide fault information capable of transmitting detailed fault information and setting various pseudo faults. To provide a processing method.

[0015]

In order to achieve the above object, the present invention provides a processor system in which a processor, a main memory, an input / output control device and the like are connected via a processor bus, the processor system being provided separately from the processor bus. A failure information bus to be provided and a failure management circuit that sorts out the competition of the failure information bus and sets a pseudo failure code are provided.

[0016]

In the fault information processing system of the present invention, the fault code and the pseudo fault code are generated by using the fault information bus provided separately from the processor bus to which the processor, the main memory, the input / output control device, etc. are connected. Transmission takes place.
At this time, the fault management circuit sorts out the conflicts on the fault information bus and sets the pseudo fault code.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a processor system to which the fault information processing system of the present invention is applied.

In FIG. 1, a processor bus 1 according to the present embodiment, a bus contention organizing circuit 2 for organizing contention for the processor bus 1, and a processor 3 connected to the processor bus 1 for performing main processing such as instruction execution. , A main memory 4 in which instruction codes and data are stored, an input / output control device 5 for controlling an external input / output device, a cross control circuit 6 for connecting to another system, and a failure which is a feature of the present invention. Information bus 8 and fault management circuit 9 that sorts out its competition
It has and. The other systems connected via the cross control circuit 6 have substantially the same configuration, and the fault management circuits 9 of both systems are connected to each other.

FIG. 2 shows a configuration example of an interface circuit for the fault information bus 8 in the input / output control device 5 and the like. The fault detection circuit 12 for detecting a fault and the fault detected by the fault detection circuit 12 are shown. The fault code encoding circuit 13 for generating the fault code and the fault code generated by the fault code encoding circuit 13 for the fault information bus 8
The fault code sending circuit 14 for sending to the fault information bus 8
A pseudo fault code receiving circuit 15 for receiving a pseudo fault code from the pseudo fault code and a pseudo fault code decoding circuit 1 for decoding the pseudo fault code received by the pseudo fault code receiving circuit 15.
6 and a pseudo fault setting circuit 17 for generating a pseudo fault based on the decoded contents of the pseudo fault code decoding circuit 16.

The operation of the embodiment will be described below with reference to FIGS. 1 and 2.

When a device connected to the processor bus 1 uses the processor bus 1, a request line (not shown) attached to the processor bus 1 requests the bus use right to the bus contention control circuit 2 and the bus use right is granted. Access will be started later.
This point is no different from the conventional method.

A certain device, for example, the input / output control device 5
When a failure occurs in, the request line (not shown) attached to the failure information bus 8 requests the failure management circuit 9 for the right to use the bus, and after the request, the failure code is sent to the failure information bus 8.

Here, the fault code is transmitted as follows. That is, in FIG. 2, when the failure detection circuit 12 detects the occurrence of a failure, the failure code encoding circuit 1
3 generates a predetermined fault code, and the fault code sending circuit 1
4 sends a fault code to the fault information bus 8.

FIG. 3 shows an example of the format of the fault code 18, which includes a fault site identification code indicating the location of the fault,
It includes a detection device code indicating the detection location and a failure type code indicating the type of failure. The fault part identification code is mainly used for system configuration change processing by hardware, and the detection device code and the fault type code are mainly used for software fault processing.

The fault management circuit 9 interrupts the processor 3 by the interrupt notification line 10 when a fault code appears on the fault information bus 8.

The processor 3 receiving the interrupt fetches the fault code from the fault information bus 8, transfers control to a predetermined fault processing routine, and executes a predetermined process.

Further, the fault management circuit 9 decodes the fault code to identify the location of the fault, and when it determines that there is a fault in another system, it operates independently of the processor 3 by an independent operation by hardware. The other system disconnection instruction line 11 instructs the cross control circuit 6 to disconnect. As a result, the cross control circuit 6 does not accept any access from other systems, and it is possible to prevent disturbance of the faulty system.

On the other hand, when a pseudo fault occurs, the processor 3 informs each device in advance by the processor bus 1 or the like that the pseudo fault mode will be entered. As a result, the pseudo fault code receiving circuit 15 of the interface circuit of the fault information bus 8 of each device shown in FIG. 2 becomes operable.

After that, when the processor 3 writes a pseudo fault code corresponding to a pseudo fault to be generated in a register (not shown) in the fault management circuit 9, the fault management circuit 9
According to the pseudo fault code set in the register, the pseudo fault code is sent to the fault information bus 8. The pseudo fault code can use the same format as the fault code 18 shown in FIG. Also, when sending the pseudo fault code,
When a genuine failure occurs and the right to use the failure information bus 8 is requested, the failure management circuit 9 prioritizes it as a conflict management.

In each device connected to the fault information bus 8,
In FIG. 2, the pseudo fault code receiving circuit 15 receives the pseudo fault code from the fault information bus 8, the pseudo fault code decoding circuit 16 performs decoding, and the pseudo fault setting circuit 17 generates a pseudo fault based on the result. Let It should be noted that the fault code sending circuit 14 gives a signal for prohibiting reception to the pseudo fault code receiving circuit 15 so that when the fault to be reported occurs, the pseudo fault code is not responded. It is given priority.

[0032]

As described above, the failure information processing system of the present invention has the following effects.

Since the occurrence of a failure is reported by a dedicated failure information bus, sufficient information indicating the location and type of failure can be placed, and fine-grained failure processing can be performed.

Since the fault information bus can be used to report a fault by clearly indicating the location and type of the fault regardless of the synchronization with the bus access, it is sufficient to provide one set of fault information buses. , Does not matter.

Since various pseudo faults can be set using the fault information bus, mounting problems can be solved, and a highly reliable system can be constructed by using various pseudo fault settings. It becomes possible to do.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a processor system to which a failure information processing system of the present invention is applied.

FIG. 2 is a configuration diagram showing an example of an interface circuit with a fault information bus provided in each unit such as a main memory and an input / output control device.

FIG. 3 is a diagram showing an example of a format of failure information.

FIG. 4 is a configuration diagram of a conventional processor system.

[Explanation of symbols] 1 ... Processor bus 2 ... Bus contention control circuit (BA) 3 ... Processor (CPU) 4 ... Main memory (MM) 5 ... Input / output control unit (IOC) 6 ... Crossover control Circuit (XC) 7 ... Fault notification individual line 8 ... Fault information bus 9 ... Fault management circuit (FDP) 10 ... Interrupt notification line 11 ... Other system disconnection instruction line 12 ... Fault detection circuit 13 ... Fault code encoding circuit 14 ... fault code sending circuit 15 ... pseudo fault code receiving circuit 16 ... pseudo fault code decoding circuit 17 ... pseudo fault setting circuit 18 ... fault code

Claims (3)

[Claims] 1. In a processor system in which a processor, a main memory, an input / output control device, etc. are connected via a processor bus, a fault information bus provided separately from the processor bus, and a contention reduction and pseudo fault of the fault information bus. A fault information processing system comprising a fault management circuit for setting a code and the like. 2. The fault management circuit performs system configuration change processing independently of the processing of the processor.
Fault information processing method described. 3. An interface circuit for a fault information bus, a fault detection circuit for detecting a fault, a fault code encoding circuit for producing a fault code according to a fault detected by the fault detection circuit, and a fault code encoding circuit Fault code sending circuit for sending fault code to fault information bus, pseudo fault code receiving circuit for receiving pseudo fault code from fault information bus, and pseudo fault code decoding for decoding pseudo fault code received by pseudo fault code receiving circuit 3. The fault information processing system according to claim 1, further comprising a circuit and a pseudo fault setting circuit that generates a pseudo fault based on the decoded contents of the pseudo fault code decoding circuit.