JPH0241551A - Interrupt handling method for specifying destination - Google Patents

Abstract

PURPOSE:To perform the interrupt handling with a destination specified by reporting a cancel processing code in case of a CPU other than a designated CPU but reporting an interrupt vector to indicate execution of prescribed interrupt handling in case of the designated CPU. CONSTITUTION:At the time of response to an interrupt request, systems 1 and 2 have means which report the interrupt level as well as system discrimination information to an input/output device 3, and a system discriminating part 5 has a means which analyzes this system discrimination information to discriminate coincidence with contents of a system designation register 6. That is, the system where the processing should be performed is preliminarily designated to the system designation register 6, and the system discriminating part 5 discriminates whether the value in the system designation register 6 and system discrimination information reported from systems coincide with each other or not at the time of response, and the vector is reported in case of coincidence but the cancel code is reported in case of disaccord. Thus, the input/output device copes with only the response from the system preliminarily designated in the system designation register 6, and interrupt handling with the destination specified is possible.

Description

[Detailed Description of the Invention] [Summary] Regarding an interrupt processing method for input/output devices in a system having multiple CPUs, an input/output device that can perform interrupt processing with a specified destination regardless of the number of CPUs and input/output devices is provided. The purpose is to provide an interrupt processing method for an output device, and each CPU is provided with means for notifying the input/output device of response information including system identification information when receiving an interrupt request from the input/output device. The input/output device includes a means for commonly issuing an interrupt request to the plurality of CPUs, and a means for determining whether the CPU is the one designated by the CPU based on system identification information notified from the CPU that accepted the interrupt request. and a means for determining the CPU's specified CPU based on the result of the determining means.
If the CPU is not a PU, the cancellation processing code is notified to the CPU, and if the CPU is the CPU specified by the CPU, an interrupt vector specifying execution of a predetermined interrupt processing is sent to the CPU by 1 cp.
and a means for notifying u.

[Industrial application field]

The present invention relates to an interrupt processing method for an input/output device in a system having a plurality of CPUs (synonymous with central processing unit, referred to as CPU in this specification).

[Conventional technology]

In recent years, multiple CPs have been installed for the purpose of improving processing power and reliability.
Multi-CPU systems and multiplex systems using U have been introduced.

When interrupt processing is necessary in this multi-CPU system or multiplex system, it is performed in the following interrupt processing sequence during boat fishing.

(1) When an input/output device requests the CPU or system (hereinafter referred to collectively as the system) to perform some kind of processing,
First, the input/output device issues an interrupt request to all systems.

(2) Next, the system that obtained the right to use the bus the fastest notifies the input/output device of the accepted interrupt level (hereinafter also referred to as response).

(3) Then, the input/output device notifies the system of the interrupt vector (hereinafter also referred to as vector notification), and the system starts necessary processing according to the vector.

By the way, with regard to this interrupt processing, there are many cases where it is desired to request processing only to a specific CPU among a plurality of CPUs, and in such cases, the general interrupt processing sequence described above cannot be used.

Conventionally, systems have been identified using the following two methods.

(a) Provide a dedicated interrupt request signal for each system.

) Allocate an interrupt level to each system, and identify the system by the interrupt level used.

[Problems to be Solved by the Invention] When the number of systems and input/output devices is large, the following problems occur with the two methods described above.

(1) Since a dedicated signal line is required for each system and input/output device, the amount of hardware increases, and it is not easy to change the system.

(2) Since interrupt levels are assigned to each system, the number of interrupt levels that can be used by other systems is reduced.

Therefore, in view of the above problems, it is an object of the present invention to provide an input/output device that can perform interrupt processing with a specified partner, regardless of the number of systems and input/output devices.

[Means to solve the problem]

FIG. 1 is an explanatory diagram of the principle of the present invention, taking a duplex system as an example.

In the figure, 1.2 is the brown system in the duplex system, 1 is the A system, and 2 is the B system. 3 is an input/output device controlled by both systems, 4 is a bus connecting 1, 2, and 3, 5 is a system determination section, and 6 is a system specification register.

When responding to an interrupt request, the system 1.2 has means for notifying the input/output device 3 of the interrupt level and system identification information,
The system determination unit 5 has means for analyzing the system identification information and determining whether it matches the system designation register 6. Also, input/output device 3
has means for notifying a cancel code instead of a vector when notifying a vector if there is a mismatch based on the determination result of the system determining unit 5.

[For production]

In the present invention, the system to be processed is specified in the system specification register 6 in advance, and at the time of response, the system determination unit 5 determines whether the value of the system specification register matches the system identification information notified from the system. If there is a match, a vector notification is sent, and if there is a mismatch, a cancellation code is sent.

Therefore, only responses from the systems specified in advance in the system designation register 6 are handled, making it possible to perform interrupt processing with a specified partner.

〔Example〕

FIG. 2 shows a configuration diagram of an embodiment of the present invention, and is an example of a duplex system.

In this figure, only the parts related to the present invention are shown for ease of explanation and understanding, and the same parts as shown in FIG. 1 are indicated by the same symbols, and 1 is A system in the duplex system, 1a is the CPU of the A system, lb is the system bus of the A system, IC is the bus adapter of the A system, 2 is the B system of the duplex system, and 2a is the CPtJ of the B system.

2b is the system bus of the B system, 2C is the bus adapter of the B system, 3 is the input/output device, 4 is the bus, 4a is the address bus in the bus 4, 4b is the data bus in the bus 4, 5 is the input/output device The system determination unit 6 represents a system designation register in the input/output device.

In the A system 1, the CPU 1a and the bus adapter IC are connected by the system bus 1b, and the bus 4 is connected via the bus adapter IC.
is connected to. The B system 2 also has a similar configuration. The input/output device 3 is connected to the bus 4, and the bus 4 is composed of an address bus 4a and a data bus 4b, and the address bus 4a is used for notification of address information, interrupt level at the time of interrupt response, system identification information, etc. The data bus 4b is used for notification of vectors or cancellation codes when notifying data and vectors. In the input/output device 3, a system determination section 5 and a system designation register 6 are provided.

FIG. 3 shows an example of the configuration of the system determination section in the embodiment, where (a) is a circuit block diagram of the system determination section, and FIG. 3(b) is a truth table explaining the operation of the system determination section. It shows.

In Fig. 3(a), 4a' is A system 1 during interrupt response.
Alternatively, the address bus sent from B system 2 has a 32-bit configuration (the bits are indicated by the symbol b in the figure), and b1 to
b3 contains the interrupt level, and b4 to b7 contain system identification information. Further, in the system determination unit 5, 5a is a comparison circuit that determines whether the system designation register 6 matches the system designation information field in the address bus 4a, and 5b is a match signal that indicates the determination result of the match circuit, that is, whether it is a match or a mismatch. , 5C is a system determination control signal indicating whether or not the value of the system specification register 6 is valid, that is, whether or not to perform interrupt processing that specifies the other party. 5d is a system determination control signal that indicates whether to notify a vector or notify a cancellation code at the time of vector notification. It represents a cancellation control signal indicating whether to do so.

The truth table shown in FIG. 3(b) shows the logical relationship for obtaining the cancellation control signal 5d as the output result, using the system judgment control signal 5C and the coincidence signal 5b as human input conditions, and shows the operation of the system judgment unit 5. This is to help you better understand.

In this truth table, true indicates that the signal is valid, false indicates that the signal is invalid, and "X" indicates that the signal may be valid or invalid.

The operation of the interrupt processing method of the present invention will be explained below. (1) First, a normal interrupt processing sequence that does not require specifying the other party will be explained. First, the input/output device 3 makes the system determination control signal 5C false and issues an interrupt request.

The request passes through the bus, bus adapter, and system bus.
CPU1a.

2a will be notified. Of the CPUs 1a and 2a, the one that obtains the right to use the bus first responds. That is, the interrupt level and system identification information are notified to the input/output device 3 via the system bus, bus adapter, and bus. Then, the system determination unit 5
A match determination is made in . In this case, since the system determination control signal 5C is false, the cancellation control signal is false (third
(see figure (b)), the vector is notified to the CPU,
Interrupt processing begins.

(2) Next, the interrupt processing sequence for identifying the other party will be explained. In this case, the input/output device 3 receives the system determination control signal 5
Set C to true, specify the system to be processed in the system specification register 6, and issue an interrupt request. The following explanation assumes that system A is specified. The request is notified to the CPUs 1a and 2a of both systems via the same route as explained in section (1).

If the A system responds, the judgment result of the system judgment unit is a match, the cancellation control signal 5d becomes false (see Fig. 3(b)), the vector is notified to the CPU 1a, and interrupt processing is started. Ru.

However, if system B responds, system judgment B5
The determination result is a mismatch, the cancellation control signal 5d becomes true (see FIG. 3(b)), and the CPU 2a is notified of the cancellation code.

〔Effect of the invention〕

As explained above, according to the present invention, an interrupt processing request to a specific system can be executed without deteriorating the function due to an increase in the system scale, thereby improving the performance of the input/output device. There is a lot to contribute.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a configuration diagram of an embodiment of the invention, and FIG. 3 is a configuration example of a system determining section in the embodiment. ■...A system in the dual system, 2...B system in the dual system, 1a...CPU of the A system, 1b...system bus of the A system, IC...bus of the A system Adapter, 2a・
...B-system CPtJ, 2b...B-system system bus,
2C... B system bus adapter, 3... Input/output device,
4... bus, 4a... address bus, 4a... address bus contents, 4b... data bus, 5... system determination section, 5a... comparison circuit, 5b... match signal ,5
C... System determination control signal, 5d... Cancellation control signal, 6... System specification register

Claims (1)

[Claims] In the case where a plurality of CPUs constituting a multi-CPU system or a multiplexed system are commonly connected by a bus, and an input/output device is connected to the bus, the plurality of input/output devices are connected to the bus. A method of processing interrupts for a CPU, wherein each CPU is provided with means for notifying the input/output device of the interrupt level and system identification information when the CPU receives an interrupt request from the input/output device; The device includes a means for commonly issuing an interrupt request to the plurality of CPUs, and a means for determining whether or not the CPU is the CPU designated by the device, based on system identification information notified from the CPU that has accepted the interrupt request. and means for determining whether the CPU uses the CPU specified by the CPU based on the result of the determining means.
If the CPU is not the PU, the cancellation processing code is notified to the CPU, and if the CPU is the CPU specified by the CPU, an interrupt vector instructing execution of the predetermined interrupt processing is sent to the CPU.
By providing means for notifying the CPU, the CPU that has responded to the interrupt request is identified, and only the specific CPU executes the interrupt process, while other CPUs perform the cancel process. Interrupt handling method.