JPH0713879A - Bus connecting device - Google Patents

Abstract

PURPOSE:To prevent an input/output controller from being disabled to be specified in case of write abnormality when the input/output controller which makes a bus use request performs a high-speed process with a write-and-run method by using a buffer in the bus connecting device by connecting a high-speed bus including a memory and a low-speed bus to which plural input/output controllers are connected by the bus connecting device. CONSTITUTION:The permission number (corresponding to the ID number, one to one) of the input/output controller 10 or 11 which makes the request use a bus 50 and then is allowed is stored in the buffer 105 together with information (b) on a write address, etc. If a write error occurs, the permission number (j) at this time is read out of the buffer 105 and the ID number (n) corresponding to the number is retrieved in a ROM 110 and reported to a CPU 20 by interruption. The CPU 20 can specifies the input/output controller at the time of the write error from the ID and an error process is facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus connecting device, and more particularly to a bus connecting device for logically connecting a high speed system bus including a memory and a low speed system bus to which a plurality of input output control devices are connected. Is.

[0002]

2. Description of the Related Art In the prior art, a memory write operation from an input / output control device is performed when a low speed bus and a high speed memory bus are logically directly connected by a bus connection device and the input / output control device writes to the memory. Often locks the bus until there is a response from. However, in this method, both the low-speed bus and the high-speed bus are used at the same time for a certain time, so the bus efficiency is poor.

Therefore, a so-called "data writing escape" method is adopted. When the I / O controller executes a write operation to the memory, the bus connection device terminates the bus cycle when it receives the address and data and loads it into the buffer, apparently high-speed memory write. To end.

If there is memory write information in the buffer, the bus connection device independently sends the information to the memory on the high speed bus to execute the memory write.

However, in the conventional data write escape system of this type, even if the bus connection device receives an abnormality report at the time of memory write, the input / output control device which actually outputs the data ends the bus cycle. It cannot be determined to which input / output control device the previous memory write abnormality notification is to be reported.

Therefore, a method is adopted in which the subsequent memory write service is stopped or the bus connection device itself prohibits all bus arbitration, and the abnormal processing is entrusted to a time-out processing by software.

[0007]

In the above-described conventional write-escape method, since the input / output control device that has executed the write-out cannot be identified when an error report is received, all the devices on the low-speed bus are disconnected. . This is a result in which although the write escape data is normal, although the memory write actually performed by the bus connection device is abnormal, the software apparently determines that the input / output control device under the low-speed bus is abnormal.

The cause of the memory write abnormality may not be the bus connection itself. There is also a drawback in that it is difficult to determine a specific input / output control device even if interrupted as an abnormality notification from the bus connection device or as software.

It is an object of the present invention to provide a bus connection device which can specify an input / output control device when a write process is abnormal in the write escape system so that the abnormal process can be performed easily and accurately. Is.

[0010]

According to the present invention, a bus connection for logically connecting a high-speed bus to which a memory and a central processing unit are connected and a low-speed bus to which a plurality of input / output control devices are connected. A device for permitting use while performing bus arbitration in response to a request for use of the low-speed bus from the input / output device; identification information for identifying the input / output device for which use is permitted; Storage means for storing the address information of the use request and the memory write data in association with each other, a means for performing a writing process to the memory according to the address information and the write data stored in the storing means, and an abnormality of this writing process. A bus connection device is obtained which includes a reporting means for responding and reporting the identification information at that time to the central processing unit.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of the present invention. In the figure, a plurality of input / output control devices 10, 1
1 is connected to the low-speed bus 50, and the bus connection device 10
It is logically connected to the high speed bus 40 via 0. The central processing unit 20 and the main memory 30 are connected to the high speed bus 40.

Input / output control devices 10 and 11 via a plurality of stages of buffers 105 provided in the bus connection device 100.
The so-called "write escape method" is used to perform a write request process from the computer to the main memory 30.

Reference numeral 101 is a bus driver, and 102
Is a bus receiver. 103 is a parity detection circuit, 104 is a decoder, 106-109 are registers, 1
13 is a selector, 114 is an error counter, and 115 is an AND gate.

The buffer 105 is an input / output control device 10, 1.
The write address and write data b permitted for the low speed bus use request e from 1 are stored, and the use permission number i is also stored correspondingly.

A ROM (Read Only Memory) 110 uses the permission number j stored in the buffer 105 as a search address, and the input / output control device 1 corresponds to this search address.
This is a memory in which ID (identification number) codes n of 0 and 11 are stored in advance.

Before the I / O controller 10 executes a memory write, it first outputs a bus request e to the bus connection device 100 in order to use the low speed bus 50.

The bus connection device 100 determines the priority of low-speed bus use by the encoder 112 and the decoder 111, and gives the bus use permission to the input / output control device 10 by the bus use permission signal f.

The I / O controller 10 activates a memory write cycle on the low speed bus 50. The bus connection device 100 performs a parity check on the activated address and data a by the check circuit 103, and if there is an error, the status line d
Then, the I / O controller 10 is notified of the abnormality within the memory cycle of the low-speed bus. I / O controller 1 if there is no abnormality
0 indicates a bus use request for executing the next memory write cycle in a DMA (direct memory access) operation and repeats the above operation.

On the other hand, the bus connection difference device 100 loads the received normal memory write information b into the buffer register 105. At this time, the permission number i (held in the register 107) that was given permission in the previous bus arbitration is also loaded. With this series of operations, the memory write cycle of the low speed bus is completed.

The buffer register 105 executes memory write to the main memory 30 connected to the high speed bus 40 if there is at least one memory write information. At this time, the permission number j in the buffer register 105 is guided to the input of the register 106 without being output to the high speed bus.

When the decoder 104 of the detection circuit detects that there is an abnormality report from the main memory, the same buffer register is used again to retry the memory write to the high speed bus.

On the other hand, when an abnormality is detected during the write processing, the abnormality signal 1 is input. However, when the error signal of the decoder 104 which has detected the abnormality is counted up by the error counter 114 and reaches the specified number, the AND signal is ANDed. Gate 1
With the output signal k of 15, the permission number j at this time is registered in the register 10
Set to 6. The output m of the register 106 is the ID code n corresponding to the input / output control device 10 or 11 in the ROM 1
It is searched from 10 and set in the register 109.

It is assumed that the ID codes of the input / output control devices 10 to 11 which are connected to the low-speed bus in advance are associated with the bus use request line.

The bus connecting device 100 uses the ID code p set at the time of a retry error to make the input / output control device 1
Instead of 0, the central processing unit 20 is notified of a memory write retry error on the interrupt request line q.

When the central processing unit 20 accepts this interrupt request, the error counter 114, the register 109 and the register 106 are reset to prepare for the next retry error. The selector 113 switches between an interrupt from the low speed bus 50 and an internal interrupt.

On the other hand, the I / O controller 10 which has completed the operation of the DMA memory write does not recognize the abnormality on the high-speed bus 40, and through the interrupt line g, the central processor 20
An interrupt request to end the series of normal processing. However, since the bus connection device 100 itself has already issued the error interrupt notification due to the retry error on the high-speed bus 40, the retry or abnormal processing by software is executed.

On the other hand, the other input / output control device 11 can execute data transfer without any influence.

In the above embodiment, the I / O controller I
Although the D number is searched in the ROM 110 by using the bus use permission number, when the bus use request e is generated, the ID number of the input / output control device that generated the request is used as it is, and the ID information i is stored in the buffer 105. If it is stored as, the ROM 110 becomes unnecessary.

[0030]

As described above, according to the present invention, the identification information for identifying the input / output control device permitted to use the bus is provided.
It is stored in the buffer together with the memory write information, and when the memory write is abnormal, the identification information at that time is read out and the CP
Since it is reported to U, the CPU has the effect of being able to know the input / output control device when an abnormality occurs.

Further, since the ID information of the input / output control device at the time of occurrence of the memory write abnormality is reported to the CPU by the interruption, the low speed bus and the high speed bus can be connected without disconnecting other input / output control devices from the system. There is also an effect that the write escape of the memory write process can be realized by using the buffer between.

Further, even if the priority order of each input / output control device is changed on the bus, if the ID number is not changed, it is not necessary to change the hardware and the system can be easily changed.

[Brief description of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

[Description of Reference Signs] 10, 11 Input / output control device 20 CPU 30 Main memory 40 High-speed bus 50 Low-speed bus 100 Bus connection device 105 Buffer 110 ROM 111 Decoder 112 Encoder 113 Selector 114 Error counter 115 AND gate

Claims (3)

[Claims] 1. A bus connection device for logically connecting a high-speed bus to which a memory and a central processing unit are connected and a low-speed bus to which a plurality of input / output control devices are connected. Means for permitting use while arbitrating the bus in response to the request for use of the low-speed bus, identification information for identifying the input / output device permitted to use, address information of the use request, and memory write data. In correspondence with the address information and write data stored in the storage means, and the identification information at that time in response to an abnormality in the writing process. A bus connecting device comprising: a reporting unit for reporting to the central processing unit. 2. The reporting means is configured to perform retry control a predetermined number of times when the writing process is abnormal and to make the report when the number of retries reaches the specified number of times. Claim 1 characterized by the above.
Bus control device as described. 3. The bus control device according to claim 1, wherein the reporting means is configured to make an interrupt request to the central processing unit using the identification information.