JP2560312B2 - Information processing system - Google Patents

Description

The present invention relates to an information processing system, and more particularly to an interrupt processing system by an interrupt controller and a central processing unit when an incomplete interrupt occurs.

<Prior Art> In an information processing system, a central processing unit (hereinafter abbreviated as a processor) needs to exchange information with some input / output devices (hereinafter abbreviated as I / O) in addition to a memory. To improve system throughput, I /
The service to O is done by an interrupt. An I / O that requires service from the processor activates an interrupt request signal to the processor. When the processor in the interrupt enabled state recognizes an interrupt, it interrupts the execution of the program up to that point and transfers control to the interrupt processing program (interrupt service routine) to service the interrupt processing program I / O.

If there are many I / Os in the information processing system,
An interrupt controller is used that arbitrates the interrupt request from each I / O according to the priority and sends it to the processor. The interrupt controller receives interrupt requests from some I / Os and notifies the processor of the presence or absence of interrupt requests. This notification signal will be called an INT signal. The processor inputs IN from the outside of the processor until the execution of one instruction is finished and the execution of the next instruction is started.
When the T signal is sampled and the INT signal is active and the processor can accept the interrupt, the processor starts an internal interrupt acceptance process, and first outputs the interrupt acceptance signal. When the interrupt controller receives the interrupt acceptance signal, it sends a vector containing information capable of identifying the interrupt request source having the highest priority among the input interrupt requests to the processor. The processor branches to the service routine for the interrupt request source by analyzing the vector obtained from the interrupt controller.

FIG. 9 is a block diagram of an information processing system including a processor and an interrupt controller. 1001 is a processor, 1002 is an interrupt controller capable of processing eight interrupt requests, 1003 is one I / O, 1004 is an interrupt request signal from I / O 1003, 1005 is the INT signal from the interrupt controller 1002, Reference numeral 1006 indicates an interrupt acceptance signal from the processor 1001, and reference numeral 1007 indicates a data bus of the information processing system. Below, the processor 1001 is in a state where it can accept interrupts, and the interrupt controller 1002 has only one
Consider a case where only one interrupt request 1004 from the I / O 1003 is active. Interrupt request 1 from the I / O1003
When 004 becomes active, the INT signal 1005 from the interrupt controller 1002 becomes active and notifies the processor 1001 that an interrupt request has occurred.

The processor 1001 sends the INT signal 1101 as shown in FIG.
After detecting that the INT signal 1005 is active, the interrupt request 1004 from the I / O 1003 continues to be active until the interrupt acceptance signal 1006 is output. Interrupt processing is performed. That is, when the processor 1001 accepts an interrupt, the interrupt acceptance / bus cycle is continuously activated for two cycles. In each interrupt acceptance bus cycle, the processor 1001 outputs an interrupt acceptance signal 1006 to the interrupt controller 1002.
In the first interrupt acceptance bus cycle, the interrupt controller 1002 determines to request the processor 1001 to service the interrupt request input having the highest priority level among the active interrupt request inputs. In this example, since only one interrupt request 1004 is active, the interrupt controller 1002 in the first interrupt acceptance bus cycle
Determine to request service from the processor 1001. In the second interrupt acceptance bus cycle, the interrupt controller 1002 outputs a vector including the priority of the interrupt request 1004 to the data bus 1007, and the processor 1001 receives the vector. As a result, processor 10
01 saves the program counter and information indicating the running state of the program interrupted by the interrupt in the stack, and then branches to the interrupt service routine for the I / O 1003 based on the vector.

The vector passed from the interrupt controller 1002 to the processor 1001 has the format shown in FIG. That is, the vector 1201 having an 8-bit width passed from the interrupt controller 1002 to the processor 1001 has a 5-bit address corresponding portion 1202 corresponding to the address in the vector 1201, and this address corresponding portion 1202
Can be preset from the processor 1001 to the interrupt controller 1002. 1203 is the vector 1201
Is an encoding part in which the priority level of the interrupt request is encoded into 3 bits. The interrupt controller 1002 assigns 8 levels of priority to the 8 interrupt requests, and when the processor 1001 accepts the interrupt,
The priority level of the interrupt request to be serviced among the interrupt requests of the book is encoded into 3 bits and shown in 1203 of the vector 1201 to the processor 1001. In this example, for example, if the interrupt request 1004 from the I / O 1003 is connected to the interrupt request input terminal corresponding to the priority level 3 of the interrupt controller, the binary part is included in the encoding part 1203 in the vector 1201 for the interrupt request 1004. 011 comes in.

The processor 1001 uses the vector 1201 obtained from the interrupt controller 1002 to generate a 16-bit address 1301 as shown in FIG. The address 1301 indicates the position of the entry corresponding to the priority level of the interrupt request 1004 in the vector table prepared in the memory.
In this example, each entry in the vector table contains
It is assumed that the information regarding the start address of the service routine of the interrupt of the priority level indicated by the entry is stored. The processor 1001 first accesses the entry in the vector table by the vector to obtain information on the start address of the interrupt service routine. Then, according to the information, control is transferred to the start address of the interrupt service routine.

FIG. 14 is a flowchart showing the flow of a conventional interrupt process. The processor 1001 executes one instruction (150
1) Determine whether the INT signal from the interrupt controller 1002 is active (1502), and if the INT signal is active, the processor 1001 activates the interrupt acceptance bus cycle twice in succession. In the second interrupt acceptance bus cycle, a vector is fetched from the interrupt controller 1002 (1503). The processor 1001 uses the vector to service the interrupt in the vector table.
The routine entry is accessed (1504) to get information about the start address of the service routine for the interrupt. Next, the processor 1001 saves information indicating the running state of the program interrupted by the program counter or the interrupt to the stack (1505), and then transfers control to the start address of the service routine for the interrupt (1506). . When the processing of the service routine for the interrupt is completed, the information such as the program counter saved in the stack is restored from the stack by executing the return instruction from the interrupt at the end of the service routine, and the interrupt is executed. Transfer control to the interrupted program (1507).

On the other hand, when the processor 1001 samples the INT signal 1005 at the timing 1401 as shown in FIG. 13, the interrupt request 1004 from the I / O 1003 was active, but the processor 1001 output the interrupt acceptance signal. At times, when the interrupt request 1004 from the I / O 1003 is inactive, the interrupt controller 1002 cannot send the vector indicating the interrupt request source to the processor 1001 in response to the input of the interrupt acceptance signal 1006. An interrupt input at the timing shown in FIG. 13 will be called an incomplete interrupt. The incomplete interrupt occurs when the I / O independently generates and deletes the interrupt request. In this case, when the I / O issues an interrupt request once and then erases the request, it is considered that the I / O does not require service by the processor. In a conventional information processing system, when such an incomplete interrupt occurs, the interrupt controller 1002 includes a priority level which is determined to be used when the incomplete interrupt occurs to the processor 1001 during the interrupt acceptance bus cycle. An incomplete interrupt vector is output, the processor 1001 receives the incomplete interrupt vector without knowing that it is an incomplete interrupt, and directly executes the incomplete interrupt process as one of the normal interrupt processes described in FIG. Was.

<Problems to be Solved by the Invention> As described above, in the conventional information processing system, even though the interrupt request source I / O 1003 erases the interrupt request because the processor does not need service, the processor 1001 When the incomplete interrupt is accepted, execution of the program up to that point is interrupted, information such as the program counter is saved in the stack, the incomplete interrupt vector is analyzed, and the start address of the incomplete interrupt processing routine is read from the vector table. Information was obtained and control was transferred to the incomplete interrupt processing routine. However, in the incomplete interrupt processing routine, there is no particular processing to be executed, and the return instruction to the program is executed by accepting the incomplete interrupt, and the execution of the return instruction causes the processor to save the program counter in the stack. Control was returned to the execution of the program interrupted by the incomplete interrupt by taking out the information such as. Despite not performing substantial control in this incomplete interrupt processing, the processor 1001 fetches the vector from the interrupt controller 1002 and then accesses the vector table and stack in the memory outside the processor 1001. Especially, it is necessary to perform a wasteful process such as a process in an incomplete interrupt processing routine having no process to be executed and an access to a stack for returning control to the execution of the program interrupted by the incomplete interrupt. In other words, in the conventional interrupt processing method, even if an incomplete interrupt occurs, the program interrupted by the incomplete interrupt cannot be directly returned, and the same interrupt path must be taken.

As a result, the processor accepts the incomplete interrupt without knowing it as an incomplete interrupt and performs the incomplete interrupt process as one of the normal interrupt processes described above, thereby substantially eliminating the waste during execution of the original program. However, there is a problem that it hinders the improvement of the throughput of the entire system. Furthermore, since the interrupt request signal from the I / O in the system cannot be connected to the interrupt request input terminal corresponding to the priority level decided to be used when an incomplete interrupt is generated by the interrupt controller, There was also a problem that the I / O that can be connected to the interrupt controller decreased.

Therefore, an object of the present invention is to provide an information processing system which can effectively use an interrupt controller and can prevent a decrease in throughput at the time of an incomplete interrupt.

<Means for Solving Problems> The gist of the present invention has a central processing unit, an interrupt controller, and a plurality of input / output devices, and when an interrupt request from the input / output device is input to the interrupt controller, The interrupt controller arbitrates interrupt requests from the plurality of input / output devices and outputs an interrupt request signal to the central processing unit, and the central processing unit responds to the interrupt request signal from the interrupt controller to generate the interrupt. In an information processing system in which an interrupt acceptance bus cycle is activated at least twice in a controller, and the interrupt controller outputs a vector to the central processing unit during the interrupt acceptance bus cycle, the interrupt controller includes the central processing unit. Does the device accept the interrupt request signal from the interrupt controller? Detection means for detecting that all interrupt requests from the input / output device to the interrupt controller have disappeared during the period from the start of the interrupt acceptance bus cycle to the interrupt reception bus cycle, and the first detection based on the detection result of the detection means. Means for causing the interrupt controller to output a vector different from the vector transmitted in the interrupt acceptance bus cycle to the interrupt controller in the acceptance bus cycle in the second cycle,
This is to recognize the disappearance of the interrupt request based on the difference between the two vectors and terminate the interrupt operation.

<Operation> In the information processing system having the above configuration, when an interrupt request is issued from the input / output device, the interrupt controller outputs an interrupt request signal to the central processing unit after arbitration of the interrupt. However, even if the input / output device subsequently cancels the interrupt request, the central processing unit activates the interrupt acceptance bus cycle based on the interrupt request signal and suspends the program being executed. However, under such circumstances, the interrupt controller sends a vector indicating request disappearance to the central processing unit, unlike the first vector which is output during normal interrupt processing through the second interrupt acceptance bus cycle. The processing unit can terminate the interrupt operation.

<Embodiment> FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, and FIG. 2 is a flow chart for explaining the operation of the first embodiment of the present invention. In FIG. 1, 101 is a processor, 102 is an interrupt controller, and 103 is an input / output device.

When the interrupt controller 102 notifies the processor 101 in this embodiment that an interrupt has occurred, the processor 101 activates the interrupt acceptance bus cycle twice in succession. In the conventional interrupt controller, the interrupt acceptance signal 106 output in association with the first interrupt acceptance bus cycle is used only for determining the interrupt priority within the interrupt controller. In 102, the vector is output even in the first interrupt acceptance bus cycle activated by the processor 101. The format of the vector 301 is, as shown in FIG. 3, different from the vector format 1201 output in the conventional second interrupt acceptance bus cycle, as shown in FIG. And a portion 303 indicating a 3-bit priority level,
In the vector 301 output in the first interrupt acceptance bus cycle, the information in the 303 portion is meaningless. In the interrupt controller 102 of this embodiment, the vector 304 output in the second interrupt acceptance ass cycle activated by the processor 101 has exactly the same format as the conventional vector 1201. That is, in the vector 304, 305 is a portion corresponding to a 5-bit address preset by the processor 101 and is stored in the register 111. 306 is a portion indicating a 3-bit priority level, which is output from the priority determination circuit 113.

The interrupt controller 102 outputs the vectors 301 and 304 for each of the two interrupt acceptance bus cycles activated by the processor 101, and when a normal interrupt occurs, it corresponds to the 5-bit address of the vector 304 305.
A 5-bit address preset by the processor 101 is output to the portion of. However, when an incomplete interrupt of the timing shown in FIG. 4 occurs, that is, the processor 101 outputs the INT signal 105 at the timing 401.
When the first interrupt-accepting bus cycle of two interrupt-accepting bus cycles is activated after sampling
When the interrupt request signal 104 from the I / O 103 is not already active, the interrupt controller 102 detects by the incomplete interrupt detection circuit 108 that an incomplete interrupt has occurred, and the second interrupt acceptance bus cycle 403 is notified. 5 is preset by the processor 101 in the portion 305 corresponding to the 5-bit address of the vector 304 to be output as
Information different from the bit address is written and output. For example, when an incomplete interrupt occurs, vector 30
In the portion 305 corresponding to the 5-bit address of 4, the information obtained by inverting each bit of the 5-bit address preset by the processor 101 by the inverter 109 is data.
Output to bus 107. FIG. 8 shows the incomplete interrupt detection circuit 108.
Is a specific example. 801 is an 8-input OR gate, 802 is an eight interrupt request input signal input to the interrupt controller 102, 803 is a D-type flip-flop (DFF), and output data is the output of the 8-input OR gate 801. Then, the strobe signal is the interrupt acceptance signal 106. Therefore, the output 110 of the D-type flip-flop 803 is "" when all eight interrupt request input signals input to the interrupt controller 102 when the strobe signal interrupt acceptance signal 106 is active. It becomes 0 "and is supplied to the selector 112 as a selection signal.

Referring again to FIG. 1, when the selection signal 110 is "0", the selector 112 is in the register 1 during the interrupt acceptance bus cycle.
Information obtained by inverting the contents of 11 by the inverter 109 is output to the data bus 107. On the other hand, the selection signal 110 is "1"
At this time, the selector 112 outputs the content of the register 111 as it is to the data bus 107 during the interrupt acceptance bus cycle.

Next, the operation of the first embodiment will be described. The processor 101 executes one instruction (201), and then the interrupt controller 102
Determine if INT signal 105 is active (20
2) If the INT signal 105 is active (Yes), the interrupt acceptance bus cycle is activated twice in succession and the vectors 301 and 304 are fetched from the interrupt controller (203 and 20), respectively.
Four). In FIG. 2, vector fetch (1) means that the processor 101 fetches the vector 301, and
It corresponds to 402 in the figure. On the other hand, vector fetch (2) is that the processor 101 fetches the vector 304, and corresponds to 403 in FIG. The processor 101 takes in the two vectors 301 and 304, and then 302 of the two vectors
By comparing the portions 305 and 305, it is possible to determine whether a normal interrupt or an incomplete interrupt has occurred (205). If 302 is compared with 305 and they match (Yes), the processor 101 determines that a normal interrupt has occurred, and performs a normal interrupt operation (206 to 20).
9). Since this normal interrupt operation is the same as the flow of the conventional interrupt processing shown in FIG. 15, detailed description thereof will be omitted. On the other hand, if the parts 302 and 305 are compared and they do not match (N
In o), the processor 101 determines that an incomplete interrupt has occurred, and directly executes the interrupt processing such as vector table access (206) after vector fetching, saving information to the stack (207), etc. Control can be returned to the program that was interrupted by the interrupt.

In the above embodiment, the incomplete interrupt detection circuit 108 constitutes detection means, and the inverter 109 and the selector 112 constitute means for outputting a vector indicating the disappearance of a request.

FIG. 5 is a flow chart showing the operation of the second embodiment of the present invention, and shows the control flow of the processor 101. In the second embodiment, when an incomplete interrupt as shown in FIG. 4 occurs (the judgment of 501 is “Yes”), the interrupt controller 102 causes the processor 101 to activate two consecutive interrupt acceptance bus cycles. For the first interrupt acceptance bus cycle of, the processor 1 only needs to perform internal processing (502) as in the conventional interrupt controller.
No information is sent to 01, but the vector 601 in the format shown in FIG. 6 is sent to the second interrupt acceptance bus cycle. In FIG. 6, a vector 601 is a second interrupt acceptance bus activated by the processor 101.
A bit 602 which is output from the interrupt controller 102 for a cycle and has a configuration indicating whether an incomplete interrupt has occurred, a portion 603 of an address preset by the processor 101, and a first interrupt acceptance bus cycle Of the interrupt request input to the interrupt controller 102 at the time when is activated, that is, a portion 604 in which the priority level of the interrupt request to be serviced is encoded into 3 bits.

Therefore, when an incomplete interrupt with the timing shown in FIG. 4 occurs, the interrupt controller 10
2 is a vector 6 that detects that an incomplete interrupt has occurred and outputs it to the second interrupt acceptance bus cycle 403.
Write “0” in bit 602 of 01 and send it to the processor 101. On the other hand, when a normal interrupt is generated, "1" is written in the bit 602 and sent to the processor 101. Two
Vector taken in the first interrupt acceptance bus cycle
Based on bit 602 of 601 processor 101 can determine whether an incomplete interrupt has occurred (503).
That is, when the bit 602 of the vector 601 obtained in the second interrupt acceptance bus cycle 403 is "1", the processor 101 determines that a normal interrupt has occurred and performs the same processing as the conventional interrupt processing ( 504-507). On the other hand, when the bit 602 is “0”, the processor 101 determines that an incomplete interrupt has occurred and does not perform interrupt processing such as vector table access after vector fetch and saving of information in the stack Can return control directly to the interrupted program.

The processor 101 can use the vector 601 obtained from the interrupt controller 102 to generate an address for accessing an entry in the vector table as shown in FIG.

<Effects of the Invention> As described above, in the present invention, the processor obtains the vector obtained from the interrupt controller by activating the interrupt reception bus cycle in an attempt to accept the interrupt.
Since it is possible to determine whether or not the interrupt is an incomplete interrupt, if the interrupt is an incomplete interrupt, it was interrupted without performing the wasteful processing that was executed by the conventional interrupt processing method. You can directly return to the execution of the original program. Therefore, there is an effect that the throughput of the entire system is improved.

Further, since the interrupt controller of the conventional interrupt processing system has decided to use the service routine of the priority level corresponding to one specific interrupt request input terminal when the incomplete interrupt occurs, Although interrupt request signals from I / O, etc. in the system could not be connected substantially, the present invention allows all interrupt request input terminals of the interrupt controller to be connected in the system.
An effect that an interrupt request signal can be connected from I / O or the like is also obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention, FIG. 2 is a flow chart showing the operation of the first embodiment, FIG. 3 is a block diagram showing the vector format of the first embodiment, and FIG. FIG. 6 is a timing chart showing the incomplete interrupt of the first embodiment, FIG. 5 is a flow chart showing the operation of the second embodiment of the present invention, and FIG. 6 is a block diagram showing the vector format of the second embodiment. FIG. 7 is a block diagram of an address for entry into the vector table of the second embodiment, FIG. 8 is a block diagram showing a concrete configuration of the incomplete interrupt detection circuit of the first embodiment, and FIG. 9 is a conventional example. Figure 10, Figure 10 is a timing diagram showing interrupts in the conventional example, Figure 11 is a block diagram showing the vector format of the conventional example, and Figure 12 is a block diagram of addresses for entry into the conventional vector table. Figure 13 is a timing diagram showing the incomplete interruption in the conventional example, FIG. 14 is a flowchart showing the operation of the conventional example. 101-processor (central processing unit), 102-interrupt controller, 103-input / output device, 108-imperfect interrupt detection circuit, 109-inverter, 112-selector, 113-priority determination circuit.

Claims (1)

(57) [Claims] 1. A central processing unit, an interrupt controller, and a plurality of input / output devices, wherein when an interrupt request from the input / output device is input to the interrupt controller,
The interrupt controller arbitrates interrupt requests from the plurality of input / output devices and outputs an interrupt request signal to the central processing unit, and the central processing unit responds to the interrupt request signal from the interrupt controller to interrupt the interrupt. An information processing system in which an interrupt acceptance bus cycle is activated at least twice in a controller, and the interrupt controller outputs a vector to the central processing unit during the interrupt acceptance bus cycle, wherein the interrupt controller is the central processing unit. Detecting means for detecting that all the interrupt requests from the input / output device to the interrupt controller have disappeared between the time the device receives the interrupt request signal from the interrupt controller and the time when the interrupt reception bus cycle is activated. And based on the detection result of the detecting means, Means for causing the interrupt controller to output a vector different from the vector transmitted in the second interrupt acceptance bus cycle to the interrupt controller in the second interrupt acceptance bus cycle, the central processing unit based on the difference between the two vectors. An information processing system characterized by recognizing disappearance of an interrupt request and terminating the interrupt operation.